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Sl.No Chapter Name MP4 Download Transcript Download
1Introduction: Objectives and Pre-requisitesDownloadPDF unavailable
2Review of digital logicDownloadPDF unavailable
3Timing and Power in digital circuitsDownloadPDF unavailable
4Implementation Costs and MetricsDownloadPDF unavailable
5Example: Audio processingDownloadPDF unavailable
6Example: AlexNetDownloadPDF unavailable
7Architecture cost componentsDownloadPDF unavailable
8Examples of ArchitecturesDownloadPDF unavailable
9Multi-objective OptimizationDownloadPDF unavailable
10Number representationDownloadPDF unavailable
11Scientific notation and Floating pointDownloadPDF unavailable
12Basic FIR filterDownloadPDF unavailable
13Serial FIR filter architecturesDownloadPDF unavailable
14Simple programmable architectureDownloadPDF unavailable
15Block diagrams and SFGsDownloadPDF unavailable
16Dataflow GraphsDownloadPDF unavailable
17Iteration periodDownloadPDF unavailable
18FIR filter iteration periodDownloadPDF unavailable
19IIR filter iteration periodDownloadPDF unavailable
20Computation ModelDownloadPDF unavailable
21Constraint analysis for IPB computationDownloadPDF unavailable
22Motivational examples for IPBDownloadPDF unavailable
23General IPB computationDownloadPDF unavailable
24Sample period calculationDownloadPDF unavailable
25Parallel architectureDownloadPDF unavailable
26Odd-even register reuseDownloadPDF unavailable
27Power consumptionDownloadPDF unavailable
28PipeliningDownloadPDF unavailable
29Pipelining FIR filterDownloadPDF unavailable
30Time-invariant systemsDownloadPDF unavailable
31Valid pipelining examplesDownloadPDF unavailable
32Feedforward cutsetsDownloadPDF unavailable
33Balanced pipelineDownloadPDF unavailable
34Retiming basic conceptDownloadPDF unavailable
35Example and uses of retimingDownloadPDF unavailable
36Resource sharing: adder exampleDownloadPDF unavailable
37Changing iteration periodDownloadPDF unavailable
38Hardware assumptions and constraint analysisDownloadPDF unavailable
39Mathematical formulationDownloadPDF unavailable
40Examples with formulationDownloadPDF unavailable
41Example: Biquad filterDownloadPDF unavailable
42Hardware architectureDownloadPDF unavailable
43Review biquad folding setsDownloadPDF unavailable
44Complete biquad hardwareDownloadPDF unavailable
45DEMO: FFT in Vivado HLSDownloadPDF unavailable
46DEMO: FFT synthesisDownloadPDF unavailable
47Obtaining a folding scheduleDownloadPDF unavailable
48ASAP scheduleDownloadPDF unavailable
49Utilization EfficiencyDownloadPDF unavailable
50ALAP scheduleDownloadPDF unavailable
51Iteration period bound and schedulingDownloadPDF unavailable
52Retiming for schedulingDownloadPDF unavailable
53Blocked schedulesDownloadPDF unavailable
54Overlapped schedulesDownloadPDF unavailable
55Improved blocked scheduleDownloadPDF unavailable
56Allocation, Binding and SchedulingDownloadPDF unavailable
57DEMO: Analyze FFT implementationDownloadPDF unavailable
58DEMO: FFT interfaceDownloadPDF unavailable
59Scheduling: problem formulationDownloadPDF unavailable
60Example: differential equation solverDownloadPDF unavailable
61Heuristic approaches to schedulingDownloadPDF unavailable
62Mathematical formulation DownloadPDF unavailable
63ILP formulationDownloadPDF unavailable
64List schedulingDownloadPDF unavailable
65Hardware modelDownloadPDF unavailable
66Force Directed SchedulingDownloadPDF unavailable
67DEMO: HLS on FFTDownloadPDF unavailable
68DEMO: FFT Simulation and OptimizationDownloadPDF unavailable
69DEMO: CPU interfacingDownloadPDF unavailable
70Software CompilationDownloadPDF unavailable
71Optimization ExamplesDownloadPDF unavailable
72Loop optimizations 1DownloadPDF unavailable
73Loop optimizations 2DownloadPDF unavailable
74Loop optimizations 3DownloadPDF unavailable
75Software pipelining 1DownloadPDF unavailable
76Software pipelining 2DownloadPDF unavailable
77FFT OptimizationDownloadPDF unavailable
78Demo: Vivado setupDownloadPDF unavailable
79Background: CPUs and FPGAsDownloadPDF unavailable
80Demo: Vivado HLS FFT IP ExportDownloadPDF unavailable
81Demo: Vivado ILA and VIO on hardwareDownloadPDF unavailable
82Demo: FFT on FPGA boardDownloadPDF unavailable
83Demo: Simulating SoC and SDKDownloadPDF unavailable
84Background: Understanding ELF filesDownloadPDF unavailable
85On-chip communication basicsDownloadPDF unavailable
86Many-to-Many communicationDownloadPDF unavailable
87AXI bus handshakingDownloadPDF unavailable
88AXI bus (contd)DownloadPDF unavailable
89Demo: Microblaze processor on FPGADownloadPDF unavailable
90Demo: Performance counter AXI peripheralDownloadPDF unavailable
91Demo: HW accelerator for FPGADownloadPDF unavailable
92DMA and arbitrationDownloadPDF unavailable
93Network-on-chip basicsDownloadPDF unavailable
94NoC - topologies and metricsDownloadPDF unavailable
95NoC - routingDownloadPDF unavailable
96NoC - switching and flow controlDownloadPDF unavailable
97Systolic Arrays - BackgroundDownloadPDF unavailable
98Systolic Arrays - ExamplesDownloadPDF unavailable
99CORDIC algorithmDownloadPDF unavailable
100Parallel implementation of FIR filtersDownloadPDF unavailable
101Unfolding TransformationDownloadPDF unavailable
102Lookahead TransformationDownloadPDF unavailable
103Introduction to GPUs and Matrix multiplicationDownloadPDF unavailable