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Sl.No Chapter Name MP4 Download Transcript Download
1Lecture 01: IntroductionDownloadDownload
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2Lecture 02: Octal and Hexadecimal Number SystemsDownloadDownload
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3Lecture 03: Signed and Unsigned Binary Number RepresentationDownloadDownload
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4Lecture 04: Binary Addition and SubtractionDownloadDownload
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5Lecture 05: BCD and Gray Code RepresentationsDownloadDownload
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6Lecture 06: Error Detection and CorrectionDownloadDownload
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7Lecture 07: Logic GatesDownloadDownload
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8Lecture 08: Logic Families to Implement GatesDownloadDownload
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9Lecture 09: Emerging Technologies (Part I)DownloadDownload
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10Lecture 10: Emerging Technologies (Part II)DownloadDownload
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11Lecture 11 : Switching AlgebraDownloadDownload
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12Lecture 12 : Algebraic ManipulationDownloadDownload
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13Lecture 13 : Properties of Switching FunctionsDownloadDownload
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14Lecture 14 : Obtaining Canonical Representations of FunctionsDownloadDownload
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15Lecture 15 : Functional CompletenessDownloadDownload
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16Lecture 16: Minimization Using Karnaugh Maps (Part I)DownloadDownload
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17Lecture 17: Minimization Using Karnaugh Maps (Part II)DownloadDownload
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18Lecture 21: Design of Adders (Part I)DownloadDownload
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19Lecture 22: Design of Adders (Part II)DownloadDownload
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20Lecture 23: Design of Adders (Part III)DownloadDownload
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21Lecture 24: Logic Design(Part I)DownloadDownload
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22Lecture 25: Logic Design(Part II)DownloadDownload
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23Lecture 26: Logic Design(Part III)DownloadDownload
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24Lecture 27: Binary Decision Diagrams (Part I)DownloadDownload
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25Lecture 28: Binary Decision Diagrams (Part II)DownloadDownload
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26Lecture 29: Logic Design using AND-EXOR NetworkDownloadDownload
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27Lecture 30: Threshold Logic and Threshold GatesDownloadDownload
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28Lecture 31: Latches and Flip-Flops (Part I)DownloadDownload
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29Lecture 32: Latches and Flip-Flops (Part II)DownloadDownload
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30Lecture 33: Latches and Flip-Flops (Part III)DownloadDownload
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31Lecture 34: Clocking and Timing (Part I)DownloadDownload
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32Lecture 35: Clocking and Timing (Part II)DownloadDownload
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33Lecture 36: Synthesis of Synchronous Sequential Circuits (Part I)DownloadDownload
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34Lecture 37: Synthesis of Synchronous Sequential Circuits (Part II)DownloadDownload
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35Lecture 38: Synthesis of Synchronous Sequential Circuits (Part III)DownloadDownload
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36Lecture 39: Synthesis of Synchronous Sequential Circuits (Part IV)DownloadDownload
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37Lecture 40: Minimization of Finite State Machines (Part I)DownloadDownload
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38Lecture 42: Design of Registers (Part I)DownloadDownload
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39Lecture 43: Design of Registers (Part II)DownloadDownload
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40Lecture 44: Design of Registers (Part III)DownloadDownload
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41Lecture 45: Design of Counters (Part I)DownloadDownload
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42Lecture 46: Design of Counters (Part II)DownloadDownload
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43Lecture 47: Digital-to-Analog Converter (Part I)DownloadDownload
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44Lecture 48: Digital-to-Analog Converter (Part II)DownloadDownload
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45Lecture 49: Analog-to-Digital Converter (Part I)DownloadDownload
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46Lecture 50: Analog-to-Digital Converter (Part II)DownloadDownload
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47Lecture 51: Analog-to-Digital Converter (Part III)DownloadDownload
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48Lecture 52: Asynchronous Sequential Circuits (Part I)DownloadDownload
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49Lecture 53: Asynchronous Sequential Circuits (Part II)DownloadDownload
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50Lecture 54: Algorithmic State Machine (ASM) ChartDownloadDownload
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51Lecture 55 : Testing of Digital CircuitsDownloadDownload
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52Lecture 56 : Fault ModelingDownloadDownload
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53Lecture 57 : Test Pattern GenerationDownloadDownload
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54Lecture 58 : Design for TestabilityDownloadDownload
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55Lecture 59 : Built-in Self-Test (Part I)DownloadDownload
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56Lecture 60 : Built-in Self-Test (Part II)DownloadDownload
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