Modules / Lectures
Module NameDownloadDescriptionDownload Size
IntroductionModule 1module1891 kb
Scheduling, Allocation and BindingModule 2module21136 kb
Logic Optimization and SynthesisModule3module31210 kb
Temporal LogicModule4module4625 kb
Verification TechniquesModule5module51026 kb
Binary Decision DiagramModule6module6583 kb
Introduction to Digital TestingModule7module71275 kb
Fault Simulation and Testability MeasuresModule8module81372 kb
Combinational Circuit Test Pattern GenerationModule9module9794 kb
Sequential Circuit Testing and Scan ChainsModule10module10931 kb
Built in Self test (BIST)Module11module11725 kb
Module NameDownloadDescriptionDownload Size
IntroductionAssignment IAssignment I64 kb
Scheduling, Allocation and BindingAssignment IIAssignment II9 kb
Logic Optimization and SynthesisAssignment IIIAssignment III63 kb
Temporal LogicAssignment IVAssignment IV34 kb
Verification TechniquesAssignment VAssignment V22 kb
Binary Decision DiagramAssignment VIAssignment VI42 kb
Introduction to Digital TestingAssignment VIIAssignment VII64 kb
Fault Simulation and Testability MeasuresAssignment VIIIAssignment VIII69 kb
Combinational Circuit Test Pattern GenerationAssignment IXAssignment IX64 kb
Sequential Circuit Testing and Scan ChainsAssignment XAssignment X68 kb
Built in Self test (BIST)Assignment XIAssignment XI15 kb


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