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Course Co-ordinated by IIT Kharagpur
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Prof. Indranil Sengupta
IIT Kharagpur

 

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B.E/B.Tech,M.E/M.Teach,M.S,PhD,

1. J. Bhasker, Verilog HDL Synthesis: A Practical Primer, B. S. Publications, 1998.
2. M. D. Ciletti, “Advanced VLSI Design with the Verilog HDL, Prentice-Hall of India, 2005.

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