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Course Co-ordinated by IIT Kharagpur
Coordinators
 
Prof. Indranil Sengupta
IIT Kharagpur

 

Untitled Document

This course covers lessons on verilog,synthesis,backend design and testing part.

S.NO
Topic
1
 Introduction                
2
 Verilog: Part - I           
3
 Verilog: Part - II          
4
 Verilog: Part - III         
5
 Verilog: Part - IV          
6
 Verilog: Part - V           
7
 Verilog: Part - VI          
8
 Synthesis: Part - I         
9
 Synthesis: Part - II        
10
 Synthesis: Part - III       
11
 Synthesis: Part - IV        
12
 Synthesis: Part - V         
13
 Synthesis: Part - VI        
14
 Synthesis: Part - VII       
15
 Backend Design: Part - I    
16
 Backend Design: Part - II   
17
 Backend Design: Part - III  
18
 Backend Design: Part - IV   
19
 Backend Design Part - V     
20
 Backend Design Part - VI    
21
 Backend Design Part - VII   
22
 Backend Design Part - VIII  
23
 Backend Design Part - IX    
24
 Backend Design Part - X     
25
 Backend Design Part - XI    
26
 Backend Design Part - XII   
27
 Backend Design Part - XIII  
28
 Backend Design Part - XIV   
29
 Backend Design Part - XV    
30
 Testing Part - I            
31
 Testing Part - II           
32
 Testing Part - III          
33
 Testing Part - IV           
34
 Testing Part - V            
35
 Testing Part - VI     
   
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