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This course is about the automatic generation of digital circuits from high-level descriptions. Modern electronic systems are specified in Hardware Description Languages and are converted automatically into digital circuits. We will introduce the VHDL Hardware Description Language, and follow it up with a discussion of the basics of synthesis topics including High-level Synthesis, FSM Synthesis, Retiming, and Logic Synthesis.


Week

Topics

1.

Course Outline and Introduction to VLSI Design Automation

2.

†Hardware Description Languages and VHDL

3.

Specifying Behaviour and Structure in HDL

4.

Introduction to High-level Synthesis

5.

Compiler Transformations in High-level Synthesis

6.

Scheduling

7.

Register Allocation and Timing Issues

8.

Finite State Machine Synthesis

9.

†The Retiming Problem

10.

Introduction to Logic Synthesis and Binary Decision Diagrams

11.

Two-level and Multi-level Logic Optimisation

12.

Technology Mapping and Timing Analysis

Pre-requisite courses: 1. Digital Design (or Logic Design) 2. Data Structuresl


Giovanni de Micheli, Synthesis and Optimization of Digital Circuits, McGraw Hill
 
 

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