﻿1 00:01:01,830 --> 00:01:08,830 Today we are going to discuss about what is called an input output or I/O subsystem. You 2 00:01:11,010 --> 00:01:18,010 know that in any computer system, a number of input output devices including say keyboard, 3 00:01:19,960 --> 00:01:26,940 video monitor, printer then again the hard disc is also considered as an input output 4 00:01:26,940 --> 00:01:29,220 or I/O system. 5 00:01:29,220 --> 00:01:36,090 Now when we talk about this I/O subsystem, it is the unit which interacts with the input 6 00:01:36,090 --> 00:01:43,090 output device. So if you look at any computer system as we have seen earlier that in a computer 7 00:01:43,320 --> 00:01:50,119 system you have at the heart of the computer system which is the CPU and the CPU is connected 8 00:01:50,119 --> 00:01:56,869 with a number of input output systems in addition to the main memory. So I will have a number 9 00:01:56,869 --> 00:02:03,869 of buses few of the lines taken together will be called control bus then address bus and 10 00:02:04,960 --> 00:02:11,960 data bus. So suppose this represents the control bus, second set of lines represents the address 11 00:02:13,730 --> 00:02:20,730 bus and the third set of line may represent the data bus. 12 00:02:21,970 --> 00:02:28,970 So whenever you connect to any input output device, you have to have an I/O interface 13 00:02:32,130 --> 00:02:39,130 unit. This is what we will call as input output interface and this input output interface 14 00:02:45,810 --> 00:02:52,810 actually connect with the input output device and as we said that this device can be of 15 00:02:53,390 --> 00:03:00,370 various forms. So actually this input output interface, this is what interfaces the device 16 00:03:00,370 --> 00:03:06,200 with the CPU. So input output device has two interface unit will have the connection with 17 00:03:06,200 --> 00:03:11,170 the control bus. It will also have connection with the address bus and it will have the 18 00:03:11,170 --> 00:03:18,170 connection with the data bus, so the connection will be like this. Now when we talk about 19 00:03:21,640 --> 00:03:28,640 an I/O subsystem, we can have three different kinds of I/O. The first kind of I/O is called 20 00:03:29,650 --> 00:03:36,650 programmed I/O that means the input output device is under direct control of the CPU, 21 00:03:45,650 --> 00:03:52,410 so any software which has to be executed to access the input output device will be executed 22 00:03:52,410 --> 00:03:59,410 by the CPU. I/O operation will be initiated by the CPU, it will also be terminated by 23 00:03:59,510 --> 00:04:06,510 the CPU. The second kind of I/O that we can have is called interrupt I/O. In case of interrupt 24 00:04:14,800 --> 00:04:20,880 I/O whenever an I/O operation is to be initiated, the CPU simply informs the I/O interface to 25 00:04:20,880 --> 00:04:26,110 start the I/O operation. At the end of the I/O operation the I/O interface will interrupt 26 00:04:26,110 --> 00:04:33,080 the CPU informing that I/O operation is complete. Now whatever the CPU has to do with that data 27 00:04:33,080 --> 00:04:39,190 either received from the I/O or sent to the I/O that the CPU can do now and the third 28 00:04:39,190 --> 00:04:46,190 kind of I/O is what is called DMA or direct memory access and in this case the data is 29 00:04:47,900 --> 00:04:53,099 transferred between the input output device and the main memory directly by the DMA unit. 30 00:04:53,099 --> 00:04:57,110 The CPU does not come into picture at all. 31 00:04:57,110 --> 00:05:04,060 So if I go for this programmed I/O in that case what will be the nature of the I/O interface 32 00:05:04,060 --> 00:05:10,630 unit? If I expand this I/O interface unit, the I/O interface unit will have a number 33 00:05:10,630 --> 00:05:17,630 of components. The first component will be that since every I/O device will have an unique 34 00:05:20,140 --> 00:05:27,140 address in the system, so I have to have an unit called address decoder. So in this I/O 35 00:05:30,770 --> 00:05:37,770 interface unit, I will have an unit called address decoder and you might be knowing that there are some other 36 00:05:43,640 --> 00:05:50,640 units which are known as say in register, out register. Then I have to have what is 37 00:05:59,490 --> 00:06:06,490 called a command word and I have to have another one called status word. So in this I/O interface 38 00:06:17,570 --> 00:06:22,919 unit if I go for the programmed I/O kind of configuration, the I/O interface unit will 39 00:06:22,919 --> 00:06:28,110 have an address decoder, it will have an in register so that for any inputting operation 40 00:06:28,110 --> 00:06:33,860 the data which is transferred from the input device is stored in the in register then the 41 00:06:33,860 --> 00:06:37,390 CPU can read the data from the in register. 42 00:06:37,390 --> 00:06:42,529 Similarly for an output device when a data is to be transmitted to the out or stored 43 00:06:42,529 --> 00:06:47,539 in the output device or is to be sent to the output device, the CPU will write data into 44 00:06:47,539 --> 00:06:53,320 out register then from the out register it will go to the device. Common register is 45 00:06:53,320 --> 00:06:59,620 mostly used to configure the I/O operation that is at what speed the I/O should operate, 46 00:06:59,620 --> 00:07:05,330 what should be the word length or how many bits will contain the data, what will be the 47 00:07:05,330 --> 00:07:11,010 error correcting message all those informations will be configured in the command register. 48 00:07:11,010 --> 00:07:18,010 The status register will inform the status of the I/O device. So these are the kind of 49 00:07:18,750 --> 00:07:24,560 things which you might have used in your microprocessor course say for example if you want to connect 50 00:07:24,560 --> 00:07:30,020 an USART that is universal synchronous asynchronous receiver transmitter so in that case what 51 00:07:30,020 --> 00:07:34,570 we have to do is we have program what is the baud rate that is at which rate the data is 52 00:07:34,570 --> 00:07:35,770 to be transmitted. 53 00:07:35,770 --> 00:07:41,169 You also have to program that how many start bits or how many stop bits you want to have, 54 00:07:41,169 --> 00:07:45,610 what is the data length whether a character will consist of 7 bits or a character will 55 00:07:45,610 --> 00:07:50,169 consist of 8 bits, all those informations are to be stored or to be written into the 56 00:07:50,169 --> 00:07:57,169 command register and then only the I/O interface will act accordingly. Similarly the status 57 00:07:57,390 --> 00:08:04,390 register will be used, suppose the CPU wants to read a data from an input device, so firstly 58 00:08:05,029 --> 00:08:11,120 by configuring the command register, it configures that in which way the data communication will 59 00:08:11,120 --> 00:08:16,010 take place then the status register will tell that whether the data which is to be read 60 00:08:16,010 --> 00:08:23,010 is available in the in register or not that is whether this device is ready with the data. 61 00:08:24,760 --> 00:08:30,060 So that information will come from the status resistor and from the status register whenever 62 00:08:30,060 --> 00:08:33,830 the CPU finds that the data is ready in the in register, the CPU can read the data from 63 00:08:33,830 --> 00:08:40,520 in register. So for doing this after sending a command to the command resistor, what the 64 00:08:40,520 --> 00:08:45,550 CPU has to do is the CPU has to remain in a loop always checking the condition of the 65 00:08:45,550 --> 00:08:50,580 status register whether the data is ready or not. So only when it finds that the data 66 00:08:50,580 --> 00:08:55,450 is ready, it reads the data from the in register and comes out. 67 00:08:55,450 --> 00:09:01,010 So this is why this kind of I/O operations is called program I/O because all the input 68 00:09:01,010 --> 00:09:05,580 output operations are directly done under the direct supervision of the CPU through 69 00:09:05,580 --> 00:09:12,550 some program. Now each of this in register, out register, command register or status resistor 70 00:09:12,550 --> 00:09:19,550 they will have different addresses that means I have to have some connection from the address 71 00:09:19,970 --> 00:09:26,970 decoder to the in register. I have to have a connection from the address decoder to the 72 00:09:27,220 --> 00:09:32,080 out register, I have to have a connection from the address decoder to the command register, 73 00:09:32,080 --> 00:09:39,080 I also have to have a connection from the address decoder to the address register so 74 00:09:40,350 --> 00:09:46,550 that I can have unique address for each of these registers. In some of the I/O interfaces 75 00:09:46,550 --> 00:09:51,960 you will find that the in and out registers they have the same address. 76 00:09:51,960 --> 00:09:57,970 Similarly command and status registers they have the same address. There the idea is suppose 77 00:09:57,970 --> 00:10:04,970 in out registers they have some address say AA, AA hexadecimal so with that AA address 78 00:10:07,160 --> 00:10:13,110 if I want to write anything, the data will always come in the in register. If I want 79 00:10:13,110 --> 00:10:20,110 to read anything from A address, the data will be read from the out register sorry it 80 00:10:20,770 --> 00:10:27,770 is opposite. Similarly here suppose this has an address of AB both command register and 81 00:10:29,340 --> 00:10:36,270 status register, so with address AB if anything is written into this it will be written into 82 00:10:36,270 --> 00:10:42,970 command register. If anything is read by the CPU with address AB then the information will 83 00:10:42,970 --> 00:10:48,870 be read from the status register that means these registers are unidirectional. To one 84 00:10:48,870 --> 00:10:55,870 register you can only write, another register can only be read. Yes, may not be. I am taking 85 00:10:59,780 --> 00:11:05,760 a specific case, there are a number of situations when the I/O interface unit will have much 86 00:11:05,760 --> 00:11:09,500 more number of registers than this. 87 00:11:09,500 --> 00:11:16,500 This I/O interface unit can have an internal memory say for example if I want to design 88 00:11:17,110 --> 00:11:22,490 an I/O interface for interacting with the key board, for interacting with the video 89 00:11:22,490 --> 00:11:29,490 unit in such cases the I/O interface unit will have some internal memory in addition 90 00:11:30,080 --> 00:11:37,080 to these registers. So this is just a particular example, a very simple example the system 91 00:11:37,800 --> 00:11:43,550 can be complicated further. Not only that, the I/O interface unit can be a processor 92 00:11:43,550 --> 00:11:50,550 itself, this itself can be a sequential machine. So in some cases if our I/O operation is very 93 00:11:50,830 --> 00:11:57,830 very complex in that case such simple interface may not be sufficient. So for every I/O operation 94 00:12:00,270 --> 00:12:05,850 the task can be given to the I/O interface unit or I/O subsystem, the subsystem will 95 00:12:05,850 --> 00:12:12,190 take care of the task in its entirety, it will not depend upon the CPU. In such cases 96 00:12:12,190 --> 00:12:19,190 its I/O interface unit has to be a processor by itself. In many cases such units are called 97 00:12:21,320 --> 00:12:26,220 I/O channels, I/O channel. 98 00:12:26,220 --> 00:12:33,220 DMA is a kind of such channel, I will come to that. So in this case this in out registers, 99 00:12:36,720 --> 00:12:41,630 command registers and status registers through this you can control all the input output 100 00:12:41,630 --> 00:12:48,630 operations. So obviously this address decoder it will have a connection from the address 101 00:12:49,320 --> 00:12:56,130 bus. All these registers in registers, out registers, command register and status register 102 00:12:56,130 --> 00:13:03,130 they will have connection with the data bus so I can put it this way and at the same time, 103 00:13:12,410 --> 00:13:19,290 the control signals which come, this control signals also propagate to these registers 104 00:13:19,290 --> 00:13:23,170 because among the control signals we have the read signal, write signal and all those 105 00:13:23,170 --> 00:13:30,170 things so whenever a read operation is to be performed this in register has to be activated. 106 00:13:31,400 --> 00:13:35,430 Whenever an output operation is to be performed or write operation is to be performed either 107 00:13:35,430 --> 00:13:40,440 the out register or the command register will be activated depending upon what address comes 108 00:13:40,440 --> 00:13:47,440 from the address decoder. So if you expand this I/O interface unit, it will look like 109 00:13:49,110 --> 00:13:56,110 this and here I will have the I/O device 110 00:14:06,050 --> 00:14:12,400 and this kind of interface unit is mostly suitable for programmed I/O kind of operation. 111 00:14:12,400 --> 00:14:19,400 Now as I said that there is another kind of I/O operation which we call as interrupt I/O. 112 00:14:24,840 --> 00:14:31,840 In case of interrupt I/O what is assumed is whenever some device needs some service, so 113 00:14:33,070 --> 00:14:38,310 in this case the serve was the initiated by the CPU, it was terminated by the CPU. In 114 00:14:38,310 --> 00:14:44,460 case of interrupt I/O we assume that whenever a device needs some service, the device interrupts 115 00:14:44,460 --> 00:14:51,460 the CPU. Now the actions or the services for different devices are different. The service 116 00:14:53,970 --> 00:15:00,740 needed by a hard disc will be different from the service needed by a keyboard or the service 117 00:15:00,740 --> 00:15:05,560 needed by a keyboard will be different from the service needed by an output device like 118 00:15:05,560 --> 00:15:12,560 printer. So in the CPU, what the CPU will do is on getting an interrupt it will identify 119 00:15:12,620 --> 00:15:19,110 that which interrupt it is and following that identification it will execute a program which 120 00:15:19,110 --> 00:15:25,400 is called an interrupt service student and it is this interrupt service student which 121 00:15:25,400 --> 00:15:30,240 meets the requirement of the device. 122 00:15:30,240 --> 00:15:36,550 So whenever any I/O device needs some service from the CPU, it is the responsibility of 123 00:15:36,550 --> 00:15:43,550 the I/O device to put the request, service request in the form of an interrupt. So I 124 00:15:45,120 --> 00:15:51,200 can have two different kinds of interrupts. One kind of interrupt is called a priority 125 00:15:51,200 --> 00:15:58,200 interrupt which you have done with a 8085 microprocessor where you might be knowing that there are 126 00:16:04,540 --> 00:16:10,650 different types of interrupts 7.5, 6.5, 5.5 trap and all these things and there is another 127 00:16:10,650 --> 00:16:17,410 interrupt which is called INTR. All these interrupt lines have got different priorities, 128 00:16:17,410 --> 00:16:24,410 trap has got the highest priority, INTR has got the lowest priority or among the vectored 129 00:16:24,670 --> 00:16:30,790 interrupts trap has got the highest priority and RST 5.5 has got the lowest priority. 130 00:16:30,790 --> 00:16:37,790 See if I go for this priority interrupts what are the units that we need? Firstly because 131 00:16:38,440 --> 00:16:44,020 a number of devices can put the interrupts simultaneously to the CPU, if the interrupts 132 00:16:44,020 --> 00:16:48,610 are not simultaneous then I don’t have any problem. If only one device puts an interrupt 133 00:16:48,610 --> 00:16:54,050 at a say, at a time then that interrupt can immediately be acknowledged and serviced but 134 00:16:54,050 --> 00:17:01,050 the problem comes when more than one devices interrupt simultaneously. In that case a decision 135 00:17:01,400 --> 00:17:08,400 has to be made that out of all these devices which device has to be serviced first. I have 136 00:17:08,929 --> 00:17:15,929 to set some interrupt priority level and to do this what I need is a priority encoder 137 00:17:24,339 --> 00:17:31,339 so this is what is known as a priority encoder. 138 00:17:36,740 --> 00:17:43,740 Priority encoder has got a number of input interrupt lines; these lines have got different 139 00:17:49,350 --> 00:17:56,350 priority levels. Now out of all these lines if more than one line’s are active simultaneously 140 00:17:57,870 --> 00:18:01,700 then the line which has got highest priority among them will be selected and passed to 141 00:18:01,700 --> 00:18:08,700 the output of the priority encoder. Now along with this, what is needed is because now I 142 00:18:09,549 --> 00:18:16,549 have a number of devices connected together and many of them can give interrupt simultaneously, 143 00:18:16,690 --> 00:18:23,690 when the interrupt is acknowledged by the CPU then the device whose interrupt is acknowledged 144 00:18:24,749 --> 00:18:30,700 that the device must know so that the device can start operation. So along with this priority 145 00:18:30,700 --> 00:18:37,700 encoder, we also have to have another unit, the reverse unit which we call as a decoder 146 00:18:41,950 --> 00:18:48,809 so this is a simple decoder. 147 00:18:48,809 --> 00:18:54,549 The devices will give an interrupt suppose this is, I name this as interrupt request 148 00:18:54,549 --> 00:19:01,549 line and this is the interrupt request line zero. When an acknowledgment comes, the acknowledgment 149 00:19:02,629 --> 00:19:08,149 should also reach the device and the acknowledgment will be generated by the decoder unit, so 150 00:19:08,149 --> 00:19:15,149 this is interrupt acknowledgment zero. Similarly we will have interrupt request one, interrupt 151 00:19:25,210 --> 00:19:31,429 acknowledgment one which will also be generated by the decoder will go to the device which 152 00:19:31,429 --> 00:19:37,210 is connected to this interrupt request one line, so this is interrupt acknowledgment 153 00:19:37,210 --> 00:19:40,999 one. 154 00:19:40,999 --> 00:19:47,999 Similarly if there are say m number of devices then this will be interrupt request m and 155 00:19:54,340 --> 00:20:01,340 similarly an interrupt acknowledgment m will be generated by the decoder. Now before an 156 00:20:05,049 --> 00:20:12,049 interrupt is actually entertain by the CPU, the CPU has to compare what is the level of 157 00:20:12,169 --> 00:20:18,429 the interrupt which is coming from a device with respect to the interrupt level or priority 158 00:20:18,429 --> 00:20:25,429 level of a task which is under execution. So if the CPU is executing a task of which 159 00:20:25,869 --> 00:20:32,869 the interrupt level is say 5, now while that task has been executed if another device whose 160 00:20:34,669 --> 00:20:41,249 interrupt level is say 2 puts an interrupt then if the priority of interrupt 2 is less 161 00:20:41,249 --> 00:20:48,119 than the priority interrupt 5 then this new interrupt will not be accepted. Whereas if 162 00:20:48,119 --> 00:20:54,519 the priority of 2 is greater than the priority of interrupt level 5 then the new interrupt 163 00:20:54,519 --> 00:21:01,519 will be accepted, so I have to have some memory element which will tell me that what is the 164 00:21:02,830 --> 00:21:09,830 current priority level of a job which is under execution. So this gives you the current priority 165 00:21:14,539 --> 00:21:21,539 level. I have to compare this current priority level with the new priority with which an 166 00:21:28,149 --> 00:21:35,149 interrupt has come. So I must need a comparator, one of the inputs to the comparator will be 167 00:21:37,950 --> 00:21:44,950 from the current priority level and the other input to this comparator will be from the 168 00:21:48,340 --> 00:21:55,340 new interrupt priority level that has come. So this is a comparator let me call this input 169 00:22:00,460 --> 00:22:06,190 as A, this input as B. 170 00:22:06,190 --> 00:22:13,190 So I will have an output which will actually give the interrupt request to the CPU. So 171 00:22:17,539 --> 00:22:24,210 this is the actual interrupt request to the CPU and I will generate this interrupt request 172 00:22:24,210 --> 00:22:31,210 following some logic. So my logic will be that if a priority level low indicates a high 173 00:22:31,480 --> 00:22:37,679 priority, I can have different types of logic. Suppose at the input I have 8 devices, so 174 00:22:37,679 --> 00:22:42,999 I can have priority levels from 0 to 7. I can assume that a priority level zero is the 175 00:22:42,999 --> 00:22:46,840 maximum priority or highest priority or I can also assume that a priority level 7 is 176 00:22:46,840 --> 00:22:52,759 the highest priority. So accordingly this comparator has to be set. So if I assume that 177 00:22:52,759 --> 00:22:59,759 the lowest priority level indicates the priority is actually high that means whenever B is 178 00:23:00,159 --> 00:23:07,159 less than A then only this interrupt will be generated. So it will be an output whether 179 00:23:09,249 --> 00:23:16,249 B is less than A or not. So if B is less than A, then only you are generating an interrupt. 180 00:23:19,529 --> 00:23:23,940 So obviously this interrupt has to be accepted by the CPU and when the interrupt is accepted 181 00:23:23,940 --> 00:23:28,980 by the CPU in turn the CPU will give an interrupt acknowledgment. 182 00:23:28,980 --> 00:23:35,759 On getting an interrupt acknowledgment that means the CPU is now going to take the new 183 00:23:35,759 --> 00:23:42,440 task. So the current priority level which was set in this current priority register 184 00:23:42,440 --> 00:23:47,320 that has to be changed, it has to get this new priority level. So along with coming to 185 00:23:47,320 --> 00:23:54,320 this comparator, this priority encoder output should go to the current priority level register 186 00:23:55,239 --> 00:24:02,239 and this has to be loaded. So I have to have a load input to this and this has to be loaded 187 00:24:03,179 --> 00:24:08,409 whenever an interrupt acknowledgment comes, so interrupt acknowledgment will be given 188 00:24:08,409 --> 00:24:15,409 by the CPU. This interrupt acknowledgment will give a load input to the current priority 189 00:24:19,869 --> 00:24:26,529 level, when this current priority can be loaded into the current priority register and at 190 00:24:26,529 --> 00:24:33,529 the same time whenever this acknowledgement comes, it also has to give a signal to the 191 00:24:33,590 --> 00:24:40,590 decoder, decoder makes use of this current priority to generate, to activate one of the 192 00:24:46,730 --> 00:24:51,809 decoder output lines. 193 00:24:51,809 --> 00:24:56,730 So whenever this acknowledgment comes from the CPU that means the new interrupt is being 194 00:24:56,730 --> 00:25:02,029 accepted, when this new interrupt is accepted, the current priority is changed. The new priority 195 00:25:02,029 --> 00:25:08,830 value along with this interrupt acknowledgment signal that comes to the decoder and accordingly 196 00:25:08,830 --> 00:25:15,830 the decoder generates an interrupt acknowledgment signal which goes to the device which is being 197 00:25:16,859 --> 00:25:23,859 selected. So this is the total scheme of an interrupt controller, if I want to use the 198 00:25:28,279 --> 00:25:35,279 priority interrupt scheme. So this whole thing is the priority interrupt controller. Yes. 199 00:25:40,840 --> 00:25:47,840 That is what I have assumed, it can be reverse also. For this case interrupt level zero is 200 00:25:53,450 --> 00:25:59,970 of highest priority. I can have the reverse also, I can make interrupt level 7 to be the 201 00:25:59,970 --> 00:26:06,970 highest priority but in this case this comparator output will be changed instead of B less than 202 00:26:22,309 --> 00:26:29,309 A, I have to make it B greater than A. That has to be done by the device itself, device 203 00:26:39,519 --> 00:26:40,299 controller has to take care of that. 204 00:26:40,299 --> 00:26:44,779 Say in the device controller, the device controller will put an interrupt request then it has 205 00:26:44,779 --> 00:26:49,909 to wait for an interrupt acknowledgment, until and unless it gets the interrupt acknowledgment 206 00:26:49,909 --> 00:26:56,549 the interrupt request line should be kept high that has to be taken care of by the device 207 00:26:56,549 --> 00:27:02,119 controller in this configuration, correct. However in case of 8085, such a type of thing 208 00:27:02,119 --> 00:27:09,119 is implemented in 8085. So if two interrupt comes say RST 7.5 and RST 5.5 simultaneously 209 00:27:10,700 --> 00:27:17,700 then RST 5.5 goes into an internal register. So after 7.5 is serviced, 5.5 will also be 210 00:27:21,779 --> 00:27:28,779 serviced. There are additional interrupt controller chips also. Yes, some question from this side. 211 00:27:35,409 --> 00:27:42,090 This is the interrupt acknowledgment, the other one is the current priority level. So 212 00:27:42,090 --> 00:27:48,440 the logic is because this decoder has to activate one of the decoder outputs. Which decoder 213 00:27:48,440 --> 00:27:55,440 output has to be activated, that depends upon this priority which has been accepted. So 214 00:27:57,480 --> 00:28:02,320 that is why it needs this input as well as this interrupt acknowledgment both are needed 215 00:28:02,320 --> 00:28:09,320 to generate an output signal high. The other kind of interrupt which can be used 216 00:28:10,600 --> 00:28:17,600 is what is called a Daisy chaining. 217 00:28:31,019 --> 00:28:35,799 In case of Daisy chaining we don’t have such a complicated circuit. Daisy chaining 218 00:28:35,799 --> 00:28:42,799 concept is very simple, say I have a set of data lines which are connected to the CPU, 219 00:28:44,960 --> 00:28:51,960 I have a single interrupt request line. So these are the data lines or data bus and this 220 00:28:54,059 --> 00:29:01,059 is the interrupt request line, in turn an interrupt acknowledgment will come from the 221 00:29:04,820 --> 00:29:11,820 CPU. I will connect a number of devices on the system. See this is device number 0, I 222 00:29:22,249 --> 00:29:29,249 have device number 1 like this, I will have see device number m. The Daisy chaining concept is whenever a device 223 00:29:47,340 --> 00:29:54,340 puts an interrupt, all the interrupts are connected to the same interrupt request line. 224 00:29:55,840 --> 00:30:02,840 So I can have some wired or kind of connection. All the devices are connected to the same 225 00:30:05,460 --> 00:30:12,460 data bus and this is usual, there is nothing special about it. What is special is the way 226 00:30:17,499 --> 00:30:24,499 the interrupt acknowledgment signal is connected. What is done is whenever the CPU gives an 227 00:30:25,220 --> 00:30:31,009 interrupt acknowledgment, the acknowledgment goes through the first device. From the first 228 00:30:31,009 --> 00:30:37,950 device, the first device gives an interrupt acknowledgment output signal, this output 229 00:30:37,950 --> 00:30:44,950 is connected to the interrupt acknowledgment input of the next device and this way it continues. 230 00:30:47,049 --> 00:30:53,090 The device m will get the interrupt acknowledgment from device m minus 1. 231 00:30:53,090 --> 00:30:58,489 Similarly device m will give an interrupt acknowledgment out signal which will go to 232 00:30:58,489 --> 00:31:05,489 device m plus 1. So this way it continues. For any device say device j the logic is like 233 00:31:08,369 --> 00:31:15,369 this, interrupt acknowledgment of j will be active provided you get an interrupt acknowledgment 234 00:31:20,999 --> 00:31:27,999 out from device j minus 1 and interrupt request of j minus 1 and enable j minus 1, this is 235 00:31:44,119 --> 00:31:51,119 not true. So the concept is every device will have an enable signal, so device can put the 236 00:31:53,210 --> 00:32:00,210 request only when the corresponding device is enabled. Now because the acknowledgment 237 00:32:01,119 --> 00:32:07,229 signal moves from one device to another device in the form of a chain, so we find that this 238 00:32:07,229 --> 00:32:14,229 device one can get an acknowledgment signal from device zero only if there was an interrupt 239 00:32:15,499 --> 00:32:22,080 to the CPU. The CPU gives an interrupt acknowledgment signal, first is it reaches the device zero 240 00:32:22,080 --> 00:32:29,080 but for device zero the condition is something like this, enable of device zero and interrupt 241 00:32:29,749 --> 00:32:34,379 request of device zero inward of this if this is true. 242 00:32:34,379 --> 00:32:41,190 This means two things either the device was not enabled or the device was enabled but 243 00:32:41,190 --> 00:32:48,190 it did not put the interrupt. Only in this case the acknowledgment signal will reach 244 00:32:49,470 --> 00:32:56,409 device one from device zero and the same logic follows. Acknowledgment signal will reach 245 00:32:56,409 --> 00:33:03,409 device two from device one if this is true for device one. Similarly device one can generate 246 00:33:05,749 --> 00:33:10,279 an output acknowledgment if it gets an input acknowledgment and the input acknowledgment 247 00:33:10,279 --> 00:33:17,279 can come from device zero if this is true for devices zero. So we find that the acknowledgment 248 00:33:18,690 --> 00:33:24,570 signal flows from one device to another device in the form of a chain. So that is why it 249 00:33:24,570 --> 00:33:31,570 is called a Daisy chaining priority interrupt scheme and here of course some priority is 250 00:33:31,789 --> 00:33:38,669 in built because the device which is nearest to the CPU has the highest priority. Isn’t 251 00:33:38,669 --> 00:33:45,669 it? Suppose both device zero and device one both of them put interrupts simultaneously. 252 00:33:46,009 --> 00:33:52,999 Then because device zero is enabled and it has put the request so ireq and enable and 253 00:33:52,999 --> 00:33:58,940 these two invert it it becomes zero that means device one does not get the acknowledgment 254 00:33:58,940 --> 00:34:01,879 signal. 255 00:34:01,879 --> 00:34:06,960 So device zero can start the operation but device one cannot start the operation. So 256 00:34:06,960 --> 00:34:13,030 some priority is already in built in the scheme that is a device which is nearest to the CPU 257 00:34:13,030 --> 00:34:20,030 will get the highest priority, device which is farthest from the CPU will get the lowest priority. You have to short this. 258 00:34:34,510 --> 00:34:40,050 No, actually these adapters are like that. If you connect it, it will be through this, 259 00:34:40,050 --> 00:34:46,760 if you disconnect it in that case that will be shorted, that is how the adapters are made. 260 00:34:46,760 --> 00:34:53,760 In fact this kind of scheme was used in, have you seen the earlier HP machines, HPIB called 261 00:34:57,109 --> 00:35:04,109 HP Hewlett Packard interface bus or something like this. HPIB was using this kind of scheme, 262 00:35:06,770 --> 00:35:11,560 that is any number of devices you just connect one device to the other device by a… that’s 263 00:35:11,560 --> 00:35:18,560 all. You can connect any number of devices on the system. 264 00:35:18,950 --> 00:35:25,950 Coming to the other kind of I/O operation that is DMA or direct memory access. Now in 265 00:35:27,270 --> 00:35:34,190 this earlier scheme whether we go for programmed I/O or an interrupt I/O or basic operation 266 00:35:34,190 --> 00:35:37,930 is to transfer the data from the memory to a device or getting the data from a device 267 00:35:37,930 --> 00:35:44,930 storing it into memory. In case of a programmed I/O, the CPU itself will take the initiative 268 00:35:45,400 --> 00:35:52,400 to read a data from a memory, write that into an output device or read a data from an input 269 00:35:53,220 --> 00:36:00,220 device and write it into memory. That means the data has to be first read by the CPU then 270 00:36:00,760 --> 00:36:05,400 only it has to be given to the proper destination, transferred to the proper destination and 271 00:36:05,400 --> 00:36:11,620 that is through both in case of programmed I/O as well as interrupt I/O. In case of programmed 272 00:36:11,620 --> 00:36:18,160 I/O the initiative is taken by the CPU, in case of interrupt I/O the interrupt signal 273 00:36:18,160 --> 00:36:23,710 tells that when that action has to be performed but the action is done by the CPU. In case 274 00:36:23,710 --> 00:36:29,440 of DMA the concept is slightly different. Whenever you have to transfer some data, may 275 00:36:29,440 --> 00:36:35,460 be from an input device to the memory or from memory to the I/O device in that case the 276 00:36:35,460 --> 00:36:38,440 CPU does not come into picture. 277 00:36:38,440 --> 00:36:44,090 So basic concept is whatever operation that was to be done by the CPU is now done by a 278 00:36:44,090 --> 00:36:51,090 separate controller which is the DMA controller. So whenever some device puts a request to 279 00:36:51,740 --> 00:36:58,550 transfer some data from the device memory to the main memory, the device puts a request 280 00:36:58,550 --> 00:37:05,550 signal to the DMA controller. In turn DMA controller gives a signal to the CPU that 281 00:37:08,270 --> 00:37:15,270 it wants to perform some DMA operation. On getting that signal the CPU gets a DMA acknowledgment 282 00:37:16,160 --> 00:37:21,470 and what is done after the DMA acknowledgment? Whenever the CPU generates a DMA acknowledgment 283 00:37:21,470 --> 00:37:26,640 at the same time, the CPU releases all the buses the data bus control, bus address bus 284 00:37:26,640 --> 00:37:32,010 everything. Those are no more physically or logically connected to the CPU. Now this DMA 285 00:37:32,010 --> 00:37:37,530 controller becomes the bus master. So what it does is it reads the data from the memory, 286 00:37:37,530 --> 00:37:44,500 sends that to I/O device or reads the data from the I/O device sends that to memory. 287 00:37:44,500 --> 00:37:48,430 So all the operation which otherwise would have to be done by the CPU, now it is to be 288 00:37:48,430 --> 00:37:50,790 done by the DMA control. 289 00:37:50,790 --> 00:37:54,850 So accordingly the DMA controller will have to have a number of registers because it has 290 00:37:54,850 --> 00:38:01,810 to know that which device has to be activated. Simultaneously it also has to know that which 291 00:38:01,810 --> 00:38:08,060 memory location is to be accessed either for reading purpose or writing purpose. So number 292 00:38:08,060 --> 00:38:15,060 of units that will be present in the DMA device will be same as the number of units that you 293 00:38:16,670 --> 00:38:23,670 have in the CPU, more or less same it is not identical. So some of the units will be say 294 00:38:29,450 --> 00:38:36,450 memory address register, I have to have memory address register, I also have to have an information 295 00:38:44,930 --> 00:38:51,930 about what is the length of the data that has to be transferred that is count. So if 296 00:38:52,120 --> 00:38:56,960 I want to transfer say 100 bytes of data from the main memory to a device, in that case 297 00:38:56,960 --> 00:39:03,740 what I can do is I can simply increment the memory register address by one in a loop of 298 00:39:03,740 --> 00:39:10,740 100 and that can be controlled by this count value. And similarly I also have to have some 299 00:39:13,270 --> 00:39:20,270 control unit which will give the control signals to the memory as well as the I/O device. 300 00:39:21,910 --> 00:39:28,910 On the other hand I have to have an I/O address decoder because may be a number of devices 301 00:39:30,560 --> 00:39:35,290 are connected to the same controller, same DMA and the DMA controller has to activate 302 00:39:35,290 --> 00:39:42,290 one of the devices, so there has to be an I/O address decoder. In addition to this there 303 00:39:45,480 --> 00:39:52,480 has to be a bus control unit and in addition there will be a number of other things like 304 00:39:58,820 --> 00:40:03,210 in some cases whenever the data is to be transmitted by the different bytes are packed together 305 00:40:03,210 --> 00:40:07,910 to make a single packet and that is transmitted. All those different additional control signals 306 00:40:07,910 --> 00:40:14,810 can be accommodated in the DMA controller. So on one side the DMA controller will be 307 00:40:14,810 --> 00:40:21,810 interfaced with the memory so for that we need the address lines, we need the read write 308 00:40:24,720 --> 00:40:31,720 signals, we need the bus request, bus request signal which will go to the CPU following 309 00:40:39,020 --> 00:40:46,020 this bus request the CPU has to give a bus grant signal which will come to the DMA controller 310 00:40:48,770 --> 00:40:54,700 from the CPU and on getting this bus grant signal from the CPU, the DMA controller can 311 00:40:54,700 --> 00:41:01,700 start operation and obviously I have to have the data lines. So this is the part, this 312 00:41:06,240 --> 00:41:13,210 side is to interface the DMA controller with the memory and the CPU. 313 00:41:13,210 --> 00:41:18,430 On the other side the DMA controller has to be interfaced with the device so that means 314 00:41:18,430 --> 00:41:25,430 I will have a number of control lines for controlling the I/O device I also have to 315 00:41:28,330 --> 00:41:35,330 have a number of data lines which will carry the device data. So now we find that the responsibility 316 00:41:46,550 --> 00:41:50,380 of this DMA controller will be that on one side it will be interfaced with the device, 317 00:41:50,380 --> 00:41:54,640 so it can get the data from the device and on the other side it is interfaced with the 318 00:41:54,640 --> 00:42:00,230 memory, so it can send the data to the memory. Similarly it can get the data from the memory 319 00:42:00,230 --> 00:42:05,680 and send the data to the output device and while performing this operation, the read 320 00:42:05,680 --> 00:42:12,680 and write operations by the CPU is no more needed. Got it? And because of this additional 321 00:42:12,910 --> 00:42:18,500 registers in this DMA controller, the operation of the DMA controller can be much faster than 322 00:42:18,500 --> 00:42:24,670 that in case of the CPU because in case of CPU firstly the CPU has to read the data, 323 00:42:24,670 --> 00:42:29,490 get it into its internal register then from the internal register it has to send the data 324 00:42:29,490 --> 00:42:35,090 to the destination, so two cycles are always necessary if I want to transfer the data through 325 00:42:35,090 --> 00:42:42,090 CPU whereas similar operation can be done in a single cycle by making use of this DMA 326 00:42:42,370 --> 00:42:42,760 controller. 327 00:42:42,760 --> 00:42:49,090 Again when you come to the DMA controller, I can have two different options. As I said 328 00:42:49,090 --> 00:42:56,090 that I mean this is a kind of channel because this DMA controller itself is a processor 329 00:42:57,750 --> 00:43:04,580 which can work independently of the CPU. So again in this case of DMA controller or channel 330 00:43:04,580 --> 00:43:10,100 as we said that such kind of devices are also called channels, I can have two types of options, 331 00:43:10,100 --> 00:43:17,100 one is called a selector channel and other one is called a multiplexer channel. What 332 00:43:33,980 --> 00:43:39,580 is the selector channel and what is the multiplexer channel? Suppose I use the same DMA controller 333 00:43:39,580 --> 00:43:45,550 to which a number of devices are connected. 334 00:43:45,550 --> 00:43:51,230 Now a selector channel, what it will do is suppose all the devices want to get some service 335 00:43:51,230 --> 00:43:58,230 simultaneously. Then a selector channel will select one of the devices that device will 336 00:43:58,550 --> 00:44:05,550 complete its operation then only the operation of the other device will be initiated. In 337 00:44:07,000 --> 00:44:13,590 case of multiplexer channel, the operations of different devices are time multiplexed 338 00:44:13,590 --> 00:44:18,820 that means if there are say 5 devices connected, first device will operate for say 1 milli 339 00:44:18,820 --> 00:44:24,520 second then during second one milli second period the second device will operate, may 340 00:44:24,520 --> 00:44:31,520 be the operation of the first device is not yet complete. So multiplexer channel multiplexes 341 00:44:32,000 --> 00:44:36,840 the operations of multiple devices which are connected to the DMA controller, in case of 342 00:44:36,840 --> 00:44:42,510 selector channel the DMA channel the DMA controller selects one of the device, the device completes 343 00:44:42,510 --> 00:44:49,010 its operation then only the operation of the next device is initiated. Now which type of 344 00:44:49,010 --> 00:44:52,030 channel we should go for? Whether we should go for the selector channel or we should go 345 00:44:52,030 --> 00:44:57,210 for the multiplexer channel that depends upon device characteristics. 346 00:44:57,210 --> 00:45:03,690 Say if the devices are very fast in that case I can go for selector channel because as we 347 00:45:03,690 --> 00:45:08,140 have said that once a device is selected, the device has to complete its operation then 348 00:45:08,140 --> 00:45:13,770 only the next device can start operation. So if the first device takes a small amount 349 00:45:13,770 --> 00:45:18,750 of time then the second device can wait until and unless the operation of the first device 350 00:45:18,750 --> 00:45:25,750 is complete but if the devices are very slow in that case the waiting time may not be tolerable. 351 00:45:27,450 --> 00:45:33,570 So if the devices are slow, we should go for the multiplexer channel. If the devices are 352 00:45:33,570 --> 00:45:40,570 fast enough then we can go for the selector channel. So let us take some break. 353