﻿1 00:01:00,870 --> 00:01:07,790 Towards the beginning of our course, we have talked about designing of a particular CPU, 2 00:01:07,790 --> 00:01:14,790 a common CPU and there our concentration was on defining the controls circuit of the CPU. 3 00:01:17,460 --> 00:01:22,860 Then in the latter part what we have seen is how to design a hardware control unit, 4 00:01:22,860 --> 00:01:28,290 how to design a micro program control unit and then we have seen that for improving the 5 00:01:28,290 --> 00:01:35,130 performance of the CPU, how we can pipeline different operations so that more than one 6 00:01:35,130 --> 00:01:41,310 instruction can be in the pipeline simultaneously but we dint talk about the pipelined CPU as 7 00:01:41,310 --> 00:01:45,420 such. We have taken in general pipeline architectures. 8 00:01:45,420 --> 00:01:52,170 Now another aspect which is very important for improvement of the performance of any 9 00:01:52,170 --> 00:01:57,200 processor is not only the control unit, it is also the data path that is what are the 10 00:01:57,200 --> 00:02:02,380 paths that will be taken for transferring the data from one data unit to another data 11 00:02:02,380 --> 00:02:09,380 unit. So before we go to pipelined CPU, let us see for a typical advanced CPU, how the 12 00:02:09,979 --> 00:02:16,530 data path is to be decided. So for that we consider a particular architecture which is 13 00:02:16,530 --> 00:02:23,230 known as a MIPS processor and we will take few of the MIPS instructions from the MIPS 14 00:02:23,230 --> 00:02:30,230 instruction set to decide how we can design the data path. So few of the instructions 15 00:02:30,800 --> 00:02:37,800 that we will consider for deciding the data path is, we will consider a data instruction 16 00:02:38,730 --> 00:02:45,730 of type register or R type instruction. We will also consider an instruction of type 17 00:02:50,510 --> 00:02:55,010 memory or M type instruction. 18 00:02:55,010 --> 00:03:02,010 We will consider one branch instruction. So an R-type instruction is typically like this. 19 00:03:13,420 --> 00:03:18,349 If we want to perform addition of the contents of two registers, so we have two registers 20 00:03:18,349 --> 00:03:24,590 R1 and R2. We want to add the contents of R1 and R2 and to the result, we will go the 21 00:03:24,590 --> 00:03:30,400 destination which in discuss we assume it is the third register that is R3. So an ADD 22 00:03:30,400 --> 00:03:37,400 instruction or R type instruction typically will be of this form ADD R1, R2 and R3 where 23 00:03:47,349 --> 00:03:54,349 the content of R1 and R2 will be added and the result will be stored in register R3. 24 00:03:54,650 --> 00:04:01,650 We will consider 2 M type instructions, one is load and other one is store. So the instructions 25 00:04:04,739 --> 00:04:11,739 are like this LW which is load word and LW will work with arguments like this R1 then 26 00:04:22,920 --> 00:04:29,920 offset R2. So this means that the content of the memory location… Now the address 27 00:04:35,490 --> 00:04:42,490 of the memory location will be decided by content of register R2 and an offset value. 28 00:04:43,300 --> 00:04:50,300 So this is also sometimes called relative addressing where R2 will act as the base address. 29 00:04:51,169 --> 00:04:55,850 On the content of the base address, you add the offset value to get the physical address 30 00:04:55,850 --> 00:05:02,320 in the main memory. This load word will read through the content from that physical address 31 00:05:02,320 --> 00:05:09,169 of the memory and load that content into register R1. 32 00:05:09,169 --> 00:05:16,169 Similarly a store instruction, we put this as store word. The format will be similar, 33 00:05:18,139 --> 00:05:25,139 R1 offset R2 where you calculate the address of the memory location from the content of 34 00:05:35,110 --> 00:05:41,169 register R2 and the offset value that is specified within the instruction to that particular 35 00:05:41,169 --> 00:05:48,169 location in the memory, you store the content of register R1. So this is what store word 36 00:05:48,500 --> 00:05:55,500 instruction means. In the branch category we consider one instruction, let us say branch 37 00:05:56,979 --> 00:06:03,979 on equal or BEQ. The format will be BEQ R1, R2 and an offset. So when this BEQ R1, R2, 38 00:06:25,050 --> 00:06:30,220 offset this instruction is executed, what this instruction will do is it will compare 39 00:06:30,220 --> 00:06:37,220 the contents of register R1 and register R2. If the contents are same that is R1 equal 40 00:06:37,680 --> 00:06:44,639 to R2 then a branch will take place and the branch address will be given by this offset 41 00:06:44,639 --> 00:06:49,930 and when you specify this as offset that means this offset value will be added to the present 42 00:06:49,930 --> 00:06:55,889 program counter value and that tells you that from the location from where the next instruction 43 00:06:55,889 --> 00:07:02,889 will be taken for execution. So this offset is not the physical address of the instruction. 44 00:07:06,189 --> 00:07:13,189 It gives you a relative address, relative to the present program counter value. 45 00:07:13,979 --> 00:07:20,979 Now when you execute these instructions as you have seen before also that the instruction 46 00:07:22,389 --> 00:07:29,389 fetch operation is common for all the instructions. So to decide the data path, let us see that 47 00:07:29,669 --> 00:07:34,909 what are the data components and what is the path that is informed in an instruction fetch 48 00:07:34,909 --> 00:07:41,909 operation. Obviously the data components which will be involved is a program counter because 49 00:07:42,050 --> 00:07:46,080 the program counter gives you the address of the instruction that is to be fetched and 50 00:07:46,080 --> 00:07:52,050 the other component to the data unit which will be informed is memory. Now in this case 51 00:07:52,050 --> 00:07:57,810 let us say that we have a memory which is called an instruction memory that stores only 52 00:07:57,810 --> 00:08:03,460 the instructions. Later on we will think of the other options. so we will have two components 53 00:08:03,460 --> 00:08:10,460 which are involved in any instruction fetch that is the program counter, instruction memory 54 00:08:10,699 --> 00:08:17,699 and the other component that is involved is some sort of an ALU which tells you that once 55 00:08:19,240 --> 00:08:25,939 an instruction is fetched what is the address of the next instruction to be fetched. So 56 00:08:25,939 --> 00:08:32,939 here for instruction fetch, we will have a program counter. We will have a memory 57 00:08:52,990 --> 00:08:59,990 and in this case let us say that it is instruction memory. 58 00:09:06,800 --> 00:09:12,090 The program counter gives the address to the instruction memory that particular address 59 00:09:12,090 --> 00:09:16,180 in the instruction memory contains the instruction. So output of this instruction memory will 60 00:09:16,180 --> 00:09:23,180 be an instruction and this is the read address. As I said that the other component which will be involved 61 00:09:38,910 --> 00:09:45,910 in this instruction fetch operation is some sort of an ALU and the function of this ALU 62 00:09:47,880 --> 00:09:53,279 is only addition because the program counter has to be incremented by some amount after 63 00:09:53,279 --> 00:09:59,720 an instruction is read. So output of the program counter will also go to this one of the inputs 64 00:09:59,720 --> 00:10:06,720 to this ALU. The other input of this ALU, so now instead of calling it an ALU, let us 65 00:10:09,079 --> 00:10:14,920 call it just an ADD unit because only function that this ALU will perform is addition of 66 00:10:14,920 --> 00:10:21,709 some amount to the current program counter value. Let us assume that every instruction 67 00:10:21,709 --> 00:10:28,709 in this instruction set is of fixed length and the length is let us say it is 4 bytes. 68 00:10:30,350 --> 00:10:37,350 So we add 4 to this program counter content which gives you the address of the next instruction 69 00:10:37,790 --> 00:10:44,790 to be read from this instruction memory. 70 00:10:49,500 --> 00:10:56,120 So these are the components, the data units and this is the data path which is involved 71 00:10:56,120 --> 00:11:03,120 in fetching an instruction and this is common for all the instructions. Now after an instruction 72 00:11:05,029 --> 00:11:09,880 is fetched, put into program counter, you read the corresponding instruction. the instruction 73 00:11:09,880 --> 00:11:15,120 is available at the output of the instruction memory. Then the execution of the instruction 74 00:11:15,120 --> 00:11:20,949 starts from this point onwards, once the instruction is available from the output of the instruction 75 00:11:20,949 --> 00:11:27,949 memory. Now let us see that for execution of different instructions, what type of units 76 00:11:28,000 --> 00:11:35,000 that you need and what is the data path involved in each of them. So firstly we will consider 77 00:11:35,860 --> 00:11:42,790 the R-type instruction that is ADD R1, R2 and R3. So the instruction that will consider 78 00:11:42,790 --> 00:11:49,790 first is an instruction of the form ADD R1, R2 and R3 where the contents of the registers 79 00:12:00,220 --> 00:12:06,170 R1 and R2 will be read and for the result will be written into register R3. 80 00:12:06,170 --> 00:12:09,779 So you find that there are three registers involved, two registers will take part in 81 00:12:09,779 --> 00:12:16,779 read operation and one register that is R3 will take part in the write operation. Now 82 00:12:17,550 --> 00:12:24,149 there can be a number of registers in the CPU. Each of the registers will have an unique 83 00:12:24,149 --> 00:12:31,149 address. So if in this field, in the instruction if I specify 0 0 0 0 like this, in that case 84 00:12:31,880 --> 00:12:36,480 zeroth register in the registers I will put all the registers together, let us call it 85 00:12:36,480 --> 00:12:43,480 a register bank. So zeroth register in the register bank will be accessed. So to decide 86 00:12:43,750 --> 00:12:50,750 the data path for this and the units that are involved in execution of this instruction, 87 00:12:50,899 --> 00:12:57,899 we will put it like this. We have a register bank, in some book you will find that this 88 00:13:00,740 --> 00:13:07,740 is also mentioned as register file. So this is the register bank 89 00:13:17,889 --> 00:13:24,380 and three addresses are involved in this. One for register R1, one for register R2 and 90 00:13:24,380 --> 00:13:31,380 the other for register R3. All these addresses will be mentioned within the instruction. 91 00:13:31,630 --> 00:13:37,889 So I have to have address for register R1, I have to have address for register R2, I 92 00:13:37,889 --> 00:13:44,889 also have to have address for register R3. So this is for read operation, so read R1 93 00:13:50,910 --> 00:13:57,910 or we put read register one. This address will be for reading register two and the third 94 00:14:03,940 --> 00:14:10,940 address is meant for writing into a register, so this is for write register. The other input 95 00:14:17,850 --> 00:14:24,149 to this register bank will be the data that is to be written into one of the registers. 96 00:14:24,149 --> 00:14:31,149 So the third input will be meant for write data. This register bank will have two outputs, 97 00:14:40,370 --> 00:14:45,360 the outputs corresponding to output of register R1, content of register R1 and content of 98 00:14:45,360 --> 00:14:52,360 register R2. So I will have two outputs, one is the read data 1 and other one is read data 99 00:15:08,110 --> 00:15:15,110 2. 100 00:15:15,120 --> 00:15:19,790 Now since the operation to be performed is adding the content of register R1 and register 101 00:15:19,790 --> 00:15:25,380 R2 which are available on the output of this register bank, they have to be added together 102 00:15:25,380 --> 00:15:30,970 and the result has to go to register R3. That means this outputs are to be fed to the input 103 00:15:30,970 --> 00:15:37,970 of an ALU. So I have to have an ALU and it is an output of the ALU that has to come to 104 00:15:53,410 --> 00:16:00,410 this write data input of the register bank. Is it okay? So you provide three addresses 105 00:16:06,819 --> 00:16:11,920 from the instruction address for two registers which are to be read and address of the third 106 00:16:11,920 --> 00:16:18,529 register which has to be written and another input that is provided to the register bank 107 00:16:18,529 --> 00:16:23,470 is the data input which is to be written into the third register. 108 00:16:23,470 --> 00:16:30,470 All these register addresses will come from the instruction. So it is the instruction 109 00:16:41,529 --> 00:16:45,949 which is giving you the addresses of the registers which are to be read. It is also telling you 110 00:16:45,949 --> 00:16:51,319 the address of the register which is to be written. Then the data to be written is the 111 00:16:51,319 --> 00:16:57,819 output of the ALU which works on these two output data and the control signal that will 112 00:16:57,819 --> 00:17:04,819 be needed to this register is a write control signal for writing into the register R3. So 113 00:17:10,000 --> 00:17:16,540 whatever data is available on the write data input that will be written into the register 114 00:17:16,540 --> 00:17:23,540 on asserting this write register control signal into a register whose address comes on the 115 00:17:23,790 --> 00:17:30,790 write register input of this register bank. So this will be the typical components needed 116 00:17:34,450 --> 00:17:41,450 for an R-type instruction of which a typical example is ADD R1, R2, R3. what we can assume 117 00:17:48,410 --> 00:17:54,160 is that whenever the inputs, the addresses are available to these inputs the data is 118 00:17:54,160 --> 00:18:01,160 always available on this outputs. It can be simply a combinational circuit. 119 00:18:01,650 --> 00:18:08,059 The other set of control signals that you need is the ALU control signals or ALU function 120 00:18:08,059 --> 00:18:15,059 select signals because instead of an ADD operation, if we want to perform an AND operation over 121 00:18:16,159 --> 00:18:21,840 these two registers R1 and R2 then this ALU has to perform an AND operation other than 122 00:18:21,840 --> 00:18:27,120 an ADD operation and which operation this ALU will perform that depends upon what is 123 00:18:27,120 --> 00:18:34,120 the control signal that you apply to the ALU input. So this will be the typical organization 124 00:18:35,580 --> 00:18:42,580 of different components and their interconnections for an R-type instruction. We will come to 125 00:18:48,020 --> 00:18:51,990 that later. 126 00:18:51,990 --> 00:18:57,559 Then the second kind of instruction that you have said is M-type instruction where our 127 00:18:57,559 --> 00:19:04,559 instruction format is something like this, either we can have a load word or a store 128 00:19:10,770 --> 00:19:17,770 word on R1 then offset R2. In case of load word this memory address will be read and 129 00:19:41,850 --> 00:19:48,570 the data will be written into R1. In case of store word the data from R1 will be written 130 00:19:48,570 --> 00:19:55,570 into the memory whose address is given by this. Again in this case your register bank 131 00:19:56,870 --> 00:20:03,870 will be needed. Isn’t it? To identify these two registers, which registers you are using. 132 00:20:04,500 --> 00:20:11,500 So again I need the register bank. So these are the registers, I also need the ALU but 133 00:20:25,770 --> 00:20:32,770 in this case the ALU is needed not for performing any AND or ADD operation but the ALU is needed 134 00:20:32,860 --> 00:20:37,600 to calculate the memory address from where the data is to be read or from where the data 135 00:20:37,600 --> 00:20:44,600 is to be written. So again this register bank, it will have three inputs but out of that 136 00:20:49,340 --> 00:20:56,340 we will need two register identification numbers. All three are not needed for this particular 137 00:20:57,520 --> 00:21:01,070 instruction. 138 00:21:01,070 --> 00:21:08,070 For store operation I need write register and write data. For load operation I need 139 00:21:10,600 --> 00:21:15,809 write register and write data because in case of load, the data has to be written into the 140 00:21:15,809 --> 00:21:21,559 register. In case of store word, the data is not to be written into the register but 141 00:21:21,559 --> 00:21:28,559 the data will be written into the memory and it will be read from the register. So in this 142 00:21:28,620 --> 00:21:35,620 particular case I need say read register one, I may also need read register two, I may also 143 00:21:51,230 --> 00:21:58,230 need write register, I may also need the write data. I also need the ALU for the calculation 144 00:22:21,539 --> 00:22:28,539 of the address. One of the outputs from this registers will directly go to the ALU. Isn’t 145 00:22:29,320 --> 00:22:36,320 it? Because one of the contents of one of the registers is to be added with offset value. 146 00:22:37,970 --> 00:22:43,789 This register addresses, register identification numbers will come from the instruction. All 147 00:22:43,789 --> 00:22:50,789 of them will come from the instruction. The instruction also contains the offset value. 148 00:22:56,710 --> 00:23:03,710 So in this case the other input to the ALU will not be from the registers but the other 149 00:23:04,520 --> 00:23:11,520 input to the ALU will come from the instruction. So this is my ALU. Is it okay? Now what is 150 00:23:25,020 --> 00:23:32,020 usually done is in case of MIPS architecture, this offset is given as a 16 bit watt whereas 151 00:23:34,230 --> 00:23:41,230 the total addressing capacity of a MIPS architecture is a 32 bit watt. So when I have a 16 bit 152 00:23:42,760 --> 00:23:49,760 offset, this 16 bit data or the address has to be sign extended to 32 bit. So in between 153 00:23:51,559 --> 00:23:58,559 we can have one more unit which is for sign extension. Data path will be modified like 154 00:24:03,600 --> 00:24:10,600 this. In between we have a sign extension unit, so the offset is inputted to the sign 155 00:24:16,429 --> 00:24:23,320 extension unit. So this direct path is no more there and output of the sign extension 156 00:24:23,320 --> 00:24:30,320 unit goes to the ALU. ALU output is the physical address of the memory which is to be written 157 00:24:32,880 --> 00:24:35,270 or to be read. 158 00:24:35,270 --> 00:24:41,039 In case of load word, the memory will be read. In case of store word, the memory will be 159 00:24:41,039 --> 00:24:48,039 written into. So I have a memory block here and in this case let me call it as data memory. 160 00:24:56,429 --> 00:25:03,429 This is your data memory, address to the data memory comes from the ALU. So this is the 161 00:25:10,090 --> 00:25:17,090 address. Now the data memory gives you the output. Let me take it from here which is 162 00:25:25,700 --> 00:25:32,700 the read data. In case of load word, this data output from the data memory has to be 163 00:25:39,890 --> 00:25:45,149 given back to the write data input of the register bank because you are reading from 164 00:25:45,149 --> 00:25:52,149 the memory location, loading the data into register R1. So in case of load word instruction, 165 00:25:55,600 --> 00:26:02,600 the write data of the registers will come from the read data from the memory. Whereas 166 00:26:05,470 --> 00:26:11,870 in case of store word, it is the content of one of the registers which is to be written 167 00:26:11,870 --> 00:26:14,090 into the data memory. 168 00:26:14,090 --> 00:26:21,090 So other output of the registers will now be connected to the data input of the memory. 169 00:26:26,549 --> 00:26:33,549 The control signals that you need for this memory is, one is memory read which is used 170 00:26:36,149 --> 00:26:43,080 in case of load word and the other control signal that will be used is memory write which 171 00:26:43,080 --> 00:26:50,080 will be used for store word instruction. So you see that how you are deciding the data 172 00:26:51,490 --> 00:26:57,860 path, depending upon the type of operation that is to be performed we decide that what 173 00:26:57,860 --> 00:27:04,860 kind of data path will be needed. So this is for the second category of instruction 174 00:27:05,190 --> 00:27:11,049 that is accessing the memory either for load operation or for store operation. 175 00:27:11,049 --> 00:27:18,049 The data path that will be used for third kind of instruction that we are using is for 176 00:27:18,429 --> 00:27:25,429 branch on equal that is BEQ and the format is BEQ R1 R2 and an offset. So you compare 177 00:27:43,679 --> 00:27:50,130 the contents of registers R1 and R2. If they are same, if they are equal then you jump 178 00:27:50,130 --> 00:27:57,130 to a location which is away by this amount offset from the current program counter value. 179 00:27:59,490 --> 00:28:03,899 So obviously that register bank is also involved because I have to read the contents of registers 180 00:28:03,899 --> 00:28:10,899 R1 and R2. Then they are to be compared, so ALU is also involved. So here again I have 181 00:28:11,779 --> 00:28:18,779 this register bank which will have read register 1 and a read register 2 control units. So 182 00:28:33,039 --> 00:28:40,039 this is for read register 1 and not control units sorry the address inputs, read register 183 00:28:43,880 --> 00:28:50,880 two address. There are other inputs also but in this particular case they are not needed. 184 00:28:52,720 --> 00:28:59,720 This output will go to an ALU which will compare the two register outputs. So this will go 185 00:29:12,059 --> 00:29:16,809 to ALU. 186 00:29:16,809 --> 00:29:21,940 The ALU will perform a separate operation because that is the way in which we have compare 187 00:29:21,940 --> 00:29:27,179 these two data. It will perform a separate operation but the output will not go anywhere 188 00:29:27,179 --> 00:29:34,130 but the zero out condition will be used by the control unit to decide what will be the 189 00:29:34,130 --> 00:29:40,909 address of the next instruction to be executed. So this ALU in addition to giving you the 190 00:29:40,909 --> 00:29:47,909 difference output, it also gives you an output whether the result is zero or not. If the 191 00:29:52,250 --> 00:29:59,250 result is zero in that case what we have to do is we have to add the current program counter 192 00:30:00,149 --> 00:30:05,990 value with this offset but again this offset is given in the form of 16 bit which is to 193 00:30:05,990 --> 00:30:12,990 be sign extended to 32 bit and all of them will come from the instruction. So all this 194 00:30:17,700 --> 00:30:24,700 comes from the instruction. The offset is sign extended to say 32 bits so I will have 195 00:30:29,840 --> 00:30:36,840 a sign extension unit. The other thing that is done for calculating this branch address 196 00:30:45,880 --> 00:30:51,840 is after sign extension, we have to ensure because we have assumed that every instruction 197 00:30:51,840 --> 00:30:57,260 is of length 4 bytes that means whatever address we generate that will always be generated 198 00:30:57,260 --> 00:31:04,260 at 4 byte offset, at 4 byte bounded. So another block that is put is that after you sign extend, 199 00:31:07,490 --> 00:31:14,140 generate the offset address. You give left shift by two bits to the offset address. Whenever 200 00:31:14,140 --> 00:31:19,570 giving left shift by 2 bits that is equivalent to multiplying by 4. That ensures that any 201 00:31:19,570 --> 00:31:24,769 new instruction that is to be fetched will start from four byte boundary. That means 202 00:31:24,769 --> 00:31:31,769 it is the beginning address of a new instruction. So this sign extended bit will now go to a 203 00:31:33,730 --> 00:31:40,730 two bit left shifter, so I have left shift by two bits. So this gives me the final offset. 204 00:31:50,659 --> 00:31:56,080 This final offset is to be added with the current program counter value and the current 205 00:31:56,080 --> 00:32:01,720 program counter value, you will get from the instruction fetch unit. This output is the 206 00:32:01,720 --> 00:32:05,980 current program counter value. 207 00:32:05,980 --> 00:32:12,980 So this left shifted offset is to be added with the current program counter value. So 208 00:32:13,950 --> 00:32:20,950 I need an adder unit here. Here what I get is the program counter and this output, this 209 00:32:29,279 --> 00:32:36,279 is a simple adder unit. This output gives me the branch address. So we will find that 210 00:32:50,909 --> 00:32:57,909 we have been able to identify that what are the data units and what will be the data path 211 00:32:58,049 --> 00:33:03,240 among different data units for the fetch operation and for execution of three different kinds 212 00:33:03,240 --> 00:33:09,260 of instructions but obviously in a CPU, I cannot have different units for execution 213 00:33:09,260 --> 00:33:14,139 of different instructions. All of them to are to be combined together. 214 00:33:14,139 --> 00:33:20,279 So next what we have to think is how to combine all these pieces together so that we can have 215 00:33:20,279 --> 00:33:27,279 a complete CPU. So for that we have to see that how, in case to a particular source the 216 00:33:34,320 --> 00:33:39,059 data comes from multiple sources to a particular destination, how to mix those different source 217 00:33:39,059 --> 00:33:46,059 outputs. So one way and the simplest way for doing that is to use a multiplexer. So first 218 00:33:47,789 --> 00:33:53,460 let us complete the data parts and then we will try to combine this with the instruction 219 00:33:53,460 --> 00:34:00,029 fetch part. In all these cases we have found that your register bank is involved, so I 220 00:34:00,029 --> 00:34:05,010 put this register bank. 221 00:34:05,010 --> 00:34:12,010 So these are the register bank. Register bank gives you two outputs and it has got four 222 00:34:25,980 --> 00:34:32,980 inputs, four inputs are meant for read register one, read register two, write register and 223 00:34:34,060 --> 00:34:41,060 write data. So I have four inputs to this register bank. Out of these four inputs, three 224 00:34:42,490 --> 00:34:49,490 of the inputs comes from the instruction, so this comes from the instruction. Now these 225 00:34:53,550 --> 00:35:00,550 outputs will go to the ALU. When it comes to an ALU, you find that in case of ALU the 226 00:35:12,640 --> 00:35:19,640 second input to the ALU can be from various sources. So you find that the first instruction 227 00:35:23,070 --> 00:35:26,790 that you have considered is for ADD instruction. 228 00:35:26,790 --> 00:35:30,790 In case of ADD instruction, the second input to the ALU comes directly from the register 229 00:35:30,790 --> 00:35:37,790 bank. First input also comes directly from the register bank. In case of load or store 230 00:35:38,560 --> 00:35:42,390 instruction, first input to the ALU comes from the register bank whereas the second 231 00:35:42,390 --> 00:35:49,390 input comes from the instruction offset. In case of branch on equal instructions, second 232 00:35:50,200 --> 00:35:56,680 input also comes from the register bank that is there are two sources from which the second 233 00:35:56,680 --> 00:36:02,930 input to the ALU will come. So I have to multiplex those two sources. 234 00:36:02,930 --> 00:36:09,930 So what I need here is a multiplexer. One input to the multiplexer is the second output 235 00:36:13,250 --> 00:36:18,640 of the register bank. first output of the register bank can directly go to the ALU. 236 00:36:18,640 --> 00:36:25,640 The other input of the multiplexer will be the offset from the instruction after sign 237 00:36:27,360 --> 00:36:34,360 extension. So this has to be sign extended and this becomes the second input to the multiplexer. 238 00:36:48,240 --> 00:36:55,240 Multiplexer output feeds the second input of the ALU, so this is my ALU. Output of the 239 00:36:59,670 --> 00:37:06,670 ALU gives the address to the memory, data memory. So this is data memory and output 240 00:37:22,070 --> 00:37:28,750 of the ALU gives you the address. Now coming to the write data, you find that for register 241 00:37:28,750 --> 00:37:35,660 type operations the write data comes from the ALU output. Whereas for load type instructions, 242 00:37:35,660 --> 00:37:42,660 the write data comes from the data memory. That means here also I have to have a multiplexer, 243 00:37:43,280 --> 00:37:50,120 I will put a multiplexer here. One of the inputs to the multiplexer is the data output 244 00:37:50,120 --> 00:37:52,140 of the data memory. 245 00:37:52,140 --> 00:37:55,930 One of the inputs to the multiplexer is data output of the data memory. The other input 246 00:37:55,930 --> 00:38:02,930 to the multiplexer is the output of the ALU and multiplexer output can now be connected 247 00:38:09,080 --> 00:38:16,080 to the write data input of the register bank. So this path is also complete. Whenever I 248 00:38:29,520 --> 00:38:36,520 wanted to write the data into the memory which has to come from one of the register bank 249 00:38:36,740 --> 00:38:43,440 outputs because that is needed for store word instruction. So the second output of this 250 00:38:43,440 --> 00:38:50,440 register bank can be connected to the data input of the memory unit. Is it okay? So you 251 00:39:00,020 --> 00:39:07,020 find that we have combined the data paths within this data unit for all types of instructions. 252 00:39:12,570 --> 00:39:19,570 The next operation that is to be performed is how to take care of the branch instructions? 253 00:39:19,910 --> 00:39:25,350 In case of branch instruction what you have said is that is this offset value, sign extender 254 00:39:25,350 --> 00:39:30,510 offset value is left shifted by two bits and this left shifted output is added with the 255 00:39:30,510 --> 00:39:34,500 current program counter. 256 00:39:34,500 --> 00:39:41,500 The current program counter value we have generated with the help of an adder like this, 257 00:39:44,520 --> 00:39:51,520 so here we had a program counter. I have the instruction memory 258 00:40:00,620 --> 00:40:07,620 which gets address from the program counter. The same program counter output goes to this 259 00:40:14,510 --> 00:40:21,510 adder to add with a number four and this gives the current program counter value. This sign 260 00:40:25,100 --> 00:40:32,100 extender offset is to be left shifted by two bits, so I have to left shift by two bits 261 00:40:35,440 --> 00:40:40,680 and after left shifting this by two bits, we have to add this with the current program 262 00:40:40,680 --> 00:40:47,680 counter value. So I need another adder. Output of this, it’s the second input of this adder. 263 00:40:54,300 --> 00:41:00,040 How do I decide the next program counter value? The next program counter value can be either 264 00:41:00,040 --> 00:41:06,950 this or output of this adder. If it is a branch instruction that is being executed then the 265 00:41:06,950 --> 00:41:12,260 next program counter value will be output of this adder, in case the branch condition 266 00:41:12,260 --> 00:41:19,260 is satisfied. So I put one more multiplexer here, this multiplexer will multiplex between 267 00:41:25,810 --> 00:41:32,810 the branch address or the normal program counter flow and output of this multiplexer can be 268 00:41:34,990 --> 00:41:41,990 loaded to the program counter and this completes my entire data path. 269 00:41:57,620 --> 00:42:02,050 Once this data path is completed then we have to design what will be the control circuit 270 00:42:02,050 --> 00:42:09,050 and as we said, as we have discussed earlier the control circuit always takes input from 271 00:42:09,170 --> 00:42:15,270 the instruction code. The instruction is decoded and depending upon the decoded instruction, 272 00:42:15,270 --> 00:42:22,270 the control circuit generates the control signals. So here we have to have a control 273 00:42:22,750 --> 00:42:29,750 unit. The control unit will take a part of the instruction and it will generate all the 274 00:42:40,350 --> 00:42:45,770 required control signals. What are the control signals required? Signals for controlling 275 00:42:45,770 --> 00:42:52,770 the ALU, for selecting what function the ALU has to perform, selecting memory read or memory 276 00:42:53,590 --> 00:43:00,590 write operations, selection of these multiplexers which input of the multiplexer has to be passed 277 00:43:01,250 --> 00:43:08,250 to the output. So all these control signals have to be generated by this control unit. 278 00:43:10,810 --> 00:43:17,810 So this will be the complete structure or complete organization of an advanced CPU. 279 00:43:19,380 --> 00:43:25,830 Now find that if you analyse this circuit, there is no reason why every instruction cannot 280 00:43:25,830 --> 00:43:32,830 be executed in single clock period. You find that whenever an instruction is available 281 00:43:33,920 --> 00:43:40,920 here or may be whenever the program counter value is that, the program counter will give 282 00:43:41,360 --> 00:43:46,750 the address to the instruction memory, instruction memory output will be the instruction code. 283 00:43:46,750 --> 00:43:53,130 All these paths will be set, registers will be read or the write data to the register 284 00:43:53,130 --> 00:43:58,620 will be set. The ALU will operate, the data can be read from the data memory or it can 285 00:43:58,620 --> 00:44:04,270 be written into the data memory depending upon the control signal that you get. So it 286 00:44:04,270 --> 00:44:10,060 is possible that all these operations can be drawn in a single clock period because 287 00:44:10,060 --> 00:44:14,070 all these components which are involved in this path they are all combinational logic 288 00:44:14,070 --> 00:44:17,580 circuits. There is no sequential logic circuit. 289 00:44:17,580 --> 00:44:24,580 The sequencing is done by the control unit. So if I want the different phases of this 290 00:44:26,130 --> 00:44:31,290 instruction execution has to be done in different clock periods then this control circuit will 291 00:44:31,290 --> 00:44:37,170 generate those control signals in sequence but it is possible that in a single clock 292 00:44:37,170 --> 00:44:44,170 period all these operations can be done. But what is the disadvantage? If I want to perform 293 00:44:44,580 --> 00:44:51,580 all these instruction execution of every instruction in a single clock period, there is a problem. 294 00:44:51,960 --> 00:44:58,960 The problem is the clock period now will be decided by the largest delay path and that 295 00:45:01,480 --> 00:45:06,630 is required for load and store instructions because it is the load and store instructions 296 00:45:06,630 --> 00:45:13,630 which makes use of instruction memory, register, ALU, data memory, everything. Whereas for 297 00:45:15,010 --> 00:45:19,620 register type instructions, the components which are used is only instruction memory, 298 00:45:19,620 --> 00:45:23,340 in any case will be there; only the register bank and the ALU. 299 00:45:23,340 --> 00:45:30,340 So I have a shorter delay path. So if I want to perform this operations in a single clock 300 00:45:32,030 --> 00:45:37,980 period, my clock period will be decided by the largest delay path which will also be 301 00:45:37,980 --> 00:45:43,930 applied on the instructions which actually require less amount of delay. So effectively 302 00:45:43,930 --> 00:45:50,930 you are making your design inefficient. Instead of doing that, what you can do is you simply 303 00:45:51,860 --> 00:45:57,580 increase the frequency, the clock frequency and decide that how many clock frequencies, 304 00:45:57,580 --> 00:46:04,000 how many clock periods will be allocated for execution of fetch instruction. In that case 305 00:46:04,000 --> 00:46:09,430 in general your design will be more efficient. We will come to more on this in the next class. 306