1
00:00:25,150 --> 00:00:32,150
We continue our discussion on CMOS circuits
just to remind you CMOS is tends for complimentary
2
00:00:36,500 --> 00:00:43,500
MOSFET circuits. In complimentary MOSFET circuits
in CMOS, we have Pmos and NMOS simultaneously,
3
00:00:48,120 --> 00:00:55,120
present on the chip these are very widely
used circuit and the most advanced circuits
4
00:00:57,400 --> 00:01:04,400
are actually, CMOS circuits and there are
two basic reasons for their popularity. One
5
00:01:08,210 --> 00:01:15,210
is that the power consumption is extremely
low in CMOS circuits, this we will show that
6
00:01:17,110 --> 00:01:24,110
why the power dissipation. The power consumption
is very small it is in fact, the lowest of
7
00:01:25,820 --> 00:01:32,820
all the known logics another reason is that
switching is very fast then on the previous
8
00:01:36,020 --> 00:01:43,020
turn we said that is an example of CMOS circuit.
We take a inverter. A inverter circuit which
9
00:01:46,250 --> 00:01:53,250
is also called a not circuit and a inverter
circuit is when input, it has only one input
10
00:01:54,010 --> 00:02:01,010
and one output. So, when the input is high
the output is low and when input is low, the
11
00:02:04,400 --> 00:02:11,400
output is high; that means, the input voltage
is inverted that is why it is called inverter.
12
00:02:12,680 --> 00:02:19,680
Now, this was also said that why we are taking
the inverter because inverter is basic for
13
00:02:23,739 --> 00:02:30,739
the digital electronics. The universal gates
nor gate and nand gate these can be realized
14
00:02:34,290 --> 00:02:41,290
by the extension of inverter circuit. So,
what is the CMOS inverter the circuit is this,
15
00:03:30,559 --> 00:03:37,559
this is Pmos, PMOSFETs and this is NMOS, NMOSFET.
And this is the d c supplied Vdd the input
16
00:03:49,519 --> 00:03:56,519
is obtained by connecting gates together for
both the mos, MOSFETs and the output is taken
17
00:04:00,949 --> 00:04:07,949
by connecting both the drains, drain of Pmos
and drain of a NMOS, they are connected together
18
00:04:08,669 --> 00:04:15,669
and from there the V out is taken. Now, we
also discuss that actually, Pmos requires
19
00:04:22,690 --> 00:04:29,690
a negative supply voltage that can be provided
by giving a positive source voltage. So, that
20
00:04:33,120 --> 00:04:38,960
is with a way these N MOSFET and P MOSFETs
are connected.
21
00:04:38,960 --> 00:04:45,960
So, this source is connected to this supply
plus terminal and this way we can get the
22
00:04:49,440 --> 00:04:56,440
we can bias both the MOSFETs by a single supply,
then we obtained to equations one for the
23
00:05:00,789 --> 00:05:07,789
input, input voltage is what is the voltage
here and that is we can write actually, that
24
00:05:09,169 --> 00:05:16,169
two equations which we got earlier this was
Vi this is equal to Vgsn is tend for NMOS
25
00:05:22,180 --> 00:05:29,180
this is equal to Vdd minus Vsg for P this
is equation one. Input is equal to this voltage
26
00:05:38,979 --> 00:05:45,979
which is Vgsn and that is also equal to Vdd
minus this voltage, that is Vsgp and the similarly,
27
00:05:54,180 --> 00:06:01,180
we can write for V out this is Vdsn this is
d, this is n, this is s.
28
00:06:04,919 --> 00:06:11,919
So, dn for NMOS and which is equal to Vdd
minus Vsd for P and this we call equation
29
00:06:20,599 --> 00:06:27,599
2 this 2 equations, we obtained the other
day which are simple these are simple the
30
00:06:31,009 --> 00:06:34,000
expressions which you have already see that
V out will be this voltage.
31
00:06:34,000 --> 00:06:41,000
Which is this and this is equal to this minus
this. So, this two equations we will be using
32
00:06:42,479 --> 00:06:49,479
later also now, the two cases we can discuss
and that two cases are case one, case one
33
00:06:55,389 --> 00:07:02,389
when input is low that is Vi is low. So, this
is 0 volt. Now, you can see you will have
34
00:07:09,430 --> 00:07:16,430
to keep in mind this circuit, when this voltage
is low; that means, this NMOS will be off
35
00:07:20,240 --> 00:07:27,240
because in this case Vgsn is equal to Vi which
is 0 and so obviously, it is less than the
36
00:07:36,099 --> 00:07:43,099
threshold voltage required for the NMOS and
hence therefore, NMOS is in off state is off
37
00:07:54,060 --> 00:08:01,060
and when the transistor is off; obviously,
the drain current I d in the NMOS.
38
00:08:01,960 --> 00:08:08,960
So, we write I d n this is equal to 0 and
then for Pmos, for Pmos this is NMOS is off,
39
00:08:17,409 --> 00:08:24,409
this mos is off. Now, let us find out when
input is low what of out Pmos. So, for Pmos
40
00:08:32,729 --> 00:08:39,729
from equation one
we get this is equation 1 from there we write
Vsgp which will be equal to Vdd minus Vgsn
41
00:08:54,560 --> 00:09:01,560
this what we write. So, Vsgp is equal to Vdd,
Vdd minus Vgsn and Vgsn is Vi. So, this is
42
00:09:22,660 --> 00:09:29,660
equal to Vdd minus Vi and since Vi is 0. So,
this is simply Vsgp this is at the potential
43
00:09:38,730 --> 00:09:45,730
Vdd and this is greater than the threshold
voltage because of the way, it is connected
44
00:09:48,900 --> 00:09:52,380
the way we have connected the drain is here
the source is here.
45
00:09:52,380 --> 00:09:59,380
So, when Vsgp is equal to Vdd it is greater
than V t for P and therefore, Pmos this was
46
00:10:05,330 --> 00:10:12,330
one state NMOS was off and now therefore,
Pmos is conducting; that means, it is on
MOSFETs they are in series. So, that will
47
00:10:32,100 --> 00:10:39,100
imply that drain current in the Pmos should
be equal to the drain current in the NMOS
48
00:10:47,100 --> 00:10:54,100
because both are in the series and that implies,
that implies that I d p is equal to 0. Now,
49
00:11:04,760 --> 00:11:11,760
it is conducting, but the, but the drain is
0 and if you look at the drain characteristics
50
00:11:15,480 --> 00:11:22,480
this situation is just in the beginning of
the ohmic linear region. So, it puts Pmos
51
00:11:28,970 --> 00:11:35,970
in the linear ohmic region, where Idp ohmic
is equal to 0.
52
00:11:53,530 --> 00:12:00,530
And once we write the expression which, when
we talked about the enhancement MOSFET then
53
00:12:03,370 --> 00:12:10,270
in ohmic region the drain current is given
by certain expression. So, that we use here.
54
00:12:10,270 --> 00:12:17,270
So, Idp ohmic is equal to k the constant,
the conductivity constant and this is Vsgp
55
00:12:28,200 --> 00:12:35,200
plus Vtp here proper sign of Vt has been used
and Vsd for P minus Vds for P square by 2
56
00:12:49,500 --> 00:12:56,500
this is the equation and because Vspvsg
for P is equal to Vdd here this was 0. So,
this one Vsgp is equal to Vdd this is what
57
00:13:26,180 --> 00:13:33,180
we have written.
So, here we can replace this by Vdd. So, Idp
58
00:13:33,770 --> 00:13:40,770
ohmic becomes equal to k Vdd plus Vt for Pvsg
for P minus Vdsp square by 2 this is, this
59
00:13:59,190 --> 00:14:06,190
is equal to 0 here. So, this we equate to
0. Then the solutions of this equation with
60
00:14:07,720 --> 00:14:14,720
this 0 k is not 0 and other parameters are
not 0 this will imply that it has the solution,
61
00:14:17,180 --> 00:14:24,180
it has the solution Vspsdp is 0. Now, substituting
this in equation two here Vsdp is 0 that will
62
00:14:44,660 --> 00:14:51,660
tell us, what will be the output in this equation.
So, substituting, substituting Vsdp equal
63
00:15:02,930 --> 00:15:09,930
to 0 in equation 2 we have V out equal to
Vdd that is high. This is what we expect from
64
00:15:25,580 --> 00:15:32,580
the inverter in the inverter, when the input
is high is input is low, the case under consideration
65
00:15:35,190 --> 00:15:42,190
then it results into high output and this
is what we are getting. So, this is case one
66
00:15:43,290 --> 00:15:50,290
that completes and then we go for case two
when input Vi is high, meaning Vi is Vdd we
67
00:16:12,200 --> 00:16:19,200
can see here also once, we say in the first
case when input is low. So, this was off and
68
00:16:23,480 --> 00:16:30,480
this was conducting. So, what is the voltage,
which you expect at output because this is
69
00:16:32,380 --> 00:16:34,550
conducting and this is off.
70
00:16:34,550 --> 00:16:41,550
So obviously, V 0 has to be equal to Vdd and
this is what we are getting similarly, in
71
00:16:42,780 --> 00:16:49,780
this case when this is high input is high
this will be conducting and once this is conducting
72
00:16:50,620 --> 00:16:57,620
very low impedance. So, then this output once
it is conducting, this will be very close
73
00:17:00,220 --> 00:17:07,220
to 0 and this is what we are going to have.
So, under this condition and Vi is Vdd then
74
00:17:08,319 --> 00:17:15,319
and Vdd is greater than Vt. So, in this case
NMOS will be on and it operates, operates
75
00:17:34,090 --> 00:17:41,090
in the linear ohmic region, but Pmos let us
see this is the state of the N mos, NMOS is
76
00:17:55,050 --> 00:18:02,050
conducting then what about the P mos, P mos
we will see is cut off Pmos is off for Vi
77
00:18:13,280 --> 00:18:20,280
equal to Vdd and this we can see from equation
one, which was Vsgp this is equal to Vdd minus
78
00:18:38,320 --> 00:18:45,320
Vgsn and Gsn is Vgd is Vi and Vi is Vdd.
79
00:18:49,790 --> 00:18:56,790
So, Vsgp this is Vdd minus Vdd which is 0
therefore, therefore, this is off Pmos is
80
00:19:06,880 --> 00:19:13,880
off, but because of the fact that both are
connected in series Idn ohmic should be equal
81
00:19:24,290 --> 00:19:31,290
to Idp off and this is equal to 0 and once
we write the equation for the drain current
82
00:19:41,760 --> 00:19:48,760
for NMOS, as we did in the previous case.
Here Idn this is equal to k for N that was
83
00:19:52,470 --> 00:19:59,470
for the P previous time.
When we did and this is Vgsn plus Vtn, Vsdn
84
00:20:10,820 --> 00:20:17,820
minus Vsdn square by two and since, Vgsn that
is equal to input, which is Vdd. So, we replace
85
00:20:33,570 --> 00:20:40,570
this by Vdd and we get Idn equal to k and
Vdd plus Vtn,Vsdn minus Vsdn square by 2 this
86
00:21:05,290 --> 00:21:12,290
is equal to 0. And the solution of this equation
is
solution is that Vsdn is equal to 0, this
87
00:21:29,700 --> 00:21:34,840
has to be 0 only then because other quantities
are not 0.
88
00:21:34,840 --> 00:21:41,840
So, we ascend is 0 and this is the same as
v d s n and what was output you will remember
89
00:21:50,840 --> 00:21:57,840
that output v 0 was Vdsn and this is 0. So,
output is low this is the working of CMOS.
90
00:22:11,130 --> 00:22:18,130
When the input, this input is low output is
high and when input is high output is low,
91
00:22:21,870 --> 00:22:28,870
this is what we get here and that is how a
CMOS the complimentary mos inverter works.
92
00:22:32,430 --> 00:22:39,430
We said that dissipation in the CMOS is least.
Let us discuss that point power dissipation,
93
00:22:46,570 --> 00:22:53,570
power dissipation, power dissipation and power
consumption are one and the same thing in
94
00:22:57,670 --> 00:23:04,670
electronics. Power dissipation in CMOS and
why power consume is equal to power dissipated
95
00:23:13,000 --> 00:23:19,840
because in equilibrium whatever, power that
transistor is dissipating.
96
00:23:19,840 --> 00:23:26,840
That is the heat which is being generated
by power consumed if for example, heat dissipation
97
00:23:27,990 --> 00:23:33,920
is less then temperature will go on increasing
and finally, there will be a thermal runway
98
00:23:33,920 --> 00:23:40,280
and the device will burn. So, always power
consumption is same as power dissipation.
99
00:23:40,280 --> 00:23:47,280
So, now, we consider that why power dissipation
in CMOS is least. There are two ways the power
100
00:23:53,880 --> 00:24:00,880
there are two types of dissipation one is
static power dissipation
and the other is dynamic power dissipation,
101
00:24:26,880 --> 00:24:33,880
dynamic power dissipation we take one by one.
So, first we take is static
power dissipation. Static power dissipation
102
00:24:47,990 --> 00:24:54,990
occurs, when these MOSFETs they have change
states they have changed the states for example,
103
00:25:04,700 --> 00:25:10,240
from high output to low output or the visa
versa.
104
00:25:10,240 --> 00:25:17,240
So, the states have already changed. So, what
is the power dissipation at in it that in
105
00:25:19,420 --> 00:25:26,420
that changed state that is called is static
power dissipation. Now, we have seen that
106
00:25:29,700 --> 00:25:36,700
in when the state changes for example, from
low when V out is low in this case Pmos was
107
00:25:42,760 --> 00:25:49,760
off
and the drain current Id in the CMOS was 0.
In fact, for the total drain current 0 was
108
00:26:04,760 --> 00:26:11,760
0 in the CMOS and similarly, when it changes
state the other way then, then the drain current
109
00:26:18,270 --> 00:26:25,270
was still 0 in either case this is off this
is on, but drain current is 0 or when this
110
00:26:28,640 --> 00:26:35,640
is off this is on is still the drain current
is 0. So, the is static power dissipation
111
00:26:35,679 --> 00:26:42,679
P d power dissipation, we write normally as
P d is static and this is the drain current
112
00:26:48,540 --> 00:26:55,540
in the high output case.
This was 0 as we know and Id low output. In
113
00:27:03,970 --> 00:27:10,970
this case as well this was 0 and this is to
be multiplied by Vdd by 2. So, currents being
114
00:27:17,880 --> 00:27:24,880
0 so, P d is static is 0 because the drain
current, when the states have already changed
115
00:27:31,970 --> 00:27:38,970
the drain currents as 0, but there are in
practice, in practice leakage current of the
116
00:27:47,150 --> 00:27:54,150
order of ten to power minus eighteen amperes
very small current they do exist, this is
117
00:27:58,270 --> 00:28:05,270
about static power dissipation.
Now, the dynamic, the dynamic power dissipation.
118
00:28:23,130 --> 00:28:30,130
Dynamic power dissipation
we said above that when the MOSFETs have changed
the states then the drain current is 0 and
119
00:28:42,240 --> 00:28:49,240
that give the static dissipation to be 0,
but dynamic power dissipation occurs when,
120
00:28:55,500 --> 00:29:02,500
both these MOSFETs they are changing its states.
During that transient period when the states
121
00:29:05,299 --> 00:29:12,299
are being changed from on to off or from off
to on then for that short period, the current
122
00:29:16,179 --> 00:29:23,179
drain current flows in the CMOS and that accounts
for the dynamic power dissipation I repeat
123
00:29:25,220 --> 00:29:31,690
that in the dynamic power dissipation.
When MOSFETs are changing its states from
124
00:29:31,690 --> 00:29:38,690
conducting to non conducting and non conducting
to conducting then during that the small transient
125
00:29:38,820 --> 00:29:45,820
time, the there is a drain current and that
gives the dynamic power dissipation and it
126
00:29:49,240 --> 00:29:56,240
can be shown that P d dynamic is equal to
c l mu into Vdd square where c l is the load
127
00:30:10,110 --> 00:30:17,110
capacitance at the output. What is the capacitance?
All circuits have inherent capacitance associated
128
00:30:21,730 --> 00:30:26,440
with them.
So, the c l is the load capacitance and mu
129
00:30:26,440 --> 00:30:33,440
is the switching frequency, switching frequency
and so, this is the dynamic loss and this
130
00:30:43,670 --> 00:30:50,670
is actually of the order of few tens of P
d dynamic, this is of the order of few tens
131
00:30:59,100 --> 00:31:06,100
of micro watts very small. So, the static
dissipation is close to 0 and dynamic dissipation
132
00:31:14,150 --> 00:31:21,150
is of the order of few tens of micro watts
per circuit per inverter for example, and
133
00:31:25,390 --> 00:31:32,390
that if we combine the two. We if the total
power dissipation is extremely low and this
134
00:31:36,059 --> 00:31:43,059
is the logic this is I am repeating this statement
that CMOS logic demonstrates least power loses.
135
00:31:50,950 --> 00:31:57,950
Now, this is about this module on MOSFETs
and fets. Let us take few numerical examples.
136
00:32:04,330 --> 00:32:11,330
And then I will summarize, what we have done
in this unit
as a first example let us take problem 1 for
137
00:32:27,220 --> 00:32:34,220
an n junction field of a transistor, the device
parameters are the source then source circuited
138
00:32:44,970 --> 00:32:51,970
current is the highest current in the n junction
field, where transistor Id ss this is ten
139
00:33:01,240 --> 00:33:08,240
milliampere for the device and V p the punch
through voltage is minus four volts you remember
140
00:33:15,200 --> 00:33:20,650
the structure of junction field there is a
drain there is a source and the channel is
141
00:33:20,650 --> 00:33:27,650
implanted and when the gate is shotted to
the source, then the drain current is the
142
00:33:34,330 --> 00:33:41,330
maximum. And when we operate this with a smaller
voltages more negative voltages.
143
00:33:43,840 --> 00:33:50,840
Then drain current falls. So, in this n junction
field of a transistor the Idss is ten milli
144
00:33:54,380 --> 00:34:01,380
ampere and punch through voltage is a four
volts, then we have to calculate. Calculate
145
00:34:05,400 --> 00:34:12,400
the drain current I d for different voltages
between gate and source Vgs equal to 0 this
146
00:34:17,720 --> 00:34:24,720
is a part b, part Vgs minus 2 volt and then
Cvgs is minus 4 volts under these three conditions,
147
00:34:33,079 --> 00:34:40,079
we have to find out the drain current when
these are the parameters available. Now, we
148
00:34:41,229 --> 00:34:48,229
talk about the solution; obviously, the that
the device is working in the saturation region,
149
00:34:59,119 --> 00:35:06,119
where for JFET the drain current is given
Idss 1 minus Vgsvp square.
150
00:35:18,130 --> 00:35:25,130
This equation, we are suppose to use we have
to find out I d for various gate source voltages
151
00:35:28,489 --> 00:35:35,489
where Idss is given as ten milliampere and
let us first see part a when Vgs is 0. So,
152
00:35:43,430 --> 00:35:50,430
this term is 0 and this is I d in this case
the drain current is equal to Idss which is
153
00:35:54,150 --> 00:36:01,150
given as ten milliampere and this is of course,
understood it is well understood because the
154
00:36:02,509 --> 00:36:09,509
gate source voltage is 0 here, this is drain
source and this is drain and this is the channel
155
00:36:17,440 --> 00:36:24,440
then the gate is shotted Vgs is made 0 that
is the maximum current which flows in the
156
00:36:28,710 --> 00:36:35,710
device.
So, this is this then when Vgs, b part when
157
00:36:36,009 --> 00:36:43,009
Vgs is minus 2 volts in that case Id again
in the same expression, we put the value of
158
00:36:50,799 --> 00:36:57,799
idss that is ten milliampere into 1 minus
the voltage is minus 2 volts and this is minus
159
00:37:04,150 --> 00:37:11,150
4 volts square and. So, this is equal to 10
milliampere 1 minus 1 by 2 square, which gives
160
00:37:30,009 --> 00:37:37,009
this to be drain current is 2.5 milliampere.
So, when the gate was shotted to source, the
161
00:37:44,130 --> 00:37:51,130
drain current was ten milliamperes and when
it is given a voltage of minus 2 the drain
162
00:37:53,069 --> 00:38:00,069
current is reduced to 2.5 milliamps and case
three and Vgs is equal to minus 4 volts. In
163
00:38:08,789 --> 00:38:15,789
this case the same expression I d, Idss is
ten milli amperes here 1 minus, minus 4 by
164
00:38:20,779 --> 00:38:24,489
minus 4 square.
165
00:38:24,489 --> 00:38:31,489
So, this is 0 1 by 1, 10 milliamperes 1 minus
1. So, this is 0 I d is 0 this is also understood
166
00:38:40,319 --> 00:38:47,319
actually because for the device the pinch
off voltage was 4 and this is that, where
167
00:38:48,809 --> 00:38:55,809
the current reduces to 0. All these points
you can see from the drain characteristics
168
00:38:56,700 --> 00:39:03,700
that when gate source voltage is 0, maximum
drain current for the n type JFET flows and
169
00:39:07,880 --> 00:39:14,880
when this is made negative Vgs is made negative
current falls and when Vgs is made equal to
170
00:39:17,400 --> 00:39:24,400
V p the magnitudes are same then the drain
current reduced to 0. So, this is the solution
171
00:39:27,380 --> 00:39:34,380
of the problem. let us another problem
this is problem 2 there is a circuit which
makes use of P-JFET and the circuit is this
172
00:40:20,589 --> 00:40:27,589
is R d this is R s this is R g and this is
minus Vdd.
173
00:40:30,819 --> 00:40:37,819
Because it is P type junction field of a transistor
and the current flows this way here. So, here
174
00:40:47,940 --> 00:40:54,940
what is available is that Vdd is 12 volts
sign is provided here. So, it is actually
175
00:40:57,109 --> 00:41:04,109
minus 12 volts magnitude is 12 volts and the
drain current Idss is 8 milliampere and punch
176
00:41:14,140 --> 00:41:21,140
through is 4 volts and I d is 4 milliampere
and Vds. When the 4 milliampere current flows
177
00:41:29,109 --> 00:41:36,109
Vds this voltage here this is equal to I can
show it here Vds, this is equal to 8 volts
178
00:41:43,160 --> 00:41:50,160
we have to find out the values of these two
resistors. Find values of resistors R d and
179
00:41:58,079 --> 00:42:05,079
R s this is the problem. Here this is the
circuit and this is a P-JFET which has Idss
180
00:42:13,910 --> 00:42:20,910
is 8 milliampere and V p has 4 volts in the
circuit this battery is 12 volts.
181
00:42:21,950 --> 00:42:28,950
And the drain current of 4 milliamperes gives
a voltage drop of 8 volts here. So, what is
182
00:42:31,999 --> 00:42:38,999
the value of these two resistors R s and R
d that we have to find out. So, the solution
183
00:42:42,680 --> 00:42:49,680
of this we again, use the same equation the
drain current is Idss 1 minus Pgs minus V
184
00:42:58,190 --> 00:43:05,190
p square and it is given that I d is 4 milli
amperes. So, 4 milli amperes Idss is 8 milliampere
185
00:43:14,569 --> 00:43:21,569
1 minus Vgs minus V p is four and we can find
out the value of the only unknown is Vgs.
186
00:43:31,329 --> 00:43:38,329
So, this milliampere, this milliampere is
cancelled and is very simple calculation from
187
00:43:40,869 --> 00:43:47,869
here we get Vgs this is equal to 3 volts Vgs,
this is 3 volts and you will remember that
188
00:44:00,059 --> 00:44:07,059
it say it say self bias circuit.
So, this 3 volts is to be provided by this
189
00:44:09,999 --> 00:44:16,999
resistor R s. So, once we know Vgs is equal
to 3 volts then we can get R s resistor is
190
00:44:23,749 --> 00:44:30,749
equal to Vgs. The magnitude of Vgs by I d
that will give the value of resistance. So,
191
00:44:36,329 --> 00:44:43,329
this is three volts and I d is 4 milliamperes;
that means, minus 3 amperes this gives R s
192
00:44:54,539 --> 00:45:01,539
equal to 750 ohms, we are find out the value
of R s and to find out the value of R d this
193
00:45:09,410 --> 00:45:16,410
drain resistor, we have to apply the we have
to sum up the voltages in the output circuit.
194
00:45:16,989 --> 00:45:23,989
Here we sum up the voltages and that will
give KVL kirchoff’s voltage law at output,
195
00:45:31,410 --> 00:45:38,410
when we apply we get Vdd equal to I d, R s,
R d plus Vds this is given twelve, twelve
196
00:45:49,719 --> 00:45:55,910
this is 4 I d’s 4 milliamps.
197
00:45:55,910 --> 00:46:02,910
So, minus 3 amperes into 750 ohms plus R d
plus this is 8 volts we solve for R d and
198
00:46:13,920 --> 00:46:20,920
R d comes out to be 250 ohms. This is the
way we can find out the values of the two
199
00:46:26,509 --> 00:46:33,509
resistors R s 750 ohms and R d
is 250 ohms. Let us take one more example
and let us take this that a EMOS, this is
200
00:47:01,229 --> 00:47:08,229
problem 3 E-MOSFET the data sheet is specifies
Vgs as 6 volts and I d on as 60 milliamperes
201
00:47:23,119 --> 00:47:30,119
V t as 2 volts. Determine the drain current,
drain current we have, we have to find out
202
00:47:34,039 --> 00:47:41,039
at Vgs equal to 4 volts . So, this is one
example we are taking a MOSFET this is the
203
00:47:48,259 --> 00:47:54,619
data available on the data the manufacturers
give with the data sheet.
204
00:47:54,619 --> 00:48:01,420
And this is what the problem is drain current
is to be determined at Vgs four volts. Now,
205
00:48:01,420 --> 00:48:08,420
the solution this data we can use to find
out the constant k the conductivity constant,
206
00:48:10,890 --> 00:48:16,410
conductance constant of the device of the
MOSFET this we discussed, when we were talking
207
00:48:16,410 --> 00:48:23,410
about the MOSFETs and this constant k. 1 of
the ways we can get is through this data and
208
00:48:23,930 --> 00:48:30,930
this was given to be I d on Vgs minus Vt square.
So, we substitute the values I d on is given
209
00:48:39,170 --> 00:48:46,170
as 60 milliampere and this is given 6 volts
this is 2 volts square and this gives 3.75
210
00:48:53,029 --> 00:48:58,309
milliampere per root square this is the constant
k.
211
00:48:58,309 --> 00:49:05,309
And then for the Emos, the drain current k
into Vgs minus V t square. This was the expression
212
00:49:11,869 --> 00:49:18,869
that expresses the drain current in the saturation
region. When we substitute the values this
213
00:49:22,170 --> 00:49:29,170
is 3.75 in milliamperes mind it, we are putting
in milliamperes and this 4 volts 2 volts square,
214
00:49:32,440 --> 00:49:39,440
then this comes out to be 15 milli ampere.
So, I d is equal to 15 milliampere this is
215
00:49:45,069 --> 00:49:52,069
what, we have we were suppose to determine.
So, this was the problem on E-MOSFET and similarly,
216
00:49:54,989 --> 00:50:01,989
it can be on D-MOSFET and such expression
can be used there to last example another
217
00:50:09,039 --> 00:50:16,039
this is on the amplifier common source amplifier
last and fourth problem this is a common source
218
00:50:17,170 --> 00:50:24,170
C S amplifier.
This circuit is this, this is R 1, R 2 this
219
00:50:46,959 --> 00:50:53,959
is 800 k this is 200 k kilo ohms and this
is R d which id 4 k and R d and this is 250
220
00:51:04,819 --> 00:51:11,819
ohms and this is also bypassed and the output
is taken here, this is the load of 8 k output
221
00:51:19,209 --> 00:51:26,209
is taken here and this is plus Vdd equal to
15 volts. So, here two things are to be determined
222
00:51:30,969 --> 00:51:37,969
this is the circuit where all parameters are
known and we have to find out. What is input
223
00:51:38,549 --> 00:51:45,549
impedance and voltage gain voltage gain? First
we draw the this is the input Vi and output
224
00:51:56,890 --> 00:52:03,890
is taken here first we have to draw the A
C equivalent for that D C voltage source is
225
00:52:05,170 --> 00:52:12,170
have to be grounded and these coupling capacitors
c 1 and c 2 are of sufficiently large value.
226
00:52:13,459 --> 00:52:18,619
And they have to be taken as short at the
frequency for which the amplifier is meant
227
00:52:18,619 --> 00:52:25,619
and this is bypass capacitor C that is also
large and this will be shorted. So, we can
228
00:52:25,619 --> 00:52:32,619
draw a simple equivalent A C circuit, this
is 8 k this is 4 k and this is all grounded
229
00:52:53,269 --> 00:53:00,269
this is the equivalent circuit this is R 1
this is R 2 this is 800 k and this is 200
230
00:53:02,979 --> 00:53:09,979
k. Now, first the input impedance, input impedance
we are seeing in the equivalent circuit that
231
00:53:12,489 --> 00:53:19,089
they are coming in parallel and to this will
be what is the impedance of the amplify of
232
00:53:19,089 --> 00:53:26,089
the device itself, then the input here. So,
the input impedance of the amplifier is R
233
00:53:27,579 --> 00:53:34,579
1 in parallel to R 2 in parallel with the
Z i of the device.
234
00:53:36,130 --> 00:53:43,130
This is for the FET which is very high and
remember that in parallel combination very
235
00:53:46,910 --> 00:53:53,910
high resistance is can be neglected. So, this
is actually R i simply R 1 in parallel with
236
00:53:54,749 --> 00:54:01,749
R 2 and this is 800 k parallel 200 k. So,
this comes out to be 160 kilo ohms. This is
237
00:54:04,729 --> 00:54:11,729
the input impedance as we will measure here
and then gain the g m was given for this actually,
238
00:54:15,769 --> 00:54:22,769
which i just forgot to write that g m for
the device is given 2.5 milliamperes per volt
239
00:54:26,160 --> 00:54:33,160
and which is also written as a as a milimoles.
So, part b the gain A v which is simply g
240
00:54:40,059 --> 00:54:47,059
m into R l effective load, effective load
is the parallel combination of these two.
241
00:54:47,739 --> 00:54:54,739
So, hence R l in the present case is 4 k and
8 k and that comes out to be 2.6 k. So, then
242
00:54:59,849 --> 00:55:06,849
A v becomes 2.5 into 10 to power minus 3 that
is the value of g m and into 2.6 k. So, this
243
00:55:12,319 --> 00:55:19,319
is 6.5. The voltage gain for the common source
amplifier is 6.5. So, these are the few typical
244
00:55:26,279 --> 00:55:33,279
examples which I took for the numerical problems
that finishes our this unit. And here what
245
00:55:35,380 --> 00:55:42,380
we have done, we started with the junction
field of a transistor, we gave how it is constructed,
246
00:55:42,769 --> 00:55:47,829
what are, what is the structure of junction
field of a transistor, how does it work, what
247
00:55:47,829 --> 00:55:54,079
are its I v characteristics, then we went
for MOSFETs.
248
00:55:54,079 --> 00:56:01,079
And MOSFETs the D-MOSFET depletion, MOSFETs,
MOSFETs and enhancement MOSFET, depletion
249
00:56:02,039 --> 00:56:09,039
MOSFET can be used as indepletion mode as
well as in enhancement mode and enhancement
250
00:56:10,199 --> 00:56:17,199
mode there is nochannel existing in the beginning,
but the applied voltage at the gate creates
251
00:56:19,789 --> 00:56:26,789
the channel and enhancement mode then the,
correct the we developed a model for the transistor.
252
00:56:29,099 --> 00:56:36,099
Which is applicable for junction field of
a transistors and for FET and also the we
253
00:56:37,910 --> 00:56:44,910
analyzed the three amplifiers common source
amplifier is most widely used and common and
254
00:56:45,150 --> 00:56:52,150
drain is like emitter follower, which is used
for matching purposes and then we took CMOS
255
00:56:52,690 --> 00:56:59,690
devices and we indicated that CMOS gives the
lowest loses very high speed of a switch in
256
00:57:02,699 --> 00:57:09,699
and most advanced circuits are made in CMOS.
So, this is this module is all about.