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We continue our discussion, on self bias.
Now, we take some design procedure that is
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how to know the components the values of various
a resistances and voltages and current in
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00:00:43,680 --> 00:00:50,680
the self bias circuit this comes under design
procedure. So, let us consider first the circuit
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00:00:52,430 --> 00:00:59,430
the simple circuit which we were discussing
was this
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00:01:31,899 --> 00:01:38,899
This was the self bias circuit and design
implies that we should know the value of current
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00:01:41,700 --> 00:01:48,700
I D at the Q point. So, this actually we write
as I D Q at and the voltage V D S and this
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00:01:58,390 --> 00:02:05,390
a gate source voltage V G S and at the Q point
this is also to be noted and this we shall
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00:02:10,050 --> 00:02:17,050
write V G S Q, Q point the quotient point
or operating point. We have to decide and
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00:02:20,180 --> 00:02:27,180
a since mostly these procedures which we are
doing they are going to be adapted to make
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a amplifying circuit out of a MOSFET or junction
field effect transistor. So, from the characteristics,
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how we arrive at this values that we will
see. And then we require the value of this
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00:02:47,650 --> 00:02:54,650
resistance R D R S about R G we have already
talked R G is a there is no current flows
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through this resistance.
So, actually, R G this probe this is a gate
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terminal acts as a voltage probe a voltage
probe has to have a very high resistance.
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So, normally, R G is taken 50 kilo ohms or
100 kilo ohms. So, this we say now this is
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known the these two resistances have to be
determined for the circuit and that will be
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governed by the drain characteristics what
are what type of drain characteristics drain
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characteristic tell us the amount of drain
currents which flow in the circuit and what
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are the various voltages. So, this all comes
under design procedure and we proceed to find
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out these values.
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00:04:14,629 --> 00:04:21,629
Now, the two equations we arrived earlier,
by simple summing up of voltages these equations
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where V D D equal to V D S plus I D R D plus
R S this was 1 equation, which comes simply
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when we sum up voltages in the output circuit.
Another equation is obtained when we sum up
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voltages here and from there came the equation
V G S equal to minus I D R S this can be return
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in the form I D the drain current is equal
to minus V G S by R S this is the equation
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00:05:17,729 --> 00:05:24,729
of a straight line. And when this a straight
line is plotted on the trans conductance curves
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of the device. That is this is trans conductance
curve
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and this is the line when to be plot on this
is like that this is called bias line
and the slope it is slope of bias line gives
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the this depends on the value of R s.
So, if we choose R S that will shift this
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slope; that means, thus base line will move
across this point. So, once we choose the
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operating point Q than we know the slope and
thus R S is known. And from these curves we
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also know the value of the drain current at
Q point and V G S at Q point. So, three parameters
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are known R S the resistance in the circuit
is known that will be determined by the slope
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and slope is dependent on where we choose
the operating point. So, normally we choose
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somewhere, in the center enhance the slope
will give the value of R S and this slope
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00:07:22,360 --> 00:07:29,360
of the line is actually minus 1 by r.
So, this will give the value of R S. And at
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00:07:30,490 --> 00:07:36,909
the operating point what is this drain current
and what is this voltage? Now, few points
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00:07:36,909 --> 00:07:43,909
we discussed, when we were discussing, the
bipolar transistor and it is circuit. Than,
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00:07:44,460 --> 00:07:51,460
we will recall from there that these are the
DC values and normally in an amplifier we
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00:07:53,210 --> 00:08:00,210
will use AC signals. So, the variation of
current will occur taking this DC value at
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00:08:03,539 --> 00:08:10,289
it is a center. So, the variations will be
this is the DC value than AC variations will
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00:08:10,289 --> 00:08:17,289
be along this. And similarly, the input voltage
is the gate source voltage.
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00:08:17,689 --> 00:08:24,689
So, when superimpose AC signal on this than
these variations will occur a across this
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Q point value of the gate source voltage.
So, this way three parameters are now known
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the I D Q V G S Q and resistance R all are
known than the this V G S and this I D this
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will give you actually, the value of a V D
S at the Q point also let us, see the output
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characteristics the drain characteristics
they, where like this.
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This is V G S V D S I D and if we choose the
operating point say for example, here than
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this is I D Q the same as we have we got I
D Q here. So, that we mark here and from we
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00:09:45,720 --> 00:09:52,720
extended and we get V G S Q I D Q and this
is V D S Q. So, once V D S Q is known the
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00:09:57,370 --> 00:10:04,370
battery, which we use in the circuit this,
which is the single D C source in the circuit
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00:10:06,950 --> 00:10:13,950
normally for the devices. This is the currently
used integrated circuits make use of V D D
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00:10:15,860 --> 00:10:22,860
of 5 volts, when discrete devices are use
than this voltage can be a high can be 10
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or 12 15 30.
So, this way V D D is known and then we use
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00:10:33,990 --> 00:10:40,990
this first equation which we have we had written
this one this equation here now I D Q is known
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00:10:46,779 --> 00:10:53,779
R S is known so this is known, this is known
and V D S Q is known V D D that is the battery
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00:10:54,920 --> 00:11:01,920
source, which we are using that we a anyway
no. So, this way R D can be calculated. So,
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00:11:03,360 --> 00:11:10,360
this way we find out all the parameters of
the circuit the R D can be calculated from
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00:11:18,100 --> 00:11:25,100
Kirchhoff’s voltage law equation for the
output circuit. Now, I D Q and D S Q this
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00:11:43,720 --> 00:11:50,720
is I D Q this is D S Q they are taken here
from the these, a drain characteristics there
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00:11:52,589 --> 00:11:59,589
is another procedure, which is a often employed
and that is it is the thumb rule that I D
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Q can be safely taken as IDSS by 2.
So, wherever, the largest current a through
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00:12:15,050 --> 00:12:21,470
the device this parameter is normally, given
by the manufacturer. So, once it is known,
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when it is safest to take I D Q as half of
IDSS similarly, V D S Q can be taken as one
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third of V D D or even half of this. So, this
way instead of a using these characteristics
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I D Q and V S Q can be known from here. So,
we have determined all the parameters of this
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circuit R D R S V D S I D V D D and R G and
that is the completed design of the self bias
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00:13:07,389 --> 00:13:14,389
circuit. Self bias is often used for a junction
field effect transistor and it can also be
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00:13:16,480 --> 00:13:23,480
used, where negative V G S is required in
the p MOSFETS particularly.
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Now, the another biasing circuit is voltage
divider bias it say broader circuit and infect
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it can be used for getting positive or negative
gate source voltage both can be by adjusting
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proper resistances this can be use. So, this
is having a wider use and of course, for e
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00:13:59,529 --> 00:14:06,529
MOSFET this is the one, which is used. Now,
the circuit is
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this is a V D D this is R D R S R 1 and R
2 here this voltage V D D is divided this
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00:14:51,480 --> 00:14:58,480
network R 1 R 2 this x as a voltage divider.
So, that is why the name voltage divider here
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this is V D S and this is V G S
and this can be used, because we can get this
an important. We can get positive or negative
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V G S therefore, it can be used for n and
p JFET’S or MOSFET’S any kind of MOSFET,
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00:15:52,040 --> 00:15:59,040
this circuit first we Thevenize it and the
Thevenized by applying.
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Thevenize theorem we Thevenize the circuit
and what we get is this the Thevenized circuit
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00:16:18,120 --> 00:16:25,120
is this. This V D D and this is the resistance
we will equivalent the Thevenize equivalent
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of this two resistances we will tell that
how this is determined and this is the voltage
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00:16:49,800 --> 00:16:56,800
source V G this is I D R D and this is R S.
This is Thevenize equivalent circuit and here
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the value of a equivalent thevenize resistance.
Just you remind you that by applying Thevenize
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theorem we can find out this resistance than
this resist for this resistance this D C source
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is to be grounded now, what is the equivalent
resistance between these points between this
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and ground.
So, that is to be determined now once we ground
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this terminal also this terminal also than
this is like this. This is R 1 this is R two
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00:18:05,780 --> 00:18:12,780
so, as for as this point is concerned this
Thevenize resistance are this is equal to
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00:18:14,470 --> 00:18:21,470
the parallel combination of this two resistances,
which is R G is simply, R 1 R 2 by R 1 plus
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00:18:29,150 --> 00:18:36,150
R 2 this is thevenize equivalent resistance.
The voltage is what is the voltage? Which
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00:18:38,750 --> 00:18:44,490
this, V D D produces between gate and source.
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00:18:44,490 --> 00:18:51,490
So, the equivalent circuit actually, will
be this, this is V D D and this is the two
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resistances this is R 1 this is R 2 and here
we have to find out this is V G. So, obviously,
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the DC current through this circuit is the
current is V D D by R 1 plus R 2. And the
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00:19:27,620 --> 00:19:34,620
voltage drop across R 2 is simply, that is
V G is simply R 2 V D D this current into
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this resistance so R 2 into this current so
R 1 plus R 2 this is V G. Now, once this is
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a there this current we take as I G and we
apply the summation of voltages that is Kirchhoff’s
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voltage law in the gate source circuit of
this. So, applying Kirchhoff’s voltage law
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at gate source circuit of Thevenize’s equivalent
circuit we get the equation V G S plus I D
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R S minus V G plus I G R G is equal to 0,
here this is V G S.
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So, we start with we are finding out the summation
of voltages we are writing the equation for
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summation of voltages in this circuit. So,
V G S than I D into R S than minus V G plus
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I G and R G equal to 0 where this V G is given
by this expression and a I G here is a 0.
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Since, why I G is zero? Because all gates
are operated in reverse bias, so, I G is 0
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and then we get from here when we put.
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So, this term goes and we simply get V G S
is equal to V G minus I D R S this is the
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fundamental equation. And this clearly shows,
that V G S the gate source voltage can be
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obtained either negative or positive, if it
is to be positive than V G must be greater
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than I D R S the drop across this resistance
should be smaller than V G that will give
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positive value of V G S. Or if negative value
is decide than the drop across resistance
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R S has to be higher than V G. So, this is
actually, this is the equation of load line
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or call it bias line
and this is to be plotted on the transfer
characteristics of the device to find various
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important parameters. So, when we plot these
here these are the characteristic
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this is V G S I D the output current and input
voltage gate source voltage.
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And this is the equation of a straight line
from here at this point V G S is 0, when V
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G S is zero than current I D from here we
will get I D equal to V G by R S this is the
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point and to get this point here I D is 0.
So, this is the point, which gives the value
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of V G and where this a load line crosses
cuts the transfer characteristics this is
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the Q point. And a now we will proceed to
find out for example, what is how to get negative
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and positive voltages first let us take for
N MOS on N MOSFET where, V G S is positive
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and for positive from this equation base line
equation load line equation V G has to be
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greater than I D R S. We substitute here the
value of a V G value of V G is here in this
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equation. So, this we substitute here and
let us, see what we get.
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So, when we substitute the value we get R
2 V D D by R 1 plus R 2 this should be this
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should be greater than I D R S or V D D by
1 plus R 1 by R 2 should be greater than I
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00:27:12,669 --> 00:27:19,669
D R S. This in equality can be satisfied;
obviously, if R S is choosen very large, if
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R S R 2 is chosen very large than this in
equality can be easily satisfied in the limiting
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case R 2 in this circuit in the voltage divider
circuit R 2 can be taken as infinity. Almost
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approaching infinity and infect it can be
taken as infinity a approaching R infinity
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00:28:10,769 --> 00:28:17,769
in what is R infinity, the absence of the
resistance. If R 2 is removed from the circuit,
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than we satisfy this in equality easily.
So, the circuit is reduce to this we remove
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from here R 2. So, that the circuit is
this is N M O S this is R S and this is R
1 this is V D D and this is R D. Here we will
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00:29:22,230 --> 00:29:29,230
absorb V G this is the circuit biasing circuit
just one resistance here instead of in the
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00:29:37,820 --> 00:29:44,820
self bias the resistance was here. So, we
can bias we can get a positive gate source
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voltage, which is required for example, for
N M O S here this is N M O S
and if we intent to get a negative voltage.
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When negative gate source voltage is required
negative V G S is required for example, for
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biasing n JFET or p MOS than, V G has to be
smaller than I D R S
and when we substitute for V G. We get is
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00:31:01,630 --> 00:31:08,630
less than I D R S or V D D 1 plus R 1 R 2
this is this has to be less than I D R S this
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00:31:24,299 --> 00:31:31,299
equality in equality can be satisfied, if
R 1 is very large, if R 1 is made very large
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and in the limiting case R 1 can be infinitely
high. That means, if we remove R 1 than we
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00:31:54,090 --> 00:32:01,090
will get a negative gate source voltage and
the circuit will be the same as we have got
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for self bias that is the this circuit will
be reduced voltage divider bias, if we remove
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00:32:14,419 --> 00:32:21,419
this resistance R 1 here to make it infinity
that will reduce this circuit to this form.
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00:32:33,809 --> 00:32:40,809
We are this is V D D, R D, R S and this voltage
this is of course, V D S this is V G S and
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this is R 2, which is same as we have taken
earlier R J. So, this is the circuit to get
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00:32:57,669 --> 00:33:04,669
a negative gate source voltage from the voltage
divider bias and we can get the positive also
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00:33:08,769 --> 00:33:15,769
as we have seen in the previous case. So,
this way this voltage divider bias can be
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00:33:19,889 --> 00:33:26,889
used and this is the one, which is a quit
widely used with the most devices and a thus
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00:33:27,220 --> 00:33:34,220
we finish the biasing of the FETS and MOSFETS
any kind of FET junction field effect transistor
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00:33:43,299 --> 00:33:50,299
or MOSFET can be biased in by using these
two biasing networks.
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00:33:53,940 --> 00:34:00,940
The next thing, which we are going to have
that is a small signal of parameters, a small
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00:34:02,700 --> 00:34:09,700
signal
F E T or MOSFET parameters this
we are going to a study now for V J T. We
have seen that a beta the current gain beta
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00:34:44,030 --> 00:34:51,030
for bipolar junction transistor B J T was
most popular and this was the ratio of output
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00:34:55,850 --> 00:35:02,850
current to input current. This parameter beta
appear in the expressions for input impendence
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00:35:07,030 --> 00:35:14,030
z in or voltage gain and. So, on field effect
transistor or MOSFETS they are voltage operative
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00:35:22,190 --> 00:35:29,190
device here the important parameter is
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00:35:38,250 --> 00:35:45,250
Trans conductance of the device, which is
written as G M.
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00:35:45,260 --> 00:35:52,260
So, G M Trans conductance parameter is a most
important parameter for a junction field effect
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00:35:54,030 --> 00:36:01,030
transistor or for MOSFET. And first we will
define it and then we will go for other is
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00:36:05,090 --> 00:36:12,090
no signal parameter. So, Trans conductance
G M this is defined as, because we will be
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00:36:21,560 --> 00:36:28,560
concerned with the ac operation of the device.
So, we can define
the AC drain current by a c. So, when on the
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00:36:39,060 --> 00:36:46,060
Q point when we superimpose the signal what
is I D and V G S the ratio of the two, which
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00:36:47,750 --> 00:36:54,750
can be shown equal to let us, see for first
for A F E T the J F E T here this is the Trans
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00:37:01,110 --> 00:37:08,110
conductance curve and a this is a V p and
this is I D this is V G S.
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00:37:16,540 --> 00:37:23,540
So, this curve is the Trans conductance curve
and at the operating point, we draw a small
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00:37:25,580 --> 00:37:32,580
tangent and we find out, this is change in
the drain current I D and this is the change
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00:37:36,290 --> 00:37:43,290
in a gate voltage. So, this ratio can be return
as change in ID by change in V G S at constant
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00:37:52,570 --> 00:37:59,570
V D S this is the way it is defined. Now,
this is obvious that, if we choose Q point
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00:38:05,300 --> 00:38:12,300
here here here here than every where G M is
changing and G M is highest near this I D
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00:38:15,270 --> 00:38:22,270
D S show circuit drain source current when
gate is shorted to source. This is the highest
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00:38:25,770 --> 00:38:32,770
value and the slope is highest here. So, he
re this G M will have highest value the highest
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00:38:34,870 --> 00:38:41,870
value of G M is a designated as a g m o this
is the highest value of G M.
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00:38:54,950 --> 00:39:01,950
Which, is actually, which is the Trans conductance
value near IDSS point on the trans conductance
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00:39:10,720 --> 00:39:17,720
curve. Now, g m o can be determine as we are
seeing from the trans conductance curve here
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00:39:22,830 --> 00:39:29,830
by taking this operating point in the visinity
of IDSS or it is g m o can also be obtained
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00:39:41,280 --> 00:39:48,280
from the simple relation g m o is equal to
2 IDSS by V p from here also g m o can be
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00:39:58,620 --> 00:40:05,510
obtained. Now, once g m o is known either
from that graph directly or by using these
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00:40:05,510 --> 00:40:12,510
two parameters. Than we require Trans conductance
value at the operating point and as I said
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00:40:15,290 --> 00:40:22,290
because the slope is changing. So, G M is
changing quite a bit along the Trans conductance
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00:40:23,350 --> 00:40:28,090
curve.
So, for accurate analysis at the Q point the
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00:40:28,090 --> 00:40:35,090
value of G M the Trans conductance is required
and. So, from g m o the maximum value, which
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00:40:36,990 --> 00:40:43,250
is either, provided by the manufacturer or
can be obtained from the data provided by
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00:40:43,250 --> 00:40:50,250
the manufacturer. We can find g m for any
value of V G S depending on our Q point. We
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can get from here
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00:41:09,270 --> 00:41:16,270
this is the equation, which can be used to
get value of trans conductance parameter from
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00:41:18,560 --> 00:41:25,560
g m o by substituting the value of at what
gate source voltage we require this value.
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We can get from here where here this is the
pinch of voltage.
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This example we took for is graph we took
for a J F E T for M O S F E T the curve will
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be like this
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00:42:00,680 --> 00:42:07,680
and here we choose the operating point and
we draw. So, the same thing we get the value
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00:42:09,400 --> 00:42:16,400
of I D change in I D and this is the change
in V G S
the ratio will give g m for M O S F E T at
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00:42:31,390 --> 00:42:38,390
the Q point. The another a small signal parameter,
which we require and that is the small signal
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00:42:43,370 --> 00:42:50,370
output resistance this is a defined, as it
is return as either R D or as R D S. This
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00:42:58,190 --> 00:43:05,190
is actually, the resistance of the channel
in the circuit and this is defined, R
D S is equal to
output voltage by output current
that is
V D S AC value of the drain source voltage
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00:43:53,520 --> 00:44:00,520
and the AC drain current, which is same as
changes in V D S by changes in the drain current
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00:44:09,370 --> 00:44:16,370
at this is constant V G S constant. This is
actually, if we look at the drain characteristics
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this was I D and this is V D S than this resistance
represents this slope of the drain characteristics
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00:44:44,190 --> 00:44:46,360
in the saturation region.
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Which is a nearly, horizontal and that state
that r d s is very large very high and for
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J F E T, R D S or simply R D this is 50 kilo
ohms to several hundred kilo ohms and for
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M O S F E T S r d s is up to 100 kilo ohm.
Actually, when we take the circuit actual
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analysis we will see that normally, a smaller
resistance will be put in parallel with this
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00:46:03,220 --> 00:46:10,220
r d s. So, r d s effect that way will be negligibly
a small. So, this two most important parameters
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we discussed, one was trans conductance, which
will appear for example, we want to know what
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is the voltage gain of a M O SF E T amplifier
than their essentially one of the parameters,
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which will appear is a trans conductance parameter.
And then we discussed, about the a small signal
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output resistance of the device and that is
normally, very high for J F E T or for M O
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00:46:52,360 --> 00:46:59,360
S F E T the next thing, which we take that
is a small signal F E T model.
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00:47:04,110 --> 00:47:11,110
A small signal F E T and also the same model
for M O S F E T, when we were discussing,
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the bipolar transistor and it is a model we
have already seen the utility. In a circuit,
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when the device is replaced by it is modal
that unables the analysis by using simple
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algebraic equation summation of voltages etcetera
or current. We can find the value of output
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voltage versus input voltage, which will be
the voltage gain similarly, if input impendence
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is to be determined or any other parameter
is to be determined than a small signal modal
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is very useful.
So, we are now developing a small signal modal
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for F E T, which also applicable for M O S
F E T S. Now, any two conductors when separated
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00:48:37,130 --> 00:48:44,130
with a dielectric insulator there is a capacitance
associated. So, when we talk of the exact
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00:48:48,180 --> 00:48:55,180
modal of the device there are several conducting
paths in the device there will be capacitances.
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For example, between gate and source there
will be a capacitance similarly, between gate
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00:49:10,550 --> 00:49:17,550
and drain there will be a capacitance. So,
if we talk of the exact module, which we will
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simplify of course, we will have to take into
a account these capacitance and all kinds
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00:49:25,980 --> 00:49:32,980
of resistance. So, the modal for the device
will be this.
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This is the gate terminal gate terminal here
and this is this whole is source and here
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is drain this is that a output is resistance.
Which we talked R D S and this is the current
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source and this is g m into v g s and this
is the capacitance between gate and drain
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00:51:03,650 --> 00:51:10,650
and this is the capacitance between gate and
source and this is the resistance between
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00:51:15,370 --> 00:51:22,370
gate and source. This is the exact modal,
but we can simplify for example, we are taking
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of moderate frequencies and this frequencies
will be normally up to few tense of kilo Hertz.
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00:51:40,230 --> 00:51:47,230
They are these impendence offered by this
two capacitances they are very high and very
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00:51:49,160 --> 00:51:56,160
high impendence’s becomes almost they can
be taken out from the circuit.
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00:51:58,580 --> 00:52:05,580
So, we can drop capacitances C g s and C g
d this capacitance’s we can drop for the
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00:52:22,840 --> 00:52:29,840
frequencies, which are currently presently
under discussion. Also this resistance between
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00:52:34,340 --> 00:52:41,340
gate and source is very high for j f e t this
is hundreds of kilo ohms r g s for J F E T.
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00:52:50,730 --> 00:52:57,730
This is
several 100 kilo ohms and for M O S F E T
S for M O S F E T S at least two orders of
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00:53:06,550 --> 00:53:08,320
magnitude higher.
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00:53:08,320 --> 00:53:15,320
So, this resistance can be also taken out
than what we are left is this modal, this
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00:53:45,080 --> 00:53:52,080
is gate terminal, this is source, and this
is drain and this is R D S and this is the
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00:53:58,460 --> 00:54:05,460
current source. This has the dimensions of
the current source, because g m we know g
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00:54:12,580 --> 00:54:19,580
m is I D versus v g s. So, g m into v g s
is equal to I D. So, this is the current source
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00:54:32,660 --> 00:54:39,660
and here and this current source is that the
magnitude of this current is dependent on
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00:54:43,120 --> 00:54:50,120
the gate source voltage whatever, voltage
we apply here v g s. So, this is the modal,
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which we will be using and remember it is
very simple modal this is one resistance,
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which we will see when we put actual resistance
here, than the two resistances in parallel
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one very high resistance one low resistance
than the effective resistance of the parallel
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00:55:14,090 --> 00:55:20,300
combination will be closer to the a smaller
resistance.
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00:55:20,300 --> 00:55:27,300
So, this will also disappear and so the current
source remains and this we are going to use
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for the analysis of F E T amplifiers. We are
going to a study three amplifiers the common
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source amplifier, the common drain amplifier
and common gate amplifier like B J T can be
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used in three different configurations. So,
is the case, with F E T this can also we used
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00:55:55,910 --> 00:56:02,910
for three different configurations. So, we
will drive the useful parameters for all these
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00:56:06,260 --> 00:56:13,260
amplifiers using this modal. And we will see
that we will come to a net conclusion that
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00:56:14,950 --> 00:56:21,950
like common emitter amplifier in B J T common
source amplifier with MOSFETS and a with the
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00:56:23,850 --> 00:56:30,850
FET’S is most widely used and we will be
is studying that.