1 00:00:25,339 --> 00:00:32,339 In the previous lecture, we studied the working and fabrication of a junction field effect 2 00:00:34,870 --> 00:00:41,870 transistor and we continue the investigations for any electronic device. One of the most 3 00:00:43,680 --> 00:00:48,820 important characteristics are current voltage characteristics of the device. 4 00:00:48,820 --> 00:00:55,820 So, we take I V characteristics for n type JFET, we will not a spend time, we will not 5 00:00:57,899 --> 00:01:04,899 duplicate their studies by taking P type JFET, because they are identical except at few places 6 00:01:06,610 --> 00:01:13,610 as I. Discussed in the previous lecture that the gate source voltage will be positive in 7 00:01:14,170 --> 00:01:21,170 the P type junction field effect transistor, while it is negative in the case of n type 8 00:01:21,579 --> 00:01:28,579 JFET. So, the characteristics which we have already drawn, they were this. 9 00:01:58,490 --> 00:02:05,490 This is drain current and this is V D S in volts and this is in normally mill amperes 10 00:02:08,830 --> 00:02:15,830 and these are the characteristics. This was V P, the pinch of voltage. And these are the 11 00:02:21,520 --> 00:02:28,520 characteristics for V G S equal to 0, this is minus 1 volt, minus 2 volt, minus 3 volt. 12 00:02:33,069 --> 00:02:40,069 And here these characteristics we will get for example, for minus 4 volts. these I-V 13 00:02:42,969 --> 00:02:49,030 characteristics, the drain characteristics of a the junction field effect transistor, 14 00:02:49,030 --> 00:02:56,030 they can be divided into 3 different regions. One is, this region from here to here, this 15 00:03:01,349 --> 00:03:08,349 is a ohmic region. From here to here this is saturation region and here this is the, where the drain current 16 00:03:33,489 --> 00:03:40,489 drops to 0, that is the CUT-OFF region. 17 00:03:41,930 --> 00:03:48,930 So, the characteristic has three regions, ohmic region, saturation region. Saturation 18 00:04:05,989 --> 00:04:12,989 region is also called actually constant current region, here current is almost constant so, 19 00:04:13,040 --> 00:04:20,040 also called constant current region. And third is CUT-OFF region, these are the three regions. This region where 20 00:04:44,669 --> 00:04:51,669 the current is starts saturating before that the region is called ohmic region. So, first 21 00:04:54,389 --> 00:05:01,389 we take ohmic region, ohmic region obviously, is of a V D S values greater than 0 and less 22 00:05:18,770 --> 00:05:25,770 than V D S, less than V P, the pinch of voltage. And here the we have, we are seeing from the 23 00:05:30,539 --> 00:05:37,539 plot, that current is varying from linearly with the change of V D S voltage. 24 00:05:40,330 --> 00:05:47,330 So, in this region V D S is a small and it is below pinch. So, there is no pinch off of the channel and the current increases. 25 00:06:11,330 --> 00:06:18,330 Now, when we increase the gate source voltage, then the resistance increases the changes 26 00:06:24,379 --> 00:06:31,039 slope. You see, slope is changing, this is voltage, this is current. So, the slope gives 27 00:06:31,039 --> 00:06:33,720 inverse of the slope gives the resistance. 28 00:06:33,720 --> 00:06:40,720 So, here the slope is changing and this you understand that when we increase the gate 29 00:06:40,960 --> 00:06:47,960 source voltage. This gate source voltage when we increase, this a channel conductance false, 30 00:06:52,259 --> 00:06:58,039 the resistance increases. For the reasons which we have discuss that, by increasing 31 00:06:58,039 --> 00:07:05,039 negative potential on the gate the depletion regions will a spread more, making the channel 32 00:07:06,979 --> 00:07:09,060 narrower. 33 00:07:09,060 --> 00:07:16,060 So, pinch off does not occur, but the resistance varies on the gate source voltage, the resistance 34 00:07:25,949 --> 00:07:32,949 in the ohmic region varies from 100 ohms to almost 10 kilo ohms. And obviously, this is 35 00:07:39,300 --> 00:07:46,300 a voltage controlled; it is a voltage controlled resistance, this voltage V G S, this is controlling 36 00:07:54,530 --> 00:08:01,530 the resistance. Here the slope is changing and which is a function of V G S and in this 37 00:08:08,099 --> 00:08:15,099 JFET, junction field effect transistor can be used as a voltage controlled resistor. 38 00:08:49,990 --> 00:08:56,990 V C R, voltage controlled resistance and so, this is about the ohmic region. And then we 39 00:09:07,920 --> 00:09:14,920 go for saturation region. In the saturation region; and this saturation regions is starts 40 00:09:23,890 --> 00:09:30,890 from this point and this point is actually V D S, the drain source voltage has to be 41 00:09:34,480 --> 00:09:41,480 higher than V G S minus the pinch off voltage so, this line. Here this is at, the point 42 00:09:49,590 --> 00:09:56,590 V D S is greater or equal to V G S minus V P is what I have written here, that saturation 43 00:10:00,310 --> 00:10:07,310 region is starts when V P S is equal or greater than this value. In this region, the drain 44 00:10:09,150 --> 00:10:16,150 current I D depends entirely on the gate source voltage. V D I drain current I D does not 45 00:10:28,350 --> 00:10:35,350 depend on drain source voltage V D S, but it is a function, drain current is a function 46 00:10:41,090 --> 00:10:48,090 of V G S gate source voltage. Here, this current is varying as we are changing 47 00:10:50,340 --> 00:10:57,340 the gate source voltage, it is a constant with respect to change in V D S. These are 48 00:10:58,810 --> 00:11:05,470 almost horizontal lines, the drain current is not changing when we are varying the V 49 00:11:05,470 --> 00:11:12,470 D S in this constant current region and that is why, it is called a constant current region. 50 00:11:16,470 --> 00:11:23,470 Here, the dependence of a drain current on the gate source voltage has a non-linear relationship. 51 00:11:31,070 --> 00:11:38,070 And this relationship cab be expressed by a square law and that is I D, the drain current 52 00:11:39,130 --> 00:11:46,130 is equal to I D S S into, 1 minus, V G S by V P, square this is an important equation. 53 00:11:54,860 --> 00:12:01,860 And this gives the relationship between drain current I D is expressed in terms of gate 54 00:12:15,950 --> 00:12:22,950 source voltage by this equation and from this we will use this equation very frequently. 55 00:12:25,740 --> 00:12:32,740 Now, very important thing when the device is to be used, when a junction field effect 56 00:12:32,930 --> 00:12:39,930 transistor is to be used as a amplifying device to amplifies signals. Then, JFET is operated 57 00:12:43,080 --> 00:12:49,820 in this region in the saturation region, it is operated. 58 00:12:49,820 --> 00:12:56,820 And this relationship, non-linear relationship between I G and V G S gate source voltage 59 00:13:00,510 --> 00:13:07,510 dependence I D, this has a this relationship as express by this equation is parabolic in 60 00:13:09,130 --> 00:13:16,130 nature. So, we can get actually the transfer curves, transfer characteristics of JFET, why transfer? This is the drain current 61 00:13:36,540 --> 00:13:43,540 and this is the gate source, the true are, they not the part for example of the output 62 00:13:43,800 --> 00:13:50,800 current is I D, but this is a gate source voltage so, transfer. So, the curve is a parabolic, 63 00:13:55,110 --> 00:14:02,110 this is I D and this is V G S gate source voltage, 0 positive and here it is negative. 64 00:14:10,980 --> 00:14:17,980 And this expression when V G S is 0, here the maximum current I D. Here, this is I D 65 00:14:25,730 --> 00:14:32,730 S S drain current, when gate is shorted with the source, that means, gate is at 0 potential, 66 00:14:39,850 --> 00:14:46,850 that is I D S S. And so, this is that current and as we are changing V G S more negative 67 00:14:53,660 --> 00:15:00,660 more negative, drain current is falling and here it is OFF. So, this is the parabolic 68 00:15:05,190 --> 00:15:12,190 plot and this value where this drain current drops to 0, this we call as V G S great source 69 00:15:17,370 --> 00:15:24,370 voltage OFF, these are the drain characteristics for the n type JFET. The curve will be in 70 00:15:30,570 --> 00:15:37,570 the appose, because for a P type JFET, the gate source voltage is positive. So, it will 71 00:15:39,420 --> 00:15:46,420 be this way, this is drain current and this is V G S and this is this. And this is the 72 00:15:53,280 --> 00:16:00,280 magnitude equal to this which is also V P. 73 00:16:00,550 --> 00:16:07,550 The pinch off voltage here. And so, from here, from this transfer curve, we get that the magnitude of V P is the same as V G S 74 00:16:28,570 --> 00:16:35,570 OFF, what is V G S OFF? V G S OFF is that voltage, gate source voltage which puts drain 75 00:16:38,170 --> 00:16:45,170 current to 0. And we can see from here, from this curve when drain current is 0, then V 76 00:16:51,120 --> 00:16:58,120 G S OFF is equal this relationship, we get write from this equation 1 by putting id equal 77 00:17:01,560 --> 00:17:08,560 to zero. Then from here we get V G S, the magnitude of a V G S OFF we will call, because 78 00:17:08,600 --> 00:17:14,740 that will put the drain current 0 and that come that will come out to be V P, that is 79 00:17:14,740 --> 00:17:21,740 why, I have written here V P or it is same as V G S OFF followed. 80 00:17:24,380 --> 00:17:31,380 From this curve we are getting this plot and if we plot changes in I D as a function of 81 00:17:35,009 --> 00:17:42,009 changes in the gate source voltage, then this is parabolic behavior, which is expressed 82 00:17:42,970 --> 00:17:49,970 by this equation. We also see here that V G S OFF makes I D zero and that gives right 83 00:17:51,299 --> 00:17:58,299 from this equation V P equal to V G S OFF. So that, equation 1 can also we written as 84 00:18:02,139 --> 00:18:09,139 I D, I D S S, V G S, V G S OFF, we can write that equation let us call this equation 2. 85 00:18:28,659 --> 00:18:35,659 Now, one thing is certain that since, in this equation IDSS represent the highest current 86 00:18:42,629 --> 00:18:49,629 in the JFET. So, this quantities here in the bracket, in this bracket; this has to be positive 87 00:18:56,019 --> 00:19:03,019 and less than 1. So, what have said is this that, since IDSS represents maximum current 88 00:19:11,950 --> 00:19:18,950 for JFET, the quantities in the bracket, this has to be positive and it has to be less than 89 00:19:30,500 --> 00:19:36,169 1. Now, why I am saying this, that we can just 90 00:19:36,169 --> 00:19:43,169 substitute V G S for any voltage at which if that gate source voltage at which we want 91 00:19:44,230 --> 00:19:51,230 to know, the drain current for the device. We put the value of this V G S OFF or V P, 92 00:19:53,230 --> 00:20:00,230 either we substitute this just numerical values of V G S and V P can; and if we know the current, 93 00:20:05,350 --> 00:20:11,779 drain current when gate is shorted with the source, that current is known. Then we can 94 00:20:11,779 --> 00:20:18,779 find out the amount of drain current with the any value of gate source voltage. And 95 00:20:26,610 --> 00:20:33,610 then so, this is all about the constant current region or saturation region, I repeat that 96 00:20:36,169 --> 00:20:43,169 the device is operated in this region when its purpose is to amplify the signal. We will 97 00:20:44,870 --> 00:20:51,759 see when we will develop the module for the JFET, we will use and we will use the analysis 98 00:20:51,759 --> 00:20:58,120 and derive an expression for the voltage gain. 99 00:20:58,120 --> 00:21:05,120 Now, the CUT-OFF region, CUT-OFF region is this region where the drain current is 0. 100 00:21:23,330 --> 00:21:30,330 So, for n-F E T; n-JFET, V G S is less than V P; that means, more negative, V G S is less 101 00:21:41,879 --> 00:21:48,879 than V P means, is more negative than V P and in this case the drain current is 0, in 102 00:22:00,720 --> 00:22:07,720 this region drain current is 0 and the device is OFF this region. In This region, this is; 103 00:22:23,929 --> 00:22:30,929 in this particular case minus 4 volts and V P was also 4 volts, this with voltages also 104 00:22:31,330 --> 00:22:38,330 4 volts, V G S OFF is equal to V P this is what a we have said ever. And we say that 105 00:22:44,999 --> 00:22:51,999 for the CUT-OFF region V G S is to be lesser than V P; that means, more negative than V 106 00:22:56,820 --> 00:23:03,820 P, a magnitude of V P has to be lesser than this so, that will put the device into OFF. 107 00:23:07,480 --> 00:23:14,480 So, this is about the working and the I V characteristics of a junction field effect 108 00:23:18,749 --> 00:23:25,749 Transistor to make you familiar more about the device. Let us take one or two examples 109 00:23:27,629 --> 00:23:33,669 numerically problems on the device and they will clarify some of the doubts which you 110 00:23:33,669 --> 00:23:35,210 might we having. 111 00:23:35,210 --> 00:23:42,210 So, example 1, this is for a n junction field effect transistor, the parameters of the device 112 00:23:52,159 --> 00:23:59,159 are that I D S S. When the gate is shorted with the source that the maximum current in 113 00:24:03,080 --> 00:24:10,080 the n junction field effect transistor, this is 8 mill ampere and V P is minus 4 volts. 114 00:24:23,159 --> 00:24:30,159 Then find out the drain current, number one when V G S is 0, (b) when V G S is minus 2 volts and (c) 115 00:24:50,369 --> 00:24:57,369 when V G S is minus 4 volts, under these 3 values find out the value of drain current. 116 00:25:00,700 --> 00:25:07,700 This we can do simply, with the help of that expression for the drain current interms of 117 00:25:13,570 --> 00:25:20,570 the gate source voltage. So, I D is equal to I D S S, 1 minus, V G S by V P, square. 118 00:25:29,110 --> 00:25:36,110 Now, (a) V G S is 0 in that case I D comes out to be equal to I D S S when V G S is 0 119 00:25:44,559 --> 00:25:51,559 this is a definition of the current I D S S and this is given as 8 mill ampere. 120 00:25:52,879 --> 00:25:59,879 So, this is 8 millie ampere. Then for I D is 8 millie amperes that is the value of IDSS, I have substitute it in that expression 121 00:26:16,369 --> 00:26:23,369 and 1 minus; I said that either use both with proper sign for just substitute magnitudes 122 00:26:26,119 --> 00:26:33,119 this is one in the same thing. So, if I take with proper sign just this is minus 2 and 123 00:26:34,049 --> 00:26:41,049 this is minus 4, this whole square. So, you see here this is the same if I have just substituted 124 00:26:45,929 --> 00:26:52,929 the magnitudes. So, there is no confusion about sign, it is better just we talk in terms 125 00:26:53,990 --> 00:27:00,990 of magnitude, we have substituted the magnitude of VGS and V P also. 126 00:27:01,039 --> 00:27:08,039 And so, they; this results in a current of 8 millie ampere into 1 by 4 which is 2 millie 127 00:27:12,580 --> 00:27:19,580 ampere. This is what, is expected when we increase the gate source voltage to minus 128 00:27:23,700 --> 00:27:30,580 2 volts, the current will decrease from its value I D S S, I D S S was 8 millie ampere 129 00:27:30,580 --> 00:27:37,580 and this is a 2 millie ampere. And then C, when V G S is equal to minus 4 volts, then 130 00:27:45,119 --> 00:27:52,119 I D will be 8 millie amperes by 1 minus; I am just substituting the magnitude 4 and V 131 00:27:56,259 --> 00:28:03,259 P is also 4, this is square and that makes I D equal to 0, that is expected also, because 132 00:28:12,239 --> 00:28:19,239 of the plots if you remember. Here I D is 0 when V G S of which is minus 4 volts and 133 00:28:26,429 --> 00:28:33,429 V P is also 4 volts, then our substituted any way, the given values then id is 0. So, 134 00:28:34,399 --> 00:28:40,730 at three different gate source voltages, we have calculated the drain current with the 135 00:28:40,730 --> 00:28:43,499 help of this expression. 136 00:28:43,499 --> 00:28:50,499 This is an example 2, again n-JFET which has I D S S as 10 millie amperes and V P, the 137 00:29:05,499 --> 00:29:12,499 pinch off voltage as minus 5 volts, then we have to find out VDS the minimum value of 138 00:29:16,299 --> 00:29:23,299 drain source voltage for pinch off when VGS is equal to minus 1 volt. I repeat n type junction field effect transistor 139 00:29:39,769 --> 00:29:46,769 which has the maximum current then IDSS as 10 millie ampere, the pinch off voltage of 140 00:29:46,989 --> 00:29:53,989 minus 5 volts. And we have to find out the minimum value of a V D S for pinch off at 141 00:29:58,730 --> 00:30:05,730 minus V P. So, now the solution you remember, we have written V D S minimum is equal to 142 00:30:15,649 --> 00:30:22,649 V G S minus V P. And so, this can be easily found out, this is given as minus 1 volt and 143 00:30:28,080 --> 00:30:35,080 this is given as minus 5 volts so, this is 4 volts the. In this, under these conditions, 144 00:30:38,669 --> 00:30:45,669 a drain source voltage of 4 volts will pinch off the channel and if we have to find out 145 00:30:50,320 --> 00:30:55,509 the drain current here at the pinch off. 146 00:30:55,509 --> 00:31:02,509 Then, the drain current again we can find out I D S S, 1 minus, V G S by V P, square. 147 00:31:07,100 --> 00:31:14,100 And this we can find out 10 millie amperes, 1 minus, 1 by 5, square when we solve it, 148 00:31:17,299 --> 00:31:24,299 it comes out to be 6.4 millie ampere, this way the problems can be handled. So, this 149 00:31:26,389 --> 00:31:33,090 is, about junction field effect transistor, we will return to junction field transistor 150 00:31:33,090 --> 00:31:40,090 again and when we talk of biasing and other things, let us talk of other devices. 151 00:31:43,109 --> 00:31:50,109 The next device in this module, which is very significant most important device today in 152 00:31:53,690 --> 00:32:00,690 Electronics is M O S F E T. In the beginning I have said that M O S F E T is tense for 153 00:32:10,369 --> 00:32:17,369 Metal Oxide semi Conductor field effect transistor, this is M O S F E T. Sometimes in the interview, 154 00:32:30,909 --> 00:32:37,909 it is asked elaborate for what M O S is tense in M O S F E T. So, you should know Metal 155 00:32:39,549 --> 00:32:46,549 Oxide semi Conductor, as the name suggest. Here, the gate, this very important and a 156 00:32:49,869 --> 00:32:56,869 basic difference and that gives all the differences, the basic difference between a junction field 157 00:32:57,019 --> 00:33:04,019 effect transistor and a M O S F E T is that here, gate is separated by a insulating layer, 158 00:33:06,080 --> 00:33:10,769 Oxide layer. If we are talking of Silicon, then a thin 159 00:33:10,769 --> 00:33:17,769 layer by thin I mean, for example, 50 Armstrong thin, then this is oxide layer separates the 160 00:33:21,450 --> 00:33:28,450 semi conductor with the gate electrodes. So, gate is separated from the semiconductor by an insulating layer. And as I said that 161 00:33:53,080 --> 00:33:59,940 insulating layer, when we are talking of a; normally, the Silicon is used. So, Silicon 162 00:33:59,940 --> 00:34:06,940 Oxide or Silicon dioxide is the layer which is used and that is one reason that why this 163 00:34:10,720 --> 00:34:17,720 M O S F E T is also sometimes call insulating; insulated gate M O S F E T, insulated gate 164 00:34:34,440 --> 00:34:41,440 F E T. We will see, that there are two types of construction and; that means, how through 165 00:34:52,490 --> 00:34:59,490 the field induced from the gate through the in this a insulating layer how the conductance 166 00:35:04,500 --> 00:35:11,500 of the channel is affected the whole working depends on that. And there are two kinds of 167 00:35:13,040 --> 00:35:20,040 a M O S F E T, one is Depletion M O S F E T. 168 00:35:24,400 --> 00:35:31,400 Depletion M O S F E T S, often written as D M O S F E T, D for depletion, depletion 169 00:35:35,110 --> 00:35:42,110 M O S F E T and second one Enhancement M O S F E T or simply E M O S F E T. There is 170 00:35:59,520 --> 00:36:06,520 a insulating layer which separates the gate from the semiconductor, I will give you the 171 00:36:06,910 --> 00:36:13,910 construction. But there are two possibilities, one is the Depletion M O S F E T that is D 172 00:36:15,160 --> 00:36:21,030 M O S F E T and other is Enhancement M O S F E T that is E M O S F E T, both are very 173 00:36:21,030 --> 00:36:28,030 widely used. And first we take the depletion MOS FET. 174 00:36:41,820 --> 00:36:48,820 Depletion M O S F E T, first the construction Fabrication; here is a small crystal of say P type Silicon, which is a substrate, 175 00:37:15,790 --> 00:37:22,790 on that we generate two heavily doped n regions, n plus, n plus. And then; let me first complete 176 00:37:35,600 --> 00:37:42,600 that drawing and then we will talk, this is the insulating layer S i O 2 layer, it is 177 00:37:53,100 --> 00:38:00,100 very thin say 15; 50 to 100 thick, very thin layer. How it is achieved that this silicon 178 00:38:07,340 --> 00:38:14,340 on which we are making the device, if fresh pure Oxygen, this is kept at a temperature 179 00:38:15,600 --> 00:38:22,600 and that flows it is all computer control. So, how thin Oxygen Oxide layer we need that 180 00:38:23,680 --> 00:38:28,720 this control and hence the oxide layer is obtained. 181 00:38:28,720 --> 00:38:35,720 Then two windows are obtain by edging; that means, from the two regions here and here, 182 00:38:38,350 --> 00:38:44,690 the oxide layer is edged and metal electrode circuit and one electrode. These electrodes 183 00:38:44,690 --> 00:38:51,690 normally are of Aluminum and one electrode is put here and before all this is done a 184 00:38:57,190 --> 00:39:04,190 channel is implanted. Here this is n channel, which is implanted and these are the three 185 00:39:13,430 --> 00:39:20,430 electrodes. This is source, this is gate and this is drain, these are let we do like this, 186 00:39:35,540 --> 00:39:42,540 these are metal electrodes, this is a depletion M O S F E T. I repeat all what I have done 187 00:39:53,250 --> 00:40:00,250 that, P type silicon is taken as substrate over which two regions are created by heavily 188 00:40:05,130 --> 00:40:12,130 n type dope; doping and in between this n channel is implanted. 189 00:40:18,670 --> 00:40:25,670 These are sophisticated techniques of creating n or p type region said a specified places 190 00:40:26,800 --> 00:40:32,760 very precisely, because this dimension I will draw a still bigger to make my points clear. 191 00:40:32,760 --> 00:40:38,070 But actually, these dimensions is a fraction of a millie meter, the total dimension is 192 00:40:38,070 --> 00:40:45,070 a very small 100 of a milli meter or a still a smaller. So, the channel is implanted and 193 00:40:46,480 --> 00:40:53,480 Oxide layer is put so that, the gate and the semi conductor they are separated by this 194 00:40:56,590 --> 00:41:03,590 Oxide layer. This, I will to put my points clear I will make a bigger figure, but let 195 00:41:10,280 --> 00:41:17,280 me point out one big difference with JFET. In JFET in the n type, the gate voltage was 196 00:41:21,190 --> 00:41:28,190 negative necessarily through reverse bias the junction. Here below the gate, there is 197 00:41:29,190 --> 00:41:36,190 no P n junction. Therefore, the gate source voltage V G S can be it is very significant 198 00:41:41,160 --> 00:41:48,160 point; can be 0 or positive voltage or negative voltage, all possibility. We can give gate 199 00:42:01,620 --> 00:42:08,620 positive potential with respect to source or we can keep it at a negative potential. 200 00:42:08,820 --> 00:42:15,820 So, positive, negative or 0 potential, all are possible in this device, it is a big difference. 201 00:42:18,660 --> 00:42:25,660 Why we do not operate a field effect; a junction field effect transistor with A? 202 00:42:29,770 --> 00:42:36,770 This was a F E T, this is of course P type, but it is all right. So, here now to forward 203 00:42:39,960 --> 00:42:46,960 bias it, we will have to give a positive potential, positive potential will forward bias the P 204 00:42:49,390 --> 00:42:56,390 n junction lot of current will flow so, that will not be operated. That is for n type JFET 205 00:43:00,030 --> 00:43:04,620 a figure must be ya. 206 00:43:04,620 --> 00:43:11,620 This is gate, this was P type material, this is n and we have said that gate in the n type 207 00:43:15,450 --> 00:43:22,450 JFET is always operated with the negative voltage. And we draw the characteristics where 208 00:43:24,900 --> 00:43:31,260 the gate source voltage is negative, more negative, more negative and so on. Because 209 00:43:31,260 --> 00:43:37,000 making it positive will make the junction forward bias, lot of currents will flow and 210 00:43:37,000 --> 00:43:44,000 different phenomena will occur and will create problems. In this case, in the M O S F E T, 211 00:43:47,880 --> 00:43:54,880 there is no direct; there is no P n junction. Hence it permits the voltage at the gate with 212 00:43:55,720 --> 00:44:02,720 respect to source either positive or negative or 0. 213 00:44:03,570 --> 00:44:10,570 Now, let me redraw this figure and show you, that how the charges induced through this 214 00:44:15,090 --> 00:44:22,090 a dielectric layer will change the conductance of the channel and hence will control the 215 00:44:24,770 --> 00:44:31,770 current. I will make a bigger figure and. 216 00:45:10,670 --> 00:45:17,670 This is oxide and here is the gate electrode and this is the semiconductor, which is P Silicon and here is the body b, 217 00:45:32,300 --> 00:45:39,300 which is shorted to internally shorted to the source. And we apply a positive voltage, 218 00:45:51,830 --> 00:45:58,830 here between drain, this is drain, this is source and this is gate. And we apply to the 219 00:46:01,170 --> 00:46:08,170 gate for example, we start with a negative voltage this is V D D and this is V G S. Now, 220 00:46:12,210 --> 00:46:19,210 let us see, how the channel is n type, the channel is n type, this is n region, this 221 00:46:23,970 --> 00:46:30,240 is n region heavily doped. And heavily doped is represented by plus sign is still more 222 00:46:30,240 --> 00:46:37,240 heavily and 2 plus signs, this is heavier then this doped. So, how the field will induce 223 00:46:42,650 --> 00:46:49,650 and the depletion region it will create, for that let me just draw this portion much larger. 224 00:46:55,460 --> 00:47:02,460 This is the this is that S i O 2 layer and 225 00:47:19,420 --> 00:47:21,750 these are the Electrodes. 226 00:47:21,750 --> 00:47:28,750 This is a heavily doped n type, this is source, this is drain and this is gate. Now, when 227 00:47:36,080 --> 00:47:43,080 we apply a negative voltage to the gate, then these look at these charges, this is negative 228 00:47:51,960 --> 00:47:58,960 charge and this is n type channel, n channel. And so, here are the electrons, this is the 229 00:48:02,180 --> 00:48:09,180 S i O 2 layer, a dielectric this field at the gate very important, the field at the 230 00:48:11,890 --> 00:48:18,890 gate will polarize. This S i O 2 will induce positive and negative chargers, they are bound 231 00:48:28,440 --> 00:48:35,440 charges in the insulating. It is S i O 2 is insulator, they are a low free chargers. So, 232 00:48:35,450 --> 00:48:40,630 that field at the gate will induced the opposite chargers. 233 00:48:40,630 --> 00:48:47,630 This is you must have a studied, how the capacitance of a capacitor is increased by introducing 234 00:48:49,900 --> 00:48:56,900 a dielectric. Dielectric get popularized and that, they are in the case of a capcatior 235 00:48:59,600 --> 00:49:06,600 some charges of the plate so the capacitance increases. In this case, this will induced 236 00:49:07,880 --> 00:49:14,880 some positive charges, here this negative just at the surface, just above the channel 237 00:49:19,790 --> 00:49:26,790 this positive charges will be induced. And these induced for the positive charges will 238 00:49:26,930 --> 00:49:33,930 recombine with some of the electrons. So, therefore, in this region, this is the channel, 239 00:49:40,950 --> 00:49:47,950 now, this is the depletion region which will occur. And this is of course, the Oxide and 240 00:49:50,330 --> 00:49:57,330 this is the gate negatively charged, I think I have made clear what will happen. 241 00:50:00,700 --> 00:50:07,700 Look here, that this is the geometry we are talking. The gate I am taking negative with 242 00:50:10,460 --> 00:50:17,460 respect to source and this negative field at the gate through the dielectric will induced 243 00:50:20,230 --> 00:50:27,230 some positive charges in the channel region. Channel was n type; that means, negative charges, 244 00:50:28,620 --> 00:50:35,070 the electrons were there. Now, this induced positive charges, will recombine with some 245 00:50:35,070 --> 00:50:42,070 of the electrons and a depletion region will be formed. And hence this depletion region, 246 00:50:44,040 --> 00:50:50,000 depletion region is always a region divide of mobile charges; that means, high resistivity 247 00:50:50,000 --> 00:50:57,000 region. So, by this depletion region, depletion region will increase the resistance, will 248 00:50:58,600 --> 00:51:05,600 decrease the conductance of the channel. If now, we keep this constant, there will 249 00:51:06,930 --> 00:51:13,930 be a current in the in that; these will be the characteristics here, this is V D S volts, 250 00:51:23,890 --> 00:51:28,120 this is I D when there is; if there is this. 251 00:51:28,120 --> 00:51:35,120 Voltage gate source, voltage is kept to 0. Then this is the channel when we change this 252 00:51:35,180 --> 00:51:42,180 voltage V D D, that is, V D S we change between source and drain, the current will flow because 253 00:51:43,720 --> 00:51:50,720 of these electrons, this is n channel, current will flow. So, this current will be this and now, this is V G S equal to 0. Now, we 254 00:52:08,960 --> 00:52:15,960 have given a negative voltage that reduces the conductance so, for the same voltage same 255 00:52:16,030 --> 00:52:23,030 drain source voltage the current will fall and this way, we will get these characteristics. 256 00:52:40,020 --> 00:52:47,020 This is at V G S of minus 1 volt, minus 2 volt, minus 3 volt and so on. And a voltage 257 00:52:51,390 --> 00:52:58,280 may come where this channel may be completely the depletion region has completely taken 258 00:52:58,280 --> 00:53:05,280 over and there is no continuity there is no conductance between drain and source. So, 259 00:53:06,810 --> 00:53:13,810 here device is OFF, this is the depletion mode for the device. Now, if I give a positive voltage, if you have followed this, 260 00:53:26,920 --> 00:53:33,920 that negative voltage induces a depletion region. Because positive charges will be induced 261 00:53:33,990 --> 00:53:40,990 in the channel and that will take some of the negative charges of the channel, mobile 262 00:53:42,070 --> 00:53:45,960 charges of the channel and hence the conductance will fall. 263 00:53:45,960 --> 00:53:52,960 If we give a positive voltage to the gate, which is possible and that will enhance the 264 00:53:53,590 --> 00:54:00,300 conductivity. That will induce more negative charges in the channel and hence the conductance 265 00:54:00,300 --> 00:54:07,300 will increase. So, the currents will change and here this is plus 1 volt V G S, plus 1 266 00:54:13,960 --> 00:54:20,960 volt, Plus 2 volts and so on. And this is known as depletion mode is now working in 267 00:54:22,430 --> 00:54:26,370 a enhancement mode. Remember, enhancement mode is different than Enhance E type M O 268 00:54:26,370 --> 00:54:33,370 S F E T. A Depletion M O S F E T can be operated in the 2 modes, depletion mode or enhancement mode simply by changing 269 00:54:47,590 --> 00:54:53,860 the nature of polarity at the gate. If gate is negative with respect to source 270 00:54:53,860 --> 00:55:00,590 and keep on increasing that negativity current will fall, because depletion region will penetrate 271 00:55:00,590 --> 00:55:07,590 more and more in that channel region. And by giving a positive voltage, more charges 272 00:55:08,700 --> 00:55:14,570 negative charges will be induced by the field in the channel region and the conductance 273 00:55:14,570 --> 00:55:21,570 will increase. So, for the same voltage more and more current will appear here. This is 274 00:55:21,580 --> 00:55:28,580 higher than this and this is higher than this. So, this is these are the characteristics 275 00:55:28,960 --> 00:55:35,960 of a Depletion M O S F E T, drain Characteristics of D M O S F E T. We will continue our discussion 276 00:55:50,500 --> 00:55:57,500 on MOS FETS.