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00:01:06,000 --> 00:01:09,000
Here, we will talk about the commutation process
or
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00:01:09,360 --> 00:01:16,180
the commutation over lap and due to commutation
over lap, what happens to the output voltage
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00:01:16,180 --> 00:01:21,100
repel. Here also, instead of going to the
three phase fully controlled converter, we
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will take the semi converter or the three
phase mid point configuration and we can explain
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00:01:28,490 --> 00:01:31,330
the same thing for the three phase fully controlled
converter also.
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So, let us draw the schematic of the three
phase fully controlled converter. This is
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00:01:40,670 --> 00:01:47,670
my e1 phase, this is my e2 phase, this my
e3 phase, this is my neutral side phase, mains
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00:01:57,860 --> 00:02:03,530
node. So, the finite inductance, it can be
the line leakage inductance, transformer leakage
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00:02:03,530 --> 00:02:10,009
inductance or we have deliberately introduced
to avoid the short circuit between the phases
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during the commutation over lap. So, this
is my thyristor, this is connected like this.
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I will mark these points for the analysis
as A1, this point as A2, this point as A3
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and this is my point K. So, between K and
N, we will be connecting the load. Here, we
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will represent it as a dc motor.
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Now, how the commutation over lap? Let us
draw the waveform. Let us draw for easy to
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understand, easy to explain. Let us assume
alpha is equal to, firing angle alpha is equal
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to 0. So, let us draw the waveform. This is
the half side of my e1, half side of my e2,
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this is my e3; e1 e2 e3, negative portion
we have not drawn.
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Now, let us see, this is alpha is equal to
0 starts from here. At this point, the T 3
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that is 3, T 1, T 2 and T 3, at this point,
till this point, T 3 was conducting, now T
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1 will be turned on. So, what will happen
and assuming load is highly inductive, we
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will assume the output current, the load current
this one that we say as Id is clearly dc.
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So, we are not worried about the repel part.
So, what will happen to the current? How the
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commutation, how the current transfers from
one side to other? Let us see.
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At this point that is here, I1 will conduct,
slowly conduct and I3 will be I3 is the current
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flowing through T3 will be slowly coming to
0. So, I3 will rise like this no sorry I1
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00:05:01,530 --> 00:05:08,530
will rise like this and come to Id stay there
and till now, the load current was supported
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by sore contrast flowing through T3, so we
will call this as I3. So, I3 the net value,
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this the this value is Id, the amplitude of
this one is but this is the current, this
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00:05:29,030 --> 00:05:36,030
portion of the current, this is the current,
load current; this portion of this portion
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00:05:37,250 --> 00:05:44,250
of the current, the load current flowing through
I3 T 3 and here, it is flowing through T 1.
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00:05:47,840 --> 00:05:54,780
Now, load is highly inductive so that as the
current builds up along I1 I3 will decrease
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00:05:54,780 --> 00:06:01,780
such that we can assume I1 plus I2 is equal
to Id because load is highly inductive. During
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00:06:06,590 --> 00:06:13,590
this portion, we can assume I3 plus I1 is
equal to Id and finally, the current through
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I3 decreases and fully after sometime, it
will fully, the full load current will be
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00:06:25,070 --> 00:06:29,190
taken over by I1.
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00:06:29,190 --> 00:06:36,190
Now, again here, at this point, T 2 will be
turned on. So, when T 2 will be turned on,
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00:06:39,900 --> 00:06:46,900
we can use different color so that it will
be here T 2 will be turned on. At this point,
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00:06:51,880 --> 00:06:57,260
till this point, I1 is equal to Id that is
the current through T1 will be Id and from
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00:06:57,260 --> 00:07:03,670
here I2 will slowly come into picture and
thyristor T1 will be switched off by T2. So,
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00:07:03,670 --> 00:07:10,670
current will slowly decrease like this and
I2 will slowly increase like this. So, this
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00:07:14,870 --> 00:07:21,870
portion is the I1 portion. Here also, during
this period, we can assume I1 plus I2 is equal
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to Id. So, what happens?
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00:07:34,110 --> 00:07:39,780
Whenever there is a commutation, whenever
we have initiated a turn on of the thyristor,
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00:07:39,780 --> 00:07:46,780
momentarily both the thyristors will be turned
out that is this portion during this period;
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00:07:48,110 --> 00:07:55,110
this period T 1 and T 3, this period T 1 and
T 2 and we can also from the voltage waveform
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00:08:01,030 --> 00:08:06,760
here, the instantaneous values of the voltages
are not the same in this portion and this
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00:08:06,760 --> 00:08:13,470
portion during the commutation overlap. So,
there is a difference in the voltage. This
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00:08:13,470 --> 00:08:20,389
voltage has to be dropped across some element.
For that purpose, we have put this inductance
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00:08:20,389 --> 00:08:26,350
or many times the transformer leakage inductance
may be sufficient.
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00:08:26,350 --> 00:08:33,350
Now, let us find out during this period, what
will happen to the output dc voltage. The
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00:08:36,399 --> 00:08:43,399
interval we will take it for T 1, the commutation
from T 1 to T 2, we will take for the analysis.
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00:08:46,180 --> 00:08:53,040
So, this period we will take as this is the
period T 1, this period we will take it as
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00:08:53,040 --> 00:09:00,040
T 2. So, during the current transfer from
T 1 to T 2, from this figure; what is V A1N?
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00:09:04,439 --> 00:09:11,439
V A1N is equal to e1 plus let us for we will
say the leakage inductance, this one we will
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00:09:19,809 --> 00:09:26,809
make it as this is L 1, this is L2, L3. But
now practical case, L1 is equal to L2 is equal
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00:09:28,170 --> 00:09:35,170
to L3; just for easy analysis, we will make
it as L1 into di 1 by dt and during the period
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00:09:40,459 --> 00:09:47,459
that is period from T 1 to T 2 that is commutation
from commutation from T 1 to T 2.
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Now, during this period, during the commutation
overlap; what is V A2N? V A2N is equal to
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e2. See here, e2 minus L2 di by dt. See, here
plus, here minus because in one case, e1 current
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00:10:34,869 --> 00:10:40,730
is decreasing. So, di by dt is negative, so
polarity will be trying to aid the voltage
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00:10:40,730 --> 00:10:47,730
here at the e1 side and in the other case,
current is increasing, so it will be trying
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to oppose L di2 by dt. So, V A2N will be e2
minus L2 di2 by dt.
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00:10:55,490 --> 00:10:59,869
Now, for analysis, the assumptions, we can
use some assumptions. One assumption what
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we made; we cannot take the all the practical,
all the non idealities into concentration
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if you are try to solve the equation, it will
be complicated. So, some engineering assumptions
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so that the final conclusion will not be not
very far away from the reality. So, we will
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assume the current rise and fall is approximately
linear. Assume we are neglecting the load
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repel current, we will assume current is highly
inductive that means the load inductance is
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much much higher than the leakage inductance
so that the change in the leakage inductance
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current we can assume approximately linear
so that during this period, the magnitude
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of di1 by dt is equal to di2 by dt that is
the magnitude and also I1 plus I2 is equal
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to Id.
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00:12:01,209 --> 00:12:08,209
Now, if you see here, the voltage drop across
the thyristors or we can assume the voltage
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drop across the thyristors are negligible
and we can also assume L1 is equal to L2.
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So, what it shows? So, you see, if we assume
that the voltage drop because both are conducting
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T1 and T2 are conducting, the voltage drop
across T1 and T 2 are negligible; then e1
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and e2 will be A1 and A2 will be shortened
to K that is this point. So, V A1 during this
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portion, V A1N is equal to V A2N that is from
equation 1 and this is 2, this is 3.
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00:13:12,869 --> 00:13:19,869
So, V A1 is equal to V A2N, so from 1 and
2, e1 plus L1 di1 by dt is equal to e2 minus
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L2 di2 by dt. So, then bringing back e1 e2
one side and di1 by dt terms on the other
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side, we can say we can write L1 di1 by dt
plus L2 di2 by dt is equal to e2 minus e1
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and also we said L2 is equal to L1 is equal
to L, so we can say or L2, we can say 2 into
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L2 di2 by dt is equal to e2 minus e1. What
it shows? During commutation over lap when
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the both device are conducting, during commutation
over lap when both device are conducting,
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00:14:38,879 --> 00:14:45,420
the difference in voltage; here e2 minus 1
will be dropped across the leakage inductor.
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00:14:45,420 --> 00:14:51,179
So, your leakage inductance is very much for
these type of converters.
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00:14:51,179 --> 00:14:58,179
Otherwise, let us let us assume that L1 and
L2 are not there and both thyristors are conducting;
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this e2 minus e1 difference will heavy circulating
current will flow, it can damage device or
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the transformer. So, this leakage inductance
is required. Now, we have introduced the leakage
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00:15:11,220 --> 00:15:18,220
inductance for one purpose. Now, this part,
we have not, this commutation overlap, we
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have not taken into consideration while deriving
the E0 alpha that is output dc voltage with
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respect to the firing angle.
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00:15:26,050 --> 00:15:32,589
Now, what will happen to the terminal voltage
or the output voltage due to these firing
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00:15:32,589 --> 00:15:39,589
angle or during this commutation overlap,
what is the nature of the voltage repel across
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the load; we will we will derive that one
now. Let us go to the next page now.
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Clarity, quickly I will write this portion;
e1 e2 e3, this is N, this is the leakage inductance
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part, then T 1, T 2 and T 3. This is K, A1
A2 A3 and our load. Now, during the commutation
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overlap, during the commutation overlap, during
the commutation overlap, V A1N is equal to
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e1 plus L1 di1 by dt V A2N is equal to e1
minus L2 di2 by dt. Also, we said we are assuming
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the drop. These two thyristors are in the
on condition, so the voltage drop across device
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is 0. So, V A1N is equal to V A2N will be
equal to V KN. So, this implies V A1N is equal
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to V A2N is equal to V KN.
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00:18:07,530 --> 00:18:14,530
So, what will be V A1N plus V A2N? V A1N plus
V A2N? If you see this equation, the rater
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change L1 d i1 by dt L2 di2 where the same
but this one is positive and one is negative;
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so, this will cancel. So, V A1N plus V A2N
will be equal to e1 plus e2 is equal to 2V
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KN. What is KN? KN is instantaneous repel
voltage across the load. So, V KN is equal
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to e1 plus e2 by 2.
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So, during the commutation overlap, previously
we assumed that the moment commutation started,
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the moment T 2 is turned on, the thyristor
T 1 will immediately go, there after the voltage
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repel is the part of e2. But during the commutation
overlap during that small period; that depends
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on inductance we have produced, we have introduced
and also depend on the maximum load current
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that period. This will be equal to e1 plus
e2 by 2 that means during that period, the
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output repel is not T 2 but is e1 plus e2
by 2. So, what will happen if you plot the
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waveform?
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So, let us again draw the output repel, output
waveform, only the positive side. So, this
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is our positive side of e1, after 120 degree
we have e2, then we have the e3; e3 e1 e2.
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So, during this commutation, let us say commutation
overlap is from this to this one; during this
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period, it is e1 plus e2 by 2. So, if you
see here, e1 plus if the commutation is instantaneous,
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it would not started from here that is assuming,
let us say the commutation is instantaneous,
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instantaneous means here T3 will be off and
T1 will be on, immediately from this point,
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the commutation starts. So, let us highlight
with a different color. So, it will be more
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clear.
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00:20:52,800 --> 00:20:59,800
So, instantaneous means it will start from
here. But now, due to the commutation overlap,
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it will never start with the same point at
this point. What will happen? During this
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point, it will be e1 plus e2 by 2. So, if
you see, the net repel, it will be something
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like this; that means some portion some area
is lost in the output voltage control. So,
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00:21:18,200 --> 00:21:25,200
it will go like this. This is true in every
cases. So, this much is lost. That means now,
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this much area is lost that means there is
a reduction in the output voltage due to the
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commutation overlap. How to find out the reduction
in the commutation overlap? This we can find
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out from the previous figure during which
the current was, this figure, see assuming
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the current I2 is slowly increasing and I1
is decreasing.
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So, during this portion when the I2 increases
during this portion, the voltage drop, the
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net area of the voltage on the volt second
if we take the voltage along the inductance,
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it will be equal to, we will go to the next
page, when the current is slowly rising in
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the limp in the limp where the thyristor T
2 is connected, the volt second let us say
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00:22:27,430 --> 00:22:34,430
the area dA is equal to L into di2 by dt into
d omega t or exactly d omega t; this much,
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00:22:43,060 --> 00:22:49,280
so this will be equal to this d omega t, so
omega is will not be, omega is constant, so
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00:22:49,280 --> 00:22:56,280
we will bring it outside. It will be di2 by
dt into dt but if the commutation was instantaneous,
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immediately the limp 2 will have the load
current dc current and there is no drop across
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00:23:08,720 --> 00:23:09,980
the inductance L2.
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00:23:09,980 --> 00:23:15,490
Now, because during the commutation overlap,
there is a drop across the inductance that
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00:23:15,490 --> 00:23:22,490
drop is equal to L into di2 by dt and what
is the volt second? That area L i2 by di2
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00:23:24,230 --> 00:23:30,230
that is the voltage and extacy d omega t.
So, that will be equal to dA is equal to L
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00:23:30,230 --> 00:23:37,230
omega di2 by dt into dt. This is equal to
L omega di2. Now, this is an instantaneous
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00:23:43,830 --> 00:23:48,190
that a small area loss, that is the small
area loss during the commutation process.
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00:23:48,190 --> 00:23:55,190
So, total area loss during the full commutation
process is when i2 start from 0 to Id so the
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00:23:57,010 --> 00:24:04,010
area A lost is equal to integral I2 is equal
to 0 to Id L omega into di2.
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00:24:13,590 --> 00:24:20,590
So, as the current increases from 0 to Id,
this much area volt second is loss from the
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00:24:30,830 --> 00:24:37,830
output, output from the output dc commutation.
This will be equal to L omega into Id. This
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00:24:39,580 --> 00:24:46,580
happens during this much area lossed in the
integration. Previously, we are integrating
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00:24:47,070 --> 00:24:54,070
the voltage; now but from that total area
this much will, area will be lost during every
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00:24:54,840 --> 00:24:55,550
commutation.
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00:24:55,550 --> 00:25:02,550
Now, for a general m phase; what is the period
for half bridge? 2 phi by m. So, the net voltage,
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so the average voltage drop lossed, this has
to be subtracted from the output voltage.
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00:25:14,400 --> 00:25:21,400
So, average average loss in output dc voltage
due to due to commutation overlap is equal
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00:25:47,590 --> 00:25:54,590
to L omega Id by 2 pi by m. So, this much
has to be subtracted from our previous computed
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00:26:04,950 --> 00:26:11,950
ideal conditions, computed output dc voltage
that is E0 alpha minus m into L omega Id by
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00:26:18,800 --> 00:26:22,710
2 pi. This much is lost.
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00:26:22,710 --> 00:26:29,710
This L omega, for a converter, this is a constant;
L omega sorry L omega into the whole thing,
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00:26:32,570 --> 00:26:39,570
L omega, let us clear it. So, I will rewrite
it again; L omega divide by 2 phi. So, this
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00:26:55,240 --> 00:27:02,240
portion, the whole L omega divided by 2 pi
m is a constant for a particular converter
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00:27:05,690 --> 00:27:12,690
and then if you see here, the dropping voltage
that is the V0 the dropping voltage is equal
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00:27:17,050 --> 00:27:24,050
to some constant K into Id. Id is the maximum
output load current. So, this can be assumed
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00:27:26,580 --> 00:27:33,580
as a resistive drop because this constant
into Id as an internal resistance of the converter
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00:27:34,450 --> 00:27:40,030
and converter can be we can model like this;
you have the...
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00:27:40,030 --> 00:27:47,030
So, the converter will be this is variable
dc voltage, that is our E0 alpha that is why
167
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put variable here, then Id is going, then
have an internal impedance that is equal to
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00:28:03,840 --> 00:28:10,840
this value internal impedance R. R is equal
to m L omega by 2 pi. m is the number of phases.
169
00:28:15,500 --> 00:28:22,500
For three phase, it is 3 L omega by 2 pi into
R. Then you have the load here, this way.
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00:28:29,500 --> 00:28:36,500
So here, if you see, the Id verses Id is the
load current verses our E0 alpha maximum divide
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00:28:44,800 --> 00:28:51,800
by sorry E0 alpha divide by E0 alpha maximum
just the Id varies, this is a drop happens
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00:29:02,170 --> 00:29:04,170
like this.
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00:29:04,170 --> 00:29:11,170
So, as Id varies, sometimes the output voltage
can vary and depending on the Id, sometimes
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00:29:13,130 --> 00:29:17,610
it can be a 0 also. So, this we have to take
into consider, this commutation overlap due
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00:29:17,610 --> 00:29:22,650
to leakage inductance indusly we are putting
or due to the circuit inductance, there was
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00:29:22,650 --> 00:29:28,870
a drop in the voltage. For a three phase converter,
it is L omega m by 2 pi; for three phase fully
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00:29:28,870 --> 00:29:34,020
controlled, it will be again multiplied by
2, 6 times it happens. So, this voltage drop
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00:29:34,020 --> 00:29:41,020
you should take into consideration while designing
your converter with load for control application.
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00:29:41,250 --> 00:29:48,250
This is some of the some of the problem associated
with non ideality of the phase controlled
180
00:29:48,430 --> 00:29:53,380
converter.
Now, so far we said, we start from single
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phase converter, then we are going through
the we are going through the semi converter
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fully converter converter, then three phase
mid point configuration, then we have come
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00:30:08,490 --> 00:30:14,400
to the three phase fully controlled converter,
we have derived the output dc voltage with
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00:30:14,400 --> 00:30:19,080
respective to firing angle for semi converter
as well as a fully controlled converter, then
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we have also did some more the typical output
ripple for the and we have noted the ripple
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frequency for three phase as well as fully
controlled converter.
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Then we found commutation is not instantaneous,
we introduced the commutation over lap and
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due to the commutation over lap, we found
that there is an output voltage dc reduction.
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Even though with the same firing angle is
used as the Id is increased, the output voltage
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is slowly drooped, there is a droop. That
droop depends on the Id and the internal impedance.
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Internal inductance we are represent as 3
L omega by 2 pi.
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Now, we are using the phase controlled converter
for output voltage control. So, we are using
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the phase controlled converter with firing
angle for output control. So, if you see,
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the output power will be equal to, output
power power, assuming load is highly inductive,
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we will take the dc value of the current;
output power from the converter output will
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be equal to E0 alpha that is the dc with output
dc with respectly firing angle and Id.
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00:31:31,730 --> 00:31:38,730
Now, what will happen to the input power?
Input power, input is a sinusoidal voltage
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and what type of input current drawn from
the converter? Let us see for a single phase
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fully controlled converter.
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Let us take the single phase fully controlled
converter, controlled converter. Now, let
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00:32:15,170 --> 00:32:22,170
us draw the half circuit schematic thyristor.
These are single phase, comes here. Let us
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see, this is our i1, i1 we represent as input
and we will assume the load current is nearly
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sinusoidal, triple part we will neglect for
analysis. This is our Id, load current, this
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00:33:04,660 --> 00:33:11,660
our V phase waveform. So, let us draw for
the V phase waveform; what will happen? Output
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00:33:13,960 --> 00:33:20,960
power is equal to P0 is equal to E0 alpha
into Id. The E0 alpha we have derived for
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00:33:23,990 --> 00:33:25,680
a single phase fully controlled converter.
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Now, let us see what will happen to the input
power that is AC side. If you see here, we
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will draw the mains waveform first. This is
our input mains waveform. Now, let us mark
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the thyristors; this is T 1, this is T 2,
this is T 3 and this is T 4. Now, let us say
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when the firing angle is equal to alpha, when
firing angle is equal to alpha from here,
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00:34:12,179 --> 00:34:19,179
this is alpha; from here onwards, we are turning
on S1 and T 1 and T 4 and for the negative
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00:34:26,080 --> 00:34:31,210
side, firing angle alpha from here to here,
we will be turning at this point, we will
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00:34:31,210 --> 00:34:38,210
be turning on according to diagram T 1 and
T 4 together and at this point, we will be
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00:34:39,350 --> 00:34:42,190
turning on T 2 and T 3.
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00:34:42,190 --> 00:34:48,040
Now, when the T 1 and T 4 is turned on, the
load current Id will pass through T 1, Id
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00:34:48,040 --> 00:34:55,040
will pass through T 1 and Id will pass through
T 1 that is through this way, come to the
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00:35:01,560 --> 00:35:08,560
load and through T 4 and it will transfer.
So, what will happen? Till the T 2, T 3 is
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00:35:14,970 --> 00:35:21,970
fired, the load current Id is going through
T 1 and T 3, this is the load current portion,
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00:35:24,080 --> 00:35:31,080
this is Id, this height is Id. The moment
at this point, when T 2 and T 3 are turned
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00:35:36,300 --> 00:35:42,650
on because already the voltage has become
negative, it will reverse bias T 1 and T 4
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00:35:42,650 --> 00:35:47,920
and T 2 and T 3 will conduct immediately.
Here also, for easy analysis, commutation
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overlap, we will neglect; we are aware of
the commutation overlap, with that we know
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00:35:52,960 --> 00:35:58,450
there is a decrease in output voltage. But
for easy analysis, we will assume that commutation
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00:35:58,450 --> 00:36:01,110
this commutation is instantaneous.
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00:36:01,110 --> 00:36:08,110
Now, T 1 and T 2 T 4 will be conducting this
during this portion. Now, I have taken the
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00:36:09,090 --> 00:36:15,630
i1 current direction like this, here. So,
during this portion, i1 will also have the
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00:36:15,630 --> 00:36:22,630
same current. Now, when T 2 and T 3 is conducting;
what will happen? The load current will be
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00:36:24,900 --> 00:36:31,900
transferred to T 2 and T 4 but as far the
load is concerned, till it will go from the
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00:36:33,920 --> 00:36:40,920
same direction. Load current will be always
in the same direction but if you see when
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00:36:43,710 --> 00:36:50,710
T 2 and T 3 are conducting, the load current,
the current I1 will be suddenly reversed.
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00:36:52,330 --> 00:36:58,210
During the tilt, the next thyristor is fired.
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00:36:58,210 --> 00:37:05,210
So, the load current is a stepped waveform
with 180 degree for single phase. Assuming
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load is highly inductive, the load current
is fully dc, regaining our ripple, we say
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00:37:14,660 --> 00:37:21,660
waveform will be a square waveform and what
is the input power? Input power if, this mains
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00:37:22,240 --> 00:37:29,240
we will assume sinusoidal voltage, input power
will be V rms into I rms into cos phi. That
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00:37:33,040 --> 00:37:37,260
is the fundamental component of the voltage
and the fundamental component of the current
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00:37:37,260 --> 00:37:43,230
and the angle between the them. Now, the current
is a alternating waveform with a square wave
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00:37:43,230 --> 00:37:50,230
where the fundamental current will be fundamental
current will be approximately here. The fundamental
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00:37:58,460 --> 00:38:05,300
current will have the same phase relation
which have the same phase relation with respect
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00:38:05,300 --> 00:38:11,200
to the voltage waveform as the square wave
has, the square wave pulse current has with
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00:38:11,200 --> 00:38:12,810
the phase waveform.
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00:38:12,810 --> 00:38:18,590
So now, here, what is the phi? phi is the
firing angle alpha. So here, the input power
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00:38:18,590 --> 00:38:25,590
P in is equal to V rms into I rms into cos
alpha. So, what happens? As the output power
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00:38:40,720 --> 00:38:47,720
increases or decreases or if we want to change
the output dc voltage; let us assume Id is
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00:38:51,430 --> 00:38:57,940
constant, we want to vary the output dc voltage.
As the firing angle varies, the input power
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00:38:57,940 --> 00:39:04,940
factor, the cos alpha as alpha varies it will
get versant. So, what happens? It will affect
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00:39:10,220 --> 00:39:15,810
the input power, the input power factor is
not always constant.
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00:39:15,810 --> 00:39:22,810
So but ideal case, we want ideal case will
be where cos alpha is equal to 1, alpha is
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00:39:23,550 --> 00:39:30,550
equal to 0 that means voltage and current
in the same phase, ideal case voltage. Then
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00:39:36,660 --> 00:39:43,660
the output power P0 will be V rms into I rms.
Now, with different different firing angle
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00:39:48,240 --> 00:39:55,240
that means output power will be with different
firing angle, with different firing angle;
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00:40:01,430 --> 00:40:08,430
what will be the input power and with constant
load power constant load power, what will
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00:40:09,390 --> 00:40:16,390
happen? Vr will be the same, Ir cos, cos as
alpha increases, this cos alpha decreases.
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00:40:17,530 --> 00:40:24,530
Now, to make the power the same the Ir amplitude,
the fundamental amplitude has to vary. So,
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00:40:26,560 --> 00:40:33,560
this happen, so for ideal condition, we want
cos alpha to be 0 and we want nearly, we want
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00:40:36,760 --> 00:40:43,760
nearly cos alpha should be 1 so that alpha
or the phi should be 0. So, this called unity
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00:40:46,320 --> 00:40:53,320
power factor, this ideal condition to achieve.
As the power factor increases, it is not a
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00:40:54,690 --> 00:41:01,690
positive reflection on the input power side.
This is so this the problem with the firing
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00:41:04,250 --> 00:41:11,250
angle control. Now, let us take a semi converter.
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00:41:13,080 --> 00:41:20,080
So, single phase fully
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00:41:30,820 --> 00:41:37,820
controlled converter, disadvantage. What are
the disadvantage? So, before coming to what
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00:41:57,880 --> 00:42:03,850
are the advantage; simple power circuit, the
device will be turned on, thyristor will be
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00:42:03,850 --> 00:42:08,410
turned on the moment the gate pulse is given
and you do not require extra commutation circuit
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00:42:08,410 --> 00:42:14,210
to switch off, these are natural commutation,
the incoming phase will switch off the thyristor
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00:42:14,210 --> 00:42:18,270
in the already conducting phase. So, these
are advantage.
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00:42:18,270 --> 00:42:25,270
What is the disadvantage here? The disadvantage
here, input power factor
is less as the firing angle increases. What
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00:42:35,630 --> 00:42:41,970
is meant by power factor, the definition of
the power factor? The input power factor is
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00:42:41,970 --> 00:42:48,970
equal to definition we can say, power factor
is equal to V rms into I fundamental rms into
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00:42:51,100 --> 00:42:58,100
cos phi 1 alpha divide by the V rms that is
sinusoidal and the total rms of the supply
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00:43:08,230 --> 00:43:15,230
current, rms supply current not the fundamental.
That is a square wave.
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00:43:20,960 --> 00:43:27,960
So, because input current as I told previously,
it has a square wave content. In the square
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00:43:28,619 --> 00:43:34,740
wave content, only the fundamental will generate
the real power that is the required on the
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00:43:34,740 --> 00:43:41,710
output. But the harmonics can also, it can
cause heating causes - I square r losses.
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00:43:41,710 --> 00:43:47,859
So, the total power taken from input side
V rms into I rms, the supply current, the
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00:43:47,859 --> 00:43:54,859
square wave pulse and the usual power is equal
Vr into Ir into cos phi. So, this for a particular
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00:43:55,890 --> 00:44:01,470
Id whether the firing angle is delayed or
increased, only the square wave pulse with
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00:44:01,470 --> 00:44:08,470
Id will shift left side to the right side
so that the V V rms into I rms, the total
278
00:44:08,500 --> 00:44:15,280
supply current will be always the same. But
the input real power Vr into Ir into cos phi
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00:44:15,280 --> 00:44:22,280
that will keeps on reducing as the phi one
increases. So, input power factor is less
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00:44:22,730 --> 00:44:29,730
with power factor angle. So, this is a disadvantage
with the phase controlled converter.
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00:44:32,530 --> 00:44:39,530
So, what will happen? So, it will drag as
the power factor angle power factor or the
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00:44:40,210 --> 00:44:47,210
displacement or the firing angle alpha increases,
it will draw cos phi decreases and sin phi
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00:44:48,560 --> 00:44:55,560
slowly increase. So, it will drag more amd
more lagging power and decrease the power
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00:44:56,619 --> 00:45:02,680
factor. So, this is one disadvantage. So,
ideal case, we do not want any lagging current.
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00:45:02,680 --> 00:45:09,390
The lagging current we do not want, that is
reactive component. It is not generating any
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00:45:09,390 --> 00:45:16,390
useful power. So, ideal case, we want to draw,
to get the maximum efficiency or maximum input
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00:45:17,000 --> 00:45:21,950
maximum power from the input, we require nearly
unity power factor. Current and voltage should
288
00:45:21,950 --> 00:45:26,580
be it should not have any displacement angle
phase angle.
289
00:45:26,580 --> 00:45:29,869
So, let us talk about the semi converter.
So, fully controlled converter; what is the
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00:45:29,869 --> 00:45:35,270
disadvantage? Let us talk about the semi converter.
What will happen for the semi converter? So,
291
00:45:35,270 --> 00:45:42,270
let us draw the semi converter waveform. I
will draw the semi converter waveform; this
292
00:45:58,420 --> 00:46:05,420
is T 1, T 2, D 1, D 2, this is the load. Now,
let us draw the current waveform that is input
293
00:46:17,990 --> 00:46:24,990
current, same like I1 with respect to load
current. Load current is Id, these are mains
294
00:46:40,660 --> 00:46:47,660
voltage waveform. So here, as I told previously
when T 1 and D 1 are conducting, it is a free
295
00:46:50,320 --> 00:46:55,570
wheeling. So, there is a zero period. So,
if you see, the current during the free wheeling
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00:46:55,570 --> 00:47:01,770
time, free wheeling period; there is no power,
there is no current and no power drawn from
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00:47:01,770 --> 00:47:02,690
the mains.
298
00:47:02,690 --> 00:47:09,690
So, typically for a firing angle, it will
be like this, then the zero period, then it
299
00:47:16,270 --> 00:47:23,270
goes like this. So, this is the input total
input current waveform, nature of the current
300
00:47:29,570 --> 00:47:34,940
wavefrom drawn from the mains. So, because
of the part of the time, we are not drawing
301
00:47:34,940 --> 00:47:38,670
power from the mains that means we are not
drawing reactive component power from the
302
00:47:38,670 --> 00:47:43,560
mains. So here, how the fundamental will be?
Fundamental will be the zero crossing the
303
00:47:43,560 --> 00:47:50,560
nearly half of this one. So, the fundamental
current waveform will be like this. So, what
304
00:47:59,570 --> 00:48:01,580
happens?
305
00:48:01,580 --> 00:48:08,580
Eventhough firing angle is here, alpha is
this much distance, the displacement angle,
306
00:48:15,200 --> 00:48:21,300
displacement or the phi is equal to alpha
by that is the fundamental phase shift between
307
00:48:21,300 --> 00:48:27,040
the mains and the current is equal to alpha
by 2. So, that means here there is an improvement
308
00:48:27,040 --> 00:48:32,260
in the power factor. So, for the same firing
angle, the reactive power drawn from the mains
309
00:48:32,260 --> 00:48:38,070
for a semi converter is less but semi converter,
it has its own advantages as well as disadvantage.
310
00:48:38,070 --> 00:48:42,130
As far as the power factor is concerned, it
has a better power factor.
311
00:48:42,130 --> 00:48:49,130
Now, the question is how to get improved power
factor from the phase controlled converter?
312
00:48:51,830 --> 00:48:58,830
Then the question is with natural commutation,
is it possible? Then we have to introduce
313
00:48:59,330 --> 00:49:06,330
these type of half period or force the free
wheeling in a phase control by appropately
314
00:49:08,349 --> 00:49:12,550
turning on and turning off the devices. So,
force commutation is required. So, if you
315
00:49:12,550 --> 00:49:19,550
see here, we require single phase fully controlled
converter. Let us take the single phase thyristor.
316
00:49:21,250 --> 00:49:28,250
Why we require? We require both positive dc
and negative dc but the semi converter, semi
317
00:49:31,000 --> 00:49:37,950
converter will have only 0 to positive voltage
but the advantage of semi converter is there
318
00:49:37,950 --> 00:49:42,800
is an improvement in the power factor that
is the displacement angle between the fundamental
319
00:49:42,800 --> 00:49:49,800
voltage and fundamental input current is alpha
by 2. So, the power factor, power factor increases
320
00:49:51,030 --> 00:49:55,920
compared to the single phase fully controlled
converter.
321
00:49:55,920 --> 00:50:02,369
Now, we want to in ideal case, we want to
draw the input current, input power as close
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00:50:02,369 --> 00:50:09,369
as to unity. The fundamental should be fundamental
should be in phase with the as close as, as
323
00:50:10,340 --> 00:50:16,920
closely as possible in phase with the input
mains so that we can have nearly unity power
324
00:50:16,920 --> 00:50:23,920
factor and the system will not draw any reactive
component. So, the efficiency of the system
325
00:50:24,570 --> 00:50:31,570
can also be improved. In that case, what we
require? We require a we require a full single
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00:50:34,619 --> 00:50:39,640
phase fully controlled converter for both
positive and negative output dc voltage. But
327
00:50:39,640 --> 00:50:46,430
to improve the power factor, we have to force
the converter into semi converter operation
328
00:50:46,430 --> 00:50:53,430
both the positive cycle and negative cycle.
That means we should have a situation like
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00:50:53,670 --> 00:51:00,670
the single phase half bridge converter that
is the free wheeling, free wheeling is happening.
330
00:51:00,960 --> 00:51:04,490
During the free wheeling, there is a during
a free wheeling period forcibly happening
331
00:51:04,490 --> 00:51:11,490
through the thyristors. In that case, we have
to forcibly turn on the device. Not forcibly
332
00:51:13,250 --> 00:51:20,250
turn on, forcibly turn off the device. That
means natural commutation is required. That
333
00:51:20,760 --> 00:51:26,820
means the thyristors should for some period
it should act as diodes as for the conduction
334
00:51:26,820 --> 00:51:32,540
period with respect to the single phase semi
controlled converter as concerned. But there
335
00:51:32,540 --> 00:51:38,660
are many commutations are available, many
of these things are already used in some applications,
336
00:51:38,660 --> 00:51:44,570
its already available in text book. So, some
of the semi converter operation of fully converter,
337
00:51:44,570 --> 00:51:49,720
I will be taking in the next class. Then the
commutation circuit, one of the very popular
338
00:51:49,720 --> 00:51:56,690
commutation circuit and forced commutation
circuit and how to design the components;
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00:51:56,690 --> 00:52:03,690
we will study in the next class.