﻿1 00:01:05,960 --> 00:01:12,960 Today we shall start our discussion on the different specifications of logic families 2 00:01:13,930 --> 00:01:20,930 by which you characterize them. We had already discussed a little bit last class so we shall 3 00:01:23,190 --> 00:01:30,190 now go into the details. The first one which we shall take up is propagation delay. What 4 00:01:36,690 --> 00:01:43,690 is the propagation delay of logic circuit? Now if you have an input say if you take an 5 00:01:47,170 --> 00:01:54,170 inverter say and if the input waveform is like this, the output waveform is going to 6 00:02:07,350 --> 00:02:14,350 be something like this. 7 00:02:16,280 --> 00:02:23,280 This is how the input and the output varies. The propagation delay is defined as the difference 8 00:02:26,700 --> 00:02:33,700 or in time between the 50% points of the input and the output waveform that is this is the 9 00:02:37,750 --> 00:02:44,750 logic low and this is logic high. So midway between this logic low and logic high, the 10 00:02:45,090 --> 00:02:51,140 instant at which you have, the voltage is at the middle point of the input form and 11 00:02:51,140 --> 00:02:58,140 this is for the output waveform. So this difference in time is the propagation delay for a high 12 00:03:05,560 --> 00:03:12,560 to low transition. So you should call it tpdHL, HL stands for high to low transition. 13 00:03:14,720 --> 00:03:21,720 Similarly you can have a propagation delay for a low to high transition and these two 14 00:03:25,940 --> 00:03:30,639 propagation delays that is for high to low transition and low to high transitions need 15 00:03:30,639 --> 00:03:37,639 not be the same, they can be different. Usually the propagation delay of a logic circuit is 16 00:03:39,430 --> 00:03:43,290 defined as the average of these two propagation delays. 17 00:03:43,290 --> 00:03:50,290 So the propagation delay will be in the average of high to low and the low to high propagation 18 00:03:55,040 --> 00:04:02,040 delays. So this is the definition of a propagation delay of a logic gate. Now how to measure 19 00:04:04,859 --> 00:04:11,859 it? There is a very interesting circuit to measure this propagation delay which is called 20 00:04:12,540 --> 00:04:19,540 the ring oscillator and that is used to measure the propagation delay of any logic gate. The 21 00:04:20,979 --> 00:04:27,500 ring oscillator consists of an odd number of inverters. So if you have a NAND gate for 22 00:04:27,500 --> 00:04:34,290 example you can connect it as an inverter that is you short the inputs, it behaves as 23 00:04:34,290 --> 00:04:41,290 an inverter. So if you have an odd number of inverters say I will draw three inverters 24 00:04:46,020 --> 00:04:53,020 like this and you connect it like this and this is called the ring oscillator. Now what 25 00:04:53,210 --> 00:04:59,160 is going to happen is suppose this is logic one here, this is going to be zero here, this 26 00:04:59,160 --> 00:05:02,710 is going to be one here and this is going to be zero here. 27 00:05:02,710 --> 00:05:08,699 So this is connected here so this one becomes zero and if this one becomes zero here this 28 00:05:08,699 --> 00:05:14,790 zero is going to become one and this one is going to become zero and this zero is going 29 00:05:14,790 --> 00:05:21,139 to become one. So at each output and again this one is going to be transmitted here. 30 00:05:21,139 --> 00:05:28,139 So at each output the voltage constantly toggles between the two levels 0 1, 1 to 0 like that. 31 00:05:29,889 --> 00:05:36,889 So if you observe the waveform at any given point or at any input or output of a logic 32 00:05:40,750 --> 00:05:47,750 gate, you will observe a waveform like this which is continuously varying, a train of 33 00:05:56,490 --> 00:06:00,430 pulses. 34 00:06:00,430 --> 00:06:07,430 This train of pulses and the frequency of this waveform is going to tell us about the 35 00:06:10,110 --> 00:06:17,110 propagation delay because the time required for this one to change to zero is the time 36 00:06:17,400 --> 00:06:24,020 required, once this changes from one to zero this change has to propagate through all this 37 00:06:24,020 --> 00:06:29,289 and come back here. So once it becomes zero this has to go to one, this one has to go 38 00:06:29,289 --> 00:06:36,289 to zero and zero has to go to one then only this changes. So the frequency, the time taken 39 00:06:40,689 --> 00:06:47,689 for it to change is determined by the propagation delay and since in each time period you have 40 00:06:51,490 --> 00:06:58,490 two transitions, the propagation delay tpd will be given by 1 by 2 Nf where f is the 41 00:07:20,810 --> 00:07:25,620 frequency of oscillation or you can write it this way, actually s is equal to 1 by 2 42 00:07:25,620 --> 00:07:32,620 N tpd that is f is the frequency of oscillation, N is the number of inverters and two because 43 00:07:38,270 --> 00:07:41,779 in each time period you have 2 oscillation. 44 00:07:41,779 --> 00:07:48,779 Basically the time period of this is equal to twice n tpd, the time period of oscillation 45 00:07:50,800 --> 00:07:57,800 is twice N tpd, the propagation delay. So looking at the waveform and knowing the frequency 46 00:07:59,409 --> 00:08:04,360 you can find out the propagation delay. In fact this is a very important circuit and 47 00:08:04,360 --> 00:08:10,529 is used as a test structure whenever you are developing logic circuit that is you want 48 00:08:10,529 --> 00:08:17,069 to know what is going to be the time period or what is going to be the frequency at which 49 00:08:17,069 --> 00:08:24,069 you can operate this or the propagation delay of any logic circuit, you usually use this 50 00:08:24,370 --> 00:08:28,110 circuit. 51 00:08:28,110 --> 00:08:35,110 In addition to the propagation delay there are two other delays associated with the logic 52 00:08:37,719 --> 00:08:44,540 gate what is called the rise time and the fall time. So the rise time is usually denoted 53 00:08:44,540 --> 00:08:51,540 by tr and the fall time by tf so tr is the rise time and tF is the fall time. That is 54 00:08:59,690 --> 00:09:06,690 if you look at this, observe this waveform here the time required for this to fall that 55 00:09:07,680 --> 00:09:14,160 is the fall time. Usually it is very difficult to find out exactly the time required for 56 00:09:14,160 --> 00:09:21,160 it to fall from the logic high to logic low because at these points the transitions are 57 00:09:22,950 --> 00:09:29,950 very slow at the edges. So usually it is defined as in terms of the 90% and 10% points. 58 00:09:31,360 --> 00:09:38,360 So the rise time is the time required for the waveform to rise from 10% to 90% value 59 00:09:44,150 --> 00:09:51,150 and the fall time is from 90% to 10%. So these are the two other specifications which you 60 00:09:59,280 --> 00:10:05,130 may observe if you look at a specification sheet of any logic family. So propagation 61 00:10:05,130 --> 00:10:12,130 delay rise time and the fall times and they are very important to know if you are going 62 00:10:12,760 --> 00:10:19,760 to make a circuit. So this is about the delays then we move on to the next characteristic 63 00:10:29,180 --> 00:10:36,180 which is the power dissipation. 64 00:10:43,880 --> 00:10:49,160 The power dissipation is another characteristic and it is a very important characteristic 65 00:10:49,160 --> 00:10:56,160 specially in the present scenario where the trend is to pack in large number of circuits 66 00:10:59,060 --> 00:11:05,180 in a given chip as many devices as possible in a given chip. You have millions of transistors 67 00:11:05,180 --> 00:11:12,180 nowadays in the VLSI chips, if you are introducing so many devices, the power dissipation is 68 00:11:16,620 --> 00:11:23,620 obviously going to go up. So in order to be able to integrate a larger number of circuits, 69 00:11:26,590 --> 00:11:32,410 larger number of components the power dissipation has to be brought down somehow. 70 00:11:32,410 --> 00:11:39,410 In fact some of the latest microprocessor chips consume as much as 10 of watts of power 71 00:11:43,240 --> 00:11:50,240 and if you consider that the voltages or power supply voltages was 5 volts, now it has come 72 00:11:53,140 --> 00:12:00,140 down to 3 volts or so. That means few amperes of currents which is quite a large thing, 73 00:12:06,450 --> 00:12:13,450 in the small pins they must be able to carry so much current and that is big constraint. 74 00:12:16,350 --> 00:12:21,590 The power dissipation is a very important consideration nowadays and people are looking 75 00:12:21,590 --> 00:12:26,990 at ways to reduce the power dissipation. In fact you must have one of the reasons; there 76 00:12:26,990 --> 00:12:33,990 are many reasons of course one of the reasons why the power supply voltages are coming down 77 00:12:35,150 --> 00:12:41,110 is because of the necessity to reduce power dissipation, so you know that nowadays you 78 00:12:41,110 --> 00:12:48,110 hear so much of low power circuits. So lot of research is going on in that anyway. So 79 00:12:48,750 --> 00:12:55,750 this is a very important consideration power dissipation, how much power does a gate dissipates 80 00:12:57,830 --> 00:13:04,830 that is the basic unit, how much does it dissipate? Just take a circuit like this. Let us consider 81 00:13:18,370 --> 00:13:25,370 this circuit, there is a current source I and this is an inverter circuit basically 82 00:13:30,830 --> 00:13:37,610 bipolar b j t circuit and this is driving a capacitive load. 83 00:13:37,610 --> 00:13:44,610 Now this is a current source, so if this transistor is on, the current flows into the transistor 84 00:13:48,560 --> 00:13:55,560 and this goes to saturation and the output voltage is low and when the transistor is 85 00:13:56,530 --> 00:14:01,820 cut off what happens this transistor, the current cannot flow into the transistor it 86 00:14:01,820 --> 00:14:08,820 goes into the capacitance and it charges the capacitance, the output voltage goes high. 87 00:14:09,130 --> 00:14:15,270 In such a situation if you look at the power dissipation suppose we call this the pd this 88 00:14:15,270 --> 00:14:22,270 is the power dissipation. The power dissipation is given by vCC into I then when you are charging 89 00:14:30,320 --> 00:14:37,320 this capacitance with a current i what is the delay? That is suppose the output voltage 90 00:14:40,120 --> 00:14:47,120 swing there is a term called the logic swing that is the change in the output voltage that 91 00:14:49,290 --> 00:14:56,290 is the difference between the logic low and the logic high suppose it is given by vL logic. 92 00:14:56,900 --> 00:15:02,850 So what is the delay when this capacitance is charged with a current source of value 93 00:15:02,850 --> 00:15:09,850 i? When you are charging a capacitance i is equal to cd vd. So if you write i is equal 94 00:15:14,230 --> 00:15:21,230 to c, so the change in the voltage is vL which is the logic swing and the delay will be given 95 00:15:23,080 --> 00:15:30,080 by say td. So now you can write this as or td is equal to c vL by I then from these two 96 00:15:43,970 --> 00:15:50,970 expressions the power dissipation and the delay you can write pd into td is equal to 97 00:15:54,280 --> 00:16:01,280 vCC C into vL. So this expression so this pd td it is an important figure of merit of 98 00:16:12,900 --> 00:16:19,900 a logic family, it is called the power delay product and you see that this is independent 99 00:16:22,590 --> 00:16:29,590 of the value of the current source. Now in a particular logic family, suppose this is 100 00:16:31,900 --> 00:16:33,910 the basic inverter. 101 00:16:33,910 --> 00:16:40,910 Now you can change these value of current by say for example if you have resistance, 102 00:16:41,350 --> 00:16:48,350 you can change the value of resistance. Now that is going to affect both the power dissipation 103 00:16:52,100 --> 00:16:59,100 and the delay but the power delay product is independent of the current source value 104 00:17:05,689 --> 00:17:12,000 and is just dependent on vCC that is the power supply voltage, of course here the capacitive 105 00:17:12,000 --> 00:17:18,630 load, the value of the capacitive load and the logic swing. So this is a characteristic 106 00:17:18,630 --> 00:17:21,740 figure of merit for the circuit. 107 00:17:21,740 --> 00:17:28,520 In a given circuit you can operate it at different power dissipation levels and delay levels 108 00:17:28,520 --> 00:17:33,350 by changing the value of the current. You have a circuit, if you just change the value 109 00:17:33,350 --> 00:17:40,350 of resistances for example in the circuit, it will be operating at a different for example 110 00:17:41,030 --> 00:17:46,530 if you increase the resistance values, the power dissipation is going to reduce because 111 00:17:46,530 --> 00:17:51,419 the current is going to reduce but at the same time the delays are also going to be 112 00:17:51,419 --> 00:17:58,150 affected but it is going to affect both the participation and the delay but the power 113 00:17:58,150 --> 00:18:05,150 delay product is independent of that. So this is the characteristic of the logic family 114 00:18:07,659 --> 00:18:14,659 and so you can operate it at different power dissipation or delay values for example you 115 00:18:16,039 --> 00:18:23,039 may have come across some of these curves, this pd versus td. 116 00:18:28,389 --> 00:18:35,389 Now if you plot them on a log scale, these both power dissipation and delay you will 117 00:18:40,370 --> 00:18:47,370 get these straight lines indicate constant power delay constants. So that is here you 118 00:18:59,019 --> 00:19:04,809 can operate may be a given circuit at this point or this point. You can move along this 119 00:19:04,809 --> 00:19:09,289 line that is in a constant power delay product by changing the value of this current source 120 00:19:09,289 --> 00:19:16,289 for example but of course you must also remember that this takes into account only a capacitance 121 00:19:19,529 --> 00:19:26,529 which is a constant but this is only true when we are operating the circuit, in the 122 00:19:26,620 --> 00:19:33,620 view of the last class you must remember that only when the capacitances or the junction 123 00:19:35,820 --> 00:19:41,899 capacitance type for a b j t. If you have the diffusion capacitance this capacitance 124 00:19:41,899 --> 00:19:46,179 is no longer going to be a constant but again it becomes a function of current. 125 00:19:46,179 --> 00:19:53,179 So when you are operating in the low current regime then only this is true but anyway so 126 00:19:53,499 --> 00:20:00,499 this gives us some idea and you can operate the circuit at any of these lines. In fact 127 00:20:00,799 --> 00:20:07,799 if you see that for example an ECL would be somewhere here, whereas a TTL would be somewhere 128 00:20:10,429 --> 00:20:17,429 here that is although you can operate along this line but in a TTL for example there is 129 00:20:18,879 --> 00:20:25,879 a limitation, you cannot go below a particular delay because after that it is no longer going 130 00:20:27,379 --> 00:20:32,659 to follow this curve because this capacitance as we have seen in last class, the capacitance 131 00:20:32,659 --> 00:20:39,659 is no longer going to be a constant. It is the other capacitances which take up. 132 00:20:41,429 --> 00:20:48,429 For example if you take I square L, you know its somewhere here I square l has a much lower 133 00:20:50,679 --> 00:20:57,679 power delay product compared to TTL or ECL. So as a circuit this is a much better circuit 134 00:20:59,649 --> 00:21:06,120 but of course there is a limitation as we shall see that you cannot go to very low delays, 135 00:21:06,120 --> 00:21:08,879 you cannot operate it at much very high speeds. 136 00:21:08,879 --> 00:21:13,769 So anyway we shall discuss that in detail. So this power delay product is another important 137 00:21:13,769 --> 00:21:20,769 figure of merit or specific characteristic of a logic family. What is the power delay 138 00:21:22,340 --> 00:21:29,340 product associated? Now in fact this power dissipation and the speed delays go hand in 139 00:21:35,950 --> 00:21:42,950 hand, it gives rise to many interesting considerations. For example let us take a particular logic 140 00:21:46,539 --> 00:21:53,539 family where the capacitance which we are looking here is let us say just take two some values 50 141 00:21:59,779 --> 00:22:06,779 feet of error say vCC is 3 volts and vL is equal to 0.5 volts. Let us consider that many 142 00:22:19,499 --> 00:22:26,499 of these chips, the price consideration comes from the packaging. 143 00:22:26,669 --> 00:22:32,820 Suppose you want a one watt package that is package which can dissipate one watt of power. 144 00:22:32,820 --> 00:22:37,389 So that is the limitation there, that you must have the power dissipated must be one 145 00:22:37,389 --> 00:22:43,840 watt. Now if you go for a ten watt package the price goes up. So you may be want to limit 146 00:22:43,840 --> 00:22:50,840 in a particular package so suppose you are going to this particular logic family, suppose 147 00:22:52,629 --> 00:22:59,629 you are going to package it in a one watt package and suppose you want to have say there are 148 00:23:05,789 --> 00:23:12,100 case one let us say you want to operate it at a very high speed that is say very low 149 00:23:12,100 --> 00:23:19,100 delays of say hundred Pico second. So you want to operate the circuits at high speeds. 150 00:23:24,919 --> 00:23:31,919 So now the question is for this high speed operation how many gates can be accommodated 151 00:23:35,809 --> 00:23:42,190 in a one watt package? How do you do that? 152 00:23:42,190 --> 00:23:48,369 So you have to calculate the power dissipation, so you know that this expression here. The 153 00:23:48,369 --> 00:23:55,110 product of the power dissipation and the delay is equal to vCC into vL. So now what you can 154 00:23:55,110 --> 00:24:00,879 find out is you know td you know all these things, so you can find out the power dissipation 155 00:24:00,879 --> 00:24:07,879 per gate and so how many gates you can accommodate? So I just write it here so C vCC into vL, 156 00:24:15,289 --> 00:24:22,289 if you put substitute all these values what you will get is 0.75 milli watt. So the power 157 00:24:24,769 --> 00:24:30,190 dissipation is going to be 0.75 milli watt per gate, if you operate it at a delay of 158 00:24:30,190 --> 00:24:37,190 100 Pico seconds and so if you have a one watt package, so number of gates you can accommodate 159 00:24:37,899 --> 00:24:44,899 in the package is one watt divided by 0.75 milli watt. That is 1300 gates in that one watt package. 160 00:24:56,580 --> 00:25:03,580 Now suppose in another case you want high packing density, the same circuit you want 161 00:25:05,480 --> 00:25:12,480 high packing density. Suppose you want 10 to the power 5 gates per package and you have 162 00:25:15,529 --> 00:25:22,529 a more complex circuit. So what is going to be the power dissipation per gate? One watt 163 00:25:27,759 --> 00:25:34,759 divided by 10 to the power 5, pd power dissipation is going to be one watt divided by 10 to the 164 00:25:36,210 --> 00:25:43,210 power 5 that is 0.01 milli watt. Now if you write td that is again you put down the values 165 00:25:51,610 --> 00:25:58,610 C vCC vL by pd which you got here, you will find that the delay is going to be 7.5 nano 166 00:26:00,820 --> 00:26:03,100 seconds per gate. 167 00:26:03,100 --> 00:26:10,100 Just put down these values you will get this, so which means that the delay is going to 168 00:26:10,869 --> 00:26:17,869 be much higher. So there is always a compromise between the power dissipation and the delay 169 00:26:20,860 --> 00:26:25,580 that is what I want to point out that although you talk of power dissipation and delay are 170 00:26:25,580 --> 00:26:32,580 separate entities but there is a compromise always. If you want to, you can trade of between 171 00:26:34,440 --> 00:26:41,440 these two quantities. So that is about the power dissipation and delay. Then we move 172 00:26:46,570 --> 00:26:53,570 on to the next topic that is noise margin that is the third one. The noise margin is 173 00:27:02,619 --> 00:27:09,619 also very important characteristic of a logic family and it tells you that how much noise 174 00:27:14,960 --> 00:27:21,960 the particular circuit can tolerate, if you are using in a noisy environment. 175 00:27:25,399 --> 00:27:31,580 Now you have seen the characteristic of an inverter, we shall take up again the characteristic 176 00:27:31,580 --> 00:27:38,090 of an inverter. So this is the input voltage, this is the output voltage it is something 177 00:27:38,090 --> 00:27:45,090 like this. When the input is low, the output is high, when the input is high, the output 178 00:27:49,690 --> 00:27:56,690 is low. This is known as the logic swing, the output high and the output low the difference 179 00:28:00,799 --> 00:28:07,799 in these values is known as the logic swing. This difference is the logic swing vL which 180 00:28:10,309 --> 00:28:17,309 we have already discussed, this is also an important parameter. Now if a logic swing 181 00:28:19,929 --> 00:28:26,929 is high it is true that the noise margin is also going to be high. We shall come to the 182 00:28:27,809 --> 00:28:34,809 definition of the noise margin but anyway if the logic swing is high, the noise margin 183 00:28:35,590 --> 00:28:42,590 is going to be high but at the same time you can see that the delay also increases in a 184 00:28:42,840 --> 00:28:49,840 logic circuit because the output of a gate has to change from the logic low to logic 185 00:28:52,019 --> 00:28:57,119 high. Basically you have to charge a capacitor and if you are charging a capacitor through 186 00:28:57,119 --> 00:29:03,039 a larger voltage it obviously is going to take more time. If the voltage through which 187 00:29:03,039 --> 00:29:08,940 it is charging is less takes less time. So the important thing is that all these characteristics 188 00:29:08,940 --> 00:29:15,940 you know are not independent but they are sort of dependent on one another. 189 00:29:16,139 --> 00:29:23,139 Now suppose you have a circuit like this, you have two inverters we call this inverter 190 00:29:29,830 --> 00:29:36,830 one and we call this inverter 2 and so here what you have is you can write vin1 is equal 191 00:29:40,470 --> 00:29:47,470 to vout2 and vin2 is equal to v output one. Now suppose this is the characteristic of 192 00:30:03,169 --> 00:30:10,169 inverter one, so I will just remove this, this is the characteristic of an inverter 193 00:30:10,619 --> 00:30:17,619 one. Now let us call this v output one and this 194 00:30:21,950 --> 00:30:28,950 is v input one. Now this is equal to v output 2 and this is equal to vin2. So if you want 195 00:30:47,960 --> 00:30:54,230 to now plot the input output characteristics of the second inverter that is inverter 2. 196 00:30:54,230 --> 00:31:01,230 This is the output access, this is the input access so you can plot it like this. This 197 00:31:06,649 --> 00:31:11,070 is the same characteristics they are identical inverters, we are just plotting it like this 198 00:31:11,070 --> 00:31:18,070 now because this is the output axis, this is the input axis going this way and so now 199 00:31:21,009 --> 00:31:28,009 in these two inverters if they are connected like this, the stable points of operation 200 00:31:28,330 --> 00:31:35,119 are the points of intersection of these two characteristics. So you see that these characteristics 201 00:31:35,119 --> 00:31:42,119 intersect at this point, this point as well as this point. So only at these points v input 202 00:31:43,159 --> 00:31:50,159 1 is equal to v output 2. So this point is actually very unstable because of the very 203 00:31:51,649 --> 00:31:57,509 high gain associated with any point because if you have at this point any small perturbation 204 00:31:57,509 --> 00:32:01,700 somehow noise or something, it will move away from that point. 205 00:32:01,700 --> 00:32:08,700 So usually the device operates at this point or this point, so if this point is actually called, this value v output low 206 00:32:31,960 --> 00:32:38,960 and this is v output high. So these are the two operating points, this point and this 207 00:32:48,879 --> 00:32:55,659 point, these are the two possible operating points of the inverter. Now where does noise 208 00:32:55,659 --> 00:33:02,659 come in. Suppose you have a noise source introduced here in between let us call this vN. Now what 209 00:33:10,289 --> 00:33:17,289 is happening is suppose this is low, this is vOL say and so you have the same input 210 00:33:19,549 --> 00:33:26,549 to this. Now when the input here is vOL the output is high. Now if the input here it is 211 00:33:34,139 --> 00:33:41,139 vOL so here the input to gate 2 is vOL plus vn and so what is going to happen is the input 212 00:33:46,450 --> 00:33:53,450 point to the inverter two actually I should be in this way. Anyway doesn’t matter it 213 00:33:54,239 --> 00:34:01,239 is the same in whichever way you look at it, I actually should have drawn the noise source 214 00:34:01,690 --> 00:34:02,940 here. 215 00:34:02,940 --> 00:34:07,429 So as this noise value increases what you are doing is you are shifting this operating 216 00:34:07,429 --> 00:34:14,429 point. So it is moving like this so even if the noise source is this much noise voltage, 217 00:34:16,710 --> 00:34:23,710 the output voltage is still equal to this high. This is vOH, this is also vOH, this 218 00:34:23,780 --> 00:34:30,780 is also vOL, this is also vOL, this is also vOH if you look at this way it is the same. 219 00:34:40,980 --> 00:34:47,919 When the input voltage changes it is still vOH almost close to vOH but if this input 220 00:34:47,919 --> 00:34:54,919 voltage changes by a lot then the output voltage may start to fall and then only it creates 221 00:34:57,200 --> 00:35:03,380 problems. Now what is the input voltage up to which it can tolerate? Usually the definition 222 00:35:03,380 --> 00:35:10,380 is that where the slope of this curve becomes equal to minus one that is the maximum you 223 00:35:12,510 --> 00:35:19,510 can tolerate. When the slope becomes minus one at this point this is called vIL that 224 00:35:30,599 --> 00:35:36,020 is the maximum value of the input voltage which is going to be considered as a logic 225 00:35:36,020 --> 00:35:42,619 low by this circuit that is vIL. The maximum value of the input voltage which is considered 226 00:35:42,619 --> 00:35:49,619 as logic low that is vIL beyond that it is no longer logic low at the input. 227 00:35:49,920 --> 00:35:56,920 Similarly at this end you have another minus slope is equal to minus one point and this 228 00:35:59,400 --> 00:36:06,400 is called vIH which is the minimum value at the input which is considered as a logic high. 229 00:36:11,619 --> 00:36:17,349 So this is logic high at the input, isn’t it? Normally if you apply this voltage it 230 00:36:17,349 --> 00:36:22,609 is logic high but if you the noise source pulls it down. Up to this point it is still 231 00:36:22,609 --> 00:36:27,950 considered logic high, after that it is no longer logic high. So it can tolerate this 232 00:36:27,950 --> 00:36:34,230 much amount of noise when the input is high. 233 00:36:34,230 --> 00:36:41,230 When the logic is low it can tolerate this much amount of noise. So there are two noise 234 00:36:41,510 --> 00:36:48,510 margins usually one is for logic low and the other is for logic high. So you have noise 235 00:36:50,960 --> 00:36:57,960 margin low is equal to vIL minus vOL and noise margin high is equal to vOH minus vIH. So 236 00:37:28,559 --> 00:37:35,450 these are the two noise margins in the circuit. In fact there are other definitions of noise 237 00:37:35,450 --> 00:37:42,450 margin also, a more stringent definition as you just pointed out that suppose in this 238 00:37:45,599 --> 00:37:52,599 circuit if you go back to this circuit, you have another noise source here and these are 239 00:37:53,530 --> 00:38:00,530 equal and opposite noise sources in the sense that when this end is positive, if this goes 240 00:38:04,789 --> 00:38:09,390 positive, if this is increasing the input voltage here it is pulling down the output 241 00:38:09,390 --> 00:38:16,390 voltage. So this noise source and this noise source further pulls it down, equal and opposite 242 00:38:20,579 --> 00:38:23,930 and this is a more stringent condition. 243 00:38:23,930 --> 00:38:30,930 There are two noise sources and both are acting in such a way as to change the state of the 244 00:38:34,530 --> 00:38:41,530 particular gate and for that particular condition when you have two noise sources, the noise margin is 245 00:38:49,660 --> 00:38:56,660 actually given by what is called the maximum square noise margin, so sometimes you may 246 00:38:59,799 --> 00:39:06,799 come across this term. So you must know what it is, the maximum square noise margin. It 247 00:39:09,710 --> 00:39:15,549 is called the maximum square noise margin because the noise margin in this case is given 248 00:39:15,549 --> 00:39:22,549 by the maximum square that can be accommodated in this region. This drawing is not perfectly 249 00:39:32,809 --> 00:39:39,809 correct, the maximum square which you can accommodate here is going to be the same as 250 00:39:41,780 --> 00:39:48,349 the maximum square which you can accommodate here because they are sort of identical, from 251 00:39:48,349 --> 00:39:53,730 my drawing it is not very clear maybe I should redraw it. 252 00:39:53,730 --> 00:40:00,730 It should go something like this. So here the definition of the maximum square noise 253 00:40:03,599 --> 00:40:09,700 margin you don’t differentiate between logic low and logic high, it is the same because 254 00:40:09,700 --> 00:40:16,700 here in this case if you look at this figure one of the gates will be at logic input will 255 00:40:17,960 --> 00:40:24,960 be logic low and the other gate input will be logic high. So it doesn’t matter, so 256 00:40:27,720 --> 00:40:34,520 that is called the maximum square noise margin that is given by the maximum square and is 257 00:40:34,520 --> 00:40:41,520 given by the side of the maximum square which can be accommodated inside this. This value here is called the maximum square vMS, 258 00:40:51,289 --> 00:40:58,289 maximum square noise margin this side of the square. So this is another although generally 259 00:41:06,380 --> 00:41:12,309 people talk of low noise margin and noise margin high these two noise margins but this 260 00:41:12,309 --> 00:41:17,329 maximum square noise margin is also sometimes referred to and that is the definition of 261 00:41:17,329 --> 00:41:22,799 the maximum square noise margin where you have two noise sources, sort of aiding each 262 00:41:22,799 --> 00:41:29,799 other, helping each other so that even a smaller noise can create more damage. So that is about 263 00:41:34,010 --> 00:41:40,380 noise margins and obviously the larger the noise margin the better is the circuit because 264 00:41:40,380 --> 00:41:44,380 it can operate at more noisy environment. 265 00:41:44,380 --> 00:41:51,380 In fact the reason why digital circuits have become so important is actually, even if you 266 00:41:51,890 --> 00:41:58,890 talk of audio circuits, even such some things like analog that is very much analog like 267 00:42:03,240 --> 00:42:10,240 for example audio, amplifiers you have digital amplifiers and many other things which is 268 00:42:10,930 --> 00:42:17,930 everything becoming digital nowadays because of the larger noise immunity we can say of 269 00:42:19,980 --> 00:42:26,880 digital circuits, because if you look at the circuit you know you can see if you just go 270 00:42:26,880 --> 00:42:33,880 back to this you see that even when the input changes by a long margin, the output remains 271 00:42:36,000 --> 00:42:43,000 the same. Even while you have lot of noise it does affect the output because here the 272 00:42:43,319 --> 00:42:50,319 gain is almost zero, isn’t it? The gain is almost zero so the region where you operate 273 00:42:51,230 --> 00:42:58,160 a digital circuit know this point or this point the gain at these points are very low 274 00:42:58,160 --> 00:43:00,099 almost zero. 275 00:43:00,099 --> 00:43:05,690 So if you have a noise that is almost wiped out there is no effect of noise, only when 276 00:43:05,690 --> 00:43:11,650 you come to this part then it becomes important. So that is why the digital circuit is much 277 00:43:11,650 --> 00:43:18,650 more immune to noise, it does not easily get affected by noise. So this gives us the idea 278 00:43:25,970 --> 00:43:32,970 of the noise margin so what is the maximum noise the circuit can tolerate? Obviously 279 00:43:34,190 --> 00:43:40,569 if you want to have a higher noise margin the input output characteristics should be 280 00:43:40,569 --> 00:43:47,569 more symmetric. We shall see that as we go about that is basically the noise margin low, 281 00:43:48,430 --> 00:43:55,430 it’s no point having a very high noise margin high and a very low noise margin low because 282 00:43:56,130 --> 00:44:03,130 it is mostly governed by the lower value. So if you have a symmetric input output characteristics 283 00:44:04,089 --> 00:44:11,089 that is the transition point I will just go back to that again, this one here. So another 284 00:44:12,140 --> 00:44:19,140 definition I should say this point, if you look at this point which also has lot of significance 285 00:44:21,809 --> 00:44:28,809 that is it is called the logic threshold. Logic threshold means at that value, if at 286 00:44:36,520 --> 00:44:43,520 this point the input is equal to the output. At this point the input voltage is equal to 287 00:44:45,589 --> 00:44:52,589 the output voltage that is it is like this. Now when the input is low if you call this 288 00:44:57,260 --> 00:45:04,260 logic threshold value here, when the input is lower than the logic threshold, the output 289 00:45:07,150 --> 00:45:13,960 is higher than the logic threshold and when the input is higher than the logic threshold, 290 00:45:13,960 --> 00:45:15,140 output is lower than the logic threshold. 291 00:45:15,140 --> 00:45:22,140 I will just give you an example; I shall just draw two curves, two inverter characteristics. 292 00:45:22,700 --> 00:45:29,700 So this is one inverter characteristic so this is another inverter characteristic, now 293 00:45:36,460 --> 00:45:43,460 if you draw this, the logic threshold is here for this one. So this is slope is equal to 294 00:45:49,099 --> 00:45:56,099 one so vin is equal to vout on this curve and if vin is slightly less than this value 295 00:45:57,049 --> 00:46:04,049 then v output is higher than v input because this is inverter and so this is the logic 296 00:46:04,170 --> 00:46:10,289 threshold. This logic threshold is much lower here, this logic threshold is much higher 297 00:46:10,289 --> 00:46:11,339 here. 298 00:46:11,339 --> 00:46:18,339 Now obviously if you are operating from 5 volts then this is 5 volts. If the logic threshold 299 00:46:19,589 --> 00:46:26,589 here is 2.5 volts this is the most symmetric inverter characteristics, this may be 1 volt 300 00:46:32,130 --> 00:46:39,130 say. Now if for this one, if I draw the curve like this, as we have drawn previously while drawing the noise margin, 301 00:46:55,510 --> 00:47:02,510 you will find that the noise margin low is very small whereas the noise margin high is 302 00:47:04,359 --> 00:47:11,359 very large. Again it is the lower value which is important, it’s no point having a very 303 00:47:12,890 --> 00:47:19,890 high value of noise margin high and having a very low noise margin of very low because 304 00:47:25,589 --> 00:47:32,539 you will have in a circuit some gates at operating at output logic low and some at logic high 305 00:47:32,539 --> 00:47:38,339 and so if the small value of noise margin, a small noise is going to upset the operation, 306 00:47:38,339 --> 00:47:41,349 if you have a low margin of low. 307 00:47:41,349 --> 00:47:48,349 So it is always preferred, the ideal inverter characteristic would have the logic threshold 308 00:47:48,460 --> 00:47:55,460 some where midway between logic high and logic low. There you have in this case the noise 309 00:48:00,760 --> 00:48:07,760 margin high is this much, noise margin low is this much. So they are almost same so the 310 00:48:10,400 --> 00:48:15,470 ideal characteristics would have the logic threshold somewhere. So the logic threshold 311 00:48:15,470 --> 00:48:22,470 at half you can say ideally logic threshold should be half vOH + vOL that would give you 312 00:48:29,099 --> 00:48:36,099 more or less symmetric margin. That is the logic swing what ever the logic swing is there 313 00:48:37,539 --> 00:48:44,539 it’s properly utilized to have almost equal noise margin low and noise margin high. So 314 00:48:47,359 --> 00:48:54,359 this is also very important from the point of view of characteristics. 315 00:48:54,819 --> 00:49:01,349 Finally the last point, the last characteristic which we have already pointed out is the fan 316 00:49:01,349 --> 00:49:08,349 out. The fan out is of a logic gate is the number of outputs you can connect from or 317 00:49:15,180 --> 00:49:21,690 the number of outputs or number of gates which it can drive basically. Suppose we have a 318 00:49:21,690 --> 00:49:28,690 NAND gate and we are connecting to large number of other gates. So this is the fan out, how 319 00:49:29,700 --> 00:49:36,700 many gates you are connecting to and this also there is a limit to it. So we shall take 320 00:49:37,230 --> 00:49:44,230 up that subsequently when we discuss the actual circuits. So there is a limit maximum limit 321 00:49:45,339 --> 00:49:51,640 for that. So that we hall next we shall take up actual circuits, start of with the actual 322 00:49:51,640 --> 00:49:58,640 logic circuits and discuss in terms of this characteristics which we have studied today.Thank 323 00:50:12,779 --> 00:50:19,779 you. 324