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Hello and welcome to today’s lecture on
static CMOS circuits; this is the first lecture
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on this topic. And in two lectures, I shall
cover different aspects of static CMOS circuits.
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In the last four lectures, I have discussed
about various aspects of MOS inverters, how
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different types of inverters can be realized,
their characteristics, static, dynamic and
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so on. And as I mentioned earlier, you are
following bottom of approach. So, starting
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with MOS transistor we have discussed MOS
inverters, now we are discussing more complex
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circuits realized using static CMOS circuits,
static CMOS technology.
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Here is the agenda after every introduction,
which will also include some recap of the
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previous lectures. I shall discuss about CMOS
multi-input gates; we shall see how multi-input
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gates can be realized by extending the idea
of MOS inverters. Then we shall discuss transfer
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characteristics of NAND and NOR gates, and
after that we shall discuss switching characteristics
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of NAND and NOR gates. And finally, we shall
compare the characteristics of NAND and NOR
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gates realized using static CMOS technology.
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Here is a brief recap about what we discussed
in my last four lectures, we have discussed
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about different types of inverters, that can
be realized by using MOS technology we have
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seen pull-down device is always in MOS transistor,
but pull-up device can vary it can be a passive
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resistor, or it can be some active devices
particularly nMOS depletion transistor nMOS
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enhancement transistor pseudo-n MOS circuit,
where a pMOS transistor is used as pull-up
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and also in CMOS a pMOS transistor is used
as pull-up. And we have seen except for CMOS
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where the low level is strong for all the
other cases we have seen the low level is
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weak and as a consequence the noise margin
will be poorer; that means, the noise margin
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a low in m L will be weak poor for all these
inverter configurations.
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On the other hand we find that only for nMOS
enhancement transistor the high level is weak
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for all other cases high level is strong.
So, noise margin for nMOS enhancement type
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pull-up device is inferior, and as a consequence
nMOS enhancement type transistor is never
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used in realizing inverters and other types
of circuits. So, but we find that in terms
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of all these features noise margin it is good
for CMOS power dissipation is also low, and
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and also the low and high levels are strong.
As a consequence the CMOS is the choice of
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present day VLSI circuits and that is a technology
that is used for realizing present day MOS
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circuits VLSI circuits. So, henceforth we
shall continue our discussion primarily on
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CMOS
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And we shall see in this lecture, how different
types of gates particularly NAND and NOR gates
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can be realized by extending the basic concept
of CMOS inverter, and we shall see; that means,
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whenever we are making it NAND or NOR gate
essentially we are increasing fan-in I shall
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elaborate about it what is fan-in and how
the transfer characteristic is affected by
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fan-in that we shall discuss in detail. Then
I shall also see we shall also discuss about
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the impact of fan-in on the noise margin,
because fan-in affects the noise margin that
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we shall see. Then how switching characteristic
is affected by fan-in and fan-out that also,
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we shall discuss finally, we shall end our
lecture by comparing NAND and NOR gate realizations
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their compare that various characteristics.
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First let us focus on fan-in and fan-out.
So, let us consider what is fan-in fan-in
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fan is essentially the number of number of
inputs.
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That can be applied to a gate without affecting
its operation; that means, it should behave
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like a gate switching device you know that
is. So, produce high level output low level
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output and the fan is essentially is number
of inputs. So, let us consider different types
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of gates first let us consider NAND gate.
NAND gate NAND 2 where we have got two inputs.
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So, here fan-in is two. So, NAND two fan-in
is two then we can have four input NAND gate
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NAND four where the number of inputs is 1,
2, 3, 4 and you can have NAND 4 fan-in is
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equal to 4 you can also have say NAND 6 where
the number of inputs is 6, 1, 2, 3, 4, 5 and
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6. So, here for NAND 6 fan-in is 6. So, see
we can fan-in is essentially the number of
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inputs similarly, we can have NOR gates 2
input NOR gate NOR 2 NOR 2 again will have
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fan-in of 2 NOR 4 will have fan-in of 4 4
input NOR gate will have fan-in of 4 similarly,
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you can have say NOR 6, 1, 2, 3, 4, 5, 6.
So, NOR 6 and NOR 6 will have fan-in of 6.
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So, not only NAND and NOR gates are used other
types of gates are also there for example,
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and gate or gate excusive or gate. So, these
gates are also used and which are considered
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to be part of the standard say library, but
we are discussing the characteristics of NAND
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and NOR gates primarily, because it is very
natural to realize NAND and NOR gates by using
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MOS technology. The other gates can be realized
using NAND and NOR gates later on we shall
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discuss about that. So, here is the concept
of fan-in. Now let us consider the concept
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of fan-out what do you really mean by fan-out.
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So, fan-out fan-out is essentially the number
of gates the a particular gate is driving
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for example, this inverter may be driving
several gate say it can drive only one gate
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it is going to one input of a NOR gate. So,
in this case fan-out is equal to is one or
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it can drive more than one gate say, it is
driving an inverter as well as it is driving
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one NAND gate. So, in this case the fan-out
is equal to 2 similarly, it can drive a several
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gates for example, an inverter a NAND gate
or it can drive it a NOR gate and different
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types of gates. So, fan-out in general fan-out
in this particular case 1, 2, 3. So, fan-out
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is equal to three. So, if it goes to other
more number of gates fan-out will be more.
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So, whenever we add more and more gates at
the output where particular gate, we have
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to see that performance of the circuit is
not degraded and also the correct correct
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output is produced. So that that will be our
study how fan-in and fan-out affects a particular
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circuit. For example, when we are extending
the basic concept of inverter and inverter
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can be considered as a fan-out fan-in having
fan-in is equal to 1. So, inverter is essentially
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a gate having fan-in is equal to 1, but other
types of gates with 2 input 3 or 4 input have
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fan fan-in of more than 1. And how whenever
you add more number of inputs, how the circuit
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behavior is changing that we shall discus
in terms of transfer characteristics switching
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characteristics noise margin and so on.
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So, after discussing fan-in and fan-out let
us consider a basic realization of a NOR gate
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or NAND gate let us start with NAND gate NAND
gate.
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So, a NAND function let us consider two input
NAND function NAND 2. So, it has got let us
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assume 2 inputs A and B and it produces say
output V or we can say V is produces V out.
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As you know it for 2 inputs there are four
possible combinations, that you can apply
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to the gate 10 0 0 1 1 0 1 1 and sorry in
this case the output for NAND gate will be
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whenever both of them are one only then it
is 0 for all other cases it is one this is
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how it can be realized. Now how you can realize
a NAND 2 gate NAND 2 gates can be very easily
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realized by having 2 nMOS transistors in series.
And connecting it to ground, because you know
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as we know the role of the nMOS transistors
nMOS transistor network is to pull down the
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output to low level and when in this particular
case is pulling down when both of them are
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1, as you can see when both of them are 1
this C L can be pulled down.
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Now what is the role of the pMOS transistor
is to produce 1; that means, role of nMOS
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network is to produce 0 and the role of the
pMOS network is to produce 1. So, you can
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see here the 1 is produced when any of the
input is 0. So, that can be realized by having
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two pMOS transistor in parallel. So, whenever
any of them is 0 as per this then this Vdd
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will be connected to this I mean, apply to
this load resistance and it will be charged
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to high level. So, it will become 1. So, this
is how you can realize a 2 input NAND gate
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and in this way you can extend this concept
to realize say n-input NAND gate. So, an n-input
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NAND gate will have n pMOS transistors n pMOS
transistors in parallel and nMOS transistors
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in series we can see here. So, this is connected
to ground this is connected to Vdd. So, you
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can say this is input 1, this is input 2,
this is input n similarly, this is input 1
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this is input 2 this is input n and output
is taken from here V out. So, this is the
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general structure of a n-input NAND gate where
we have got n pMOS transistors in parallel
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connected to Vdd and nMOS transistors in series
which are which is connected to ground. So,
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this is how you can realize a n-input NAND
gate.
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And similarly, you can have n-input NOR gate
realization. So, you can also realize n-input
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NAND gate, but NOR gate, but before we do
that we shall study the characteristics the
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characteristics of this n-input NAND gate;
that means, whenever you add more than one
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input; that means, whenever it is become multi-input
means, input is 2, 3, 4 then how the transfer
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characteristic is affected that we shall discuss.
So, here as you can see there are n transistors
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in parallel here n transistors in series.
Now, this can be simplified you can consider
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it. As if all the n pMOS transistors are tied
together gates are tied together and it is
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represented by single pMOS transistor similarly,
all the gates are of the nMOS transistors
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are tied together, and it is represented by
a single nMOS transistor. And then you have
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connected it to V in and here it produces
V out. How the L by W ratio is affected I
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mean, is changed whenever you convert it into
a single inverter by tying all the inputs
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together; that means, 1 to n all are tied
together and then it behaves as if it is an
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inverter. So, in that case we shall see how
the transfer characteristic is affected
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So, here as you can see since n pMOS transistors
in parallel, as if n resistors are in parallel.
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So, there or you can say that the you know
that W their widths are tied are parallel.
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And So, the W by L ratio will be n W p and
L p similarly, L by W ratio of this particular
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transistor will be equal to that W n will
not change, but the length will change, because
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you can see these are in series as if you
have connected n series n transistors in series.
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So, they are lengths are tied together to
form n L n they are in series. So, L by W
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w by L ratio for this particular inverter
which are essentially realized by tying all
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the inputs together we get this.
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Now, what is the expression for that switching
point inverter switching point? We know that
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inverter switching point or inverter threshold
voltage in that particular case, what is the
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expression for that V s p switching point
of inverter. We know that that expression
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is Vdd plus V t p where V t p is the threshold
voltage of the pMOS transistor, plus V t n
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by n root beta n by beta p by 1 plus 1 by
sorry in particular for inverter this n will
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not be there. So, it will be one plus root
beta n by beta p. So, we find this is the
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case of an for simple inverter where you have
got only 1 nMOS transistor, pMOS transistor
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and 1 nMOS transistor, but in this case in
case of n-input NAND gate we have connected
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n transistors in parallel for the pMOS network,
and n transistors in series how they are beta
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n by beta p is affected. You have already
seen they are the ratio will be affected in
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this way n W p L p width of the pMOS transistor
is increased, and length of the nMOS transistor
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is increased.
So, this if we substitute then for a the switching
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point V inverter switching point will be equal
to Vdd plus V t p this part is not affected,
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but beta n by beta p sorry beta n by it will
be beta p beta n by beta p that ratio is affected.
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And since the length of the this W by L in
this particular case, it is in the L that
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L is increased and here, W is increased W
p is increased. And as a consequence it will
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be equal to V t n root 1 by n square beta
n and beta p that corresponds to an inverter.
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Similarly, here it will be 1 plus root 1 by
n square into beta n by beta p. So, if we
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simplify this will be equal to Vdd plus V
t p plus V t n by n root beta n by beta p
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and at the denominator it will have 1 plus
1 by n root beta n by beta p.
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Now, if we plot this is this is this is not
this is the case not for inverter for NAND
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gate for n-input NAND gate. So, this is V
SP NAND that was the case for inverter how
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it is affected. So, if the switching point
of an if we consider the switching point of
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an inverter in what direction it will go.
So, let me plot the transfer characteristic
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here. So, this is the transfer characteristic
let us assume this is your V out and this
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is V in and let us assume this is the transfer
characteristic for inverter. And here as you
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can see this value as n increases in the denominator
this is 1 by n beta n by beta p into 1 by
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n. So, value of the denominator will increase,
and as a consequence this will move in this
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direction. So, for higher n as increases the
switching point will move towards right towards
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Vdd. So, later on we should see how much it
is increased for different values of n, but
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for the time being we can say that for a NAND
gate, this switching point moves toward Vdd.
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Whatever is the inversion inverter switching
point from that that NAND switching point
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NAND gate switching point will move towards.
So, this will indeed affect the noise margin,
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because ideally it should be at Vdd by 2,
but if it moves towards right then the noise
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margin of high level will degrade, and if
it moves in the left direction then noise
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margin of the low level noise margin will
be affected, but for the time being we find
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that for NAND gate n as n is input the inversion
point moves towards right and as a consequence
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the noise margin will be affected
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Now, let us consider a NOR gate in a similar
manner. So, a NOR gate what is the realization
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by extending the same concept of NAND gate
a NOR gate as you know if we real show the
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function if we it has got 2 inputs.
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So, 0 0 0 1 1 0 and 1 1 and V out for NOR
gate when it will be 1 it will be 1 for as
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you know for or gate the for these three output
is 1. So, in this case this will be 0 and
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only for 0 0 outputs will be 1 that will be
the case for NOR gate. So, how that can be
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realized? So, when both of them are 0 then
output is 1 so that means, what you have to
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do we have to put 2 2 pMOS transistor in series.
So, when both of them are 0 then this path
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is closed. So, we shall get one at the output
and what about the NAND gate network as you
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can see when when any of them any any of the
input is 1 then output is 0. So, that can
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be very easily implemented by having 2 nMOS
transistors in parallel and connecting the
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source of them to ground. So, this is here
it is a, and here it is b. So, this is how
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a 2 input NOR gate can be realized and the
idea can be extended to realize a n-input
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NOR gate.
So, an n-input NOR gate will be having n pMOS
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transistor in series. So, 1 2 n and
nMOS transistor in parallel in this case.
So, 1 2 n, so n nMOS transistors in parallel
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and the source the common this all the resource
points will be connected to the ground and
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the that series connected pMOS transistor
is connected to Vdd this is how a n-input
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NOR gate is realized.
Now, in this particular case what is the value
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of this V switching point NOR for n-input
NOR gate. In this particular case we find
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that this the value of the trans conductance
ratio that beta n by beta p is equal to that
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trans conductance ratio
trans conductance ratio is equal to n square
beta n by beta p, because in this particular
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case as if n MOS pMOS transistors in series;
that means, there width will be in series;
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that means, their length will increase for
the pMOS transistor and width of the nMOS
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00:26:04,429 --> 00:26:08,130
transistor will increase, and that is the
reason why it is n square beta n by beta p.
187
00:26:08,130 --> 00:26:15,130
So, the V switching point for the inverter
will be equal to V t n plus V t p this part
188
00:26:16,650 --> 00:26:23,650
remaining same here, it will be n root beta
n by beta p. And in the denominator it will
189
00:26:26,370 --> 00:26:33,370
have V t n plus V t p plus n root sorry it
will be 1 plus n root beta n by beta p. So,
190
00:26:43,140 --> 00:26:50,140
if you plot this what you find that the denominator
value since n is here as n increases the denominator
191
00:26:50,380 --> 00:26:56,770
value increases.
So, for an inverter if the transfer characteristic
192
00:26:56,770 --> 00:27:03,770
is somewhat like this, this neither is for
an inverter for NOR gate it will move towards
193
00:27:04,500 --> 00:27:11,500
left, because in the denominator value is
increasing and this part is actually will
194
00:27:11,659 --> 00:27:18,659
be smaller than this. So, it will move towards
as n increases, the inverter inverter switching
195
00:27:23,039 --> 00:27:26,330
point will move towards left.
196
00:27:26,330 --> 00:27:33,330
Now, let us consider the noise margin of the
for the 2 cases noise margin. How noise margin
197
00:27:44,770 --> 00:27:51,480
is affected as we know ideally the transfer
characteristic should be like this, the switching
198
00:27:51,480 --> 00:27:58,480
point is at Vdd by 2 and this is Vdd and this
is your V out, earlier by wrongly I have written
199
00:28:04,299 --> 00:28:11,299
V out it V in. So, V in again as V v output
plot is done and the if the if the switching
200
00:28:12,870 --> 00:28:19,870
is done in the middle then noise margin noise
margin low will be equal to noise margin high
201
00:28:21,230 --> 00:28:28,230
is equal to Vdd by 2, but if it moves towards
right then the noise margin high will decrease,
202
00:28:29,330 --> 00:28:35,250
if it moves if the switching point moves towards
left then the noise margin low will decrease.
203
00:28:35,250 --> 00:28:42,250
Now let us plot the let us find out the value
of the switching point for different values
204
00:28:44,159 --> 00:28:51,159
of n and other parameters.
Let us assume Vdd is equal to 5 volt then
205
00:28:55,080 --> 00:29:02,080
V t n is equal to absolute value of V t p
is equal to 1 volt, because V t p will be
206
00:29:03,400 --> 00:29:08,960
is equal to minus 1. So, you have taken the
absolute value and also let’s assume W p
207
00:29:08,960 --> 00:29:15,960
is equal to W n is equal to, L p is equal
to L n. So, here we are assuming the width
208
00:29:17,400 --> 00:29:24,400
and length all are same in such a case for
fan-in fan-in is equal to 1 that is the case
209
00:29:28,059 --> 00:29:34,630
of inverter; that means, this is a case of
an inverter. What is the switching point the
210
00:29:34,630 --> 00:29:41,630
switching point will be equal to 2.10 volt
2.10 volt for the inverter switching point.
211
00:29:43,580 --> 00:29:50,580
So, how you are getting it actually V switching
point inverter as you know is equal to V Vdd
212
00:29:56,190 --> 00:30:03,190
plus V t p plus root of beta n by beta p into
V t n by 1 plus root beta n by beta p.
213
00:30:11,610 --> 00:30:18,610
So, in this particular case what will happen
this V t p Vdd is 5 V t p is 1. So, V t Vdd
214
00:30:21,320 --> 00:30:28,320
minus it means, that will be 1 this will be
equal to 5 minus 1 plus 1 plus root beta n
215
00:30:30,440 --> 00:30:37,440
by beta p will be equal to 3 by 1. And similarly,
this will be also equal to 1 plus root 3.
216
00:30:37,730 --> 00:30:44,730
So, if you simplify it you will get 2.10.
Now, so whenever we are concerning inverter
217
00:30:46,919 --> 00:30:52,029
there is no difference between NAND gate and
NOR gate these are essentially same. Now let
218
00:30:52,029 --> 00:30:57,220
us consider fan-in of two in that case for
NAND gate as we know it will move towards
219
00:30:57,220 --> 00:31:02,770
right for NOR gate for NAND gate, and for
NOR gate it will move towards left. So, this
220
00:31:02,770 --> 00:31:08,539
becomes 2.60 volt it is moving towards right
it is increasing on the other hand it will
221
00:31:08,539 --> 00:31:15,539
be not 1.67 for NOR gate.
So, we can see it is decreasing this is increasing
222
00:31:15,570 --> 00:31:22,570
for 3 input NAND and NOR gate the corresponding
values are 2.90 and 1.48 and for 4 input the
223
00:31:26,149 --> 00:31:33,149
value will be 3.09 and 1.38. So, what we are
observing is that since it is starting with
224
00:31:36,240 --> 00:31:43,070
lower value then the midpoint by increasing
it is becoming closer to the midpoint then
225
00:31:43,070 --> 00:31:48,919
of course, it is increasing, but noise margin
is definitely better for NAND gate than NOR
226
00:31:48,919 --> 00:31:55,919
gate, because in this particular case we see,
the low that n m L noise margin low is very
227
00:31:56,399 --> 00:32:03,399
bad I mean, instead of 2.5 it is 1.38, but
here it is not that much affected it is affected
228
00:32:06,309 --> 00:32:13,309
definitely, but you can see whenever the fan-in
is 2 or 3 then it is very close to the middle
229
00:32:13,789 --> 00:32:20,789
there is small difference. So, noise margin
low noise margin low or high is not affected
230
00:32:21,380 --> 00:32:27,299
much. So, in other words the noise margin
of a NAND gate, is less affected than the
231
00:32:27,299 --> 00:32:32,309
noise margin of a NOR gate whenever you increase
the fan-in.
232
00:32:32,309 --> 00:32:39,309
So, with this conclusion in mind let us now
move to discuss about the switching characteristics.
233
00:32:40,760 --> 00:32:47,760
So, whenever we consider the switching characteristics,
the figure shows n pull-up pMOS transistors
234
00:32:49,370 --> 00:32:55,529
with their gates tied together along with
a load capacitance C l. So, for the sake sake
235
00:32:55,529 --> 00:33:02,529
of simplicity what we have assume, as if all
the NOR gates are tied together pMOS transistors
236
00:33:03,470 --> 00:33:10,470
are tied together, that is the difficult NAND
configuration and this is connected to C L.
237
00:33:10,590 --> 00:33:17,419
So, in this particular case the equivalent
circuit for NAND gate will be pMOS network
238
00:33:17,419 --> 00:33:24,419
for NAND gate n-input NAND gate will be as
if R P and there is a switch and a capacitor
239
00:33:34,190 --> 00:33:41,190
that is your C out p and we can have we have
such n such transistors. So, R P a switch
240
00:33:46,419 --> 00:33:53,220
representing the transistor depending on or
off this will be closed or not closed, and
241
00:33:53,220 --> 00:34:00,220
again you have got C out p these are tied
together. And in this way there will be n
242
00:34:02,159 --> 00:34:09,159
such resistors and capacitors which are in
parallel and for then. So, far as the resistance
243
00:34:09,399 --> 00:34:15,720
is concerned they are in series with the resistor
I mean, a switch is there in series and capacitor
244
00:34:15,720 --> 00:34:22,720
is connected and this is connected to the
load capacitance C L. So, considering this,
245
00:34:24,579 --> 00:34:31,579
the t d r rise time time delay rise time will
be equal to it can be derived R n R P this
246
00:34:33,479 --> 00:34:38,059
is your R P recharging through R P this is
connected to Vdd. So, it will charge through
247
00:34:38,059 --> 00:34:41,249
r p. So, rise time will be dependent on R
P C output.
248
00:34:41,249 --> 00:34:48,249
So, it can be derived that is equal to R P
by n into n C out p plus R P by n C L. So,
249
00:34:58,069 --> 00:35:04,640
we find that has got 2 components, the first
component is essentially for charging different
250
00:35:04,640 --> 00:35:11,640
output capacitances. And this the second term
is essentially to charge the load capacitance.
251
00:35:14,180 --> 00:35:20,799
And this particular verification you will
find in this reference CMOS circuit design
252
00:35:20,799 --> 00:35:27,799
layout and simulation by baker and Boyce published
by prentice-hall of India. So, this is the
253
00:35:31,349 --> 00:35:38,349
case for charging the capacitor. So, t d r
what about the t d f fault time; so to do
254
00:35:42,140 --> 00:35:49,140
that what we can say that as if n transistors
are in series. So, we can say that this is
255
00:35:51,469 --> 00:35:58,469
your load connected then we have got n transistors
in series. So, and gate is the input is connected
256
00:36:04,969 --> 00:36:11,969
here, and another transistor again input is
connected here. So, in this way you have got
257
00:36:12,519 --> 00:36:19,519
n pMOS nMOS transistors in series. So, representing
R n r n these capacitors are C out n C out
258
00:36:24,359 --> 00:36:31,359
n C out n minus 1 and finally, you will be
having another resistor and capacitor C out
259
00:36:36,869 --> 00:36:43,390
1 R n and a capacitor connected here this
is connected to ground. So, these inputs are
260
00:36:43,390 --> 00:36:50,099
tied together and here you are applying V
in and this is your load capacitance.
261
00:36:50,099 --> 00:36:56,130
So, the discharging take place through this
path and input is applied through these capacitances.
262
00:36:56,130 --> 00:37:03,130
As you know you are applying it to the gate,
and that is being represented by C in n minus
263
00:37:03,609 --> 00:37:10,609
1 and this is C in n and this is C in 1. So,
it is applied to the gate and these are the
264
00:37:10,650 --> 00:37:17,650
capacitances of the gate which is represented
and these are the output capacitances. And
265
00:37:17,719 --> 00:37:24,719
the expression for t d f t d f will be equal
to, n R n C out n by n plus C load these are
266
00:37:34,339 --> 00:37:39,630
essentially to charge the load capacitance,
and the output capacitances which are in series
267
00:37:39,630 --> 00:37:43,819
since they are in series they that is the
capacitance value equivalent capacitance is
268
00:37:43,819 --> 00:37:50,819
C out n by n. And another term will be there
that is for charging these input capacitances.
269
00:37:51,599 --> 00:37:58,599
So, this this value is 0.35 R n C in n and
n minus 1 square. So, these are this is the
270
00:38:04,160 --> 00:38:10,869
expression again this has been taken from
this reference CMOS circuit design. So, the
271
00:38:10,869 --> 00:38:15,239
rise time and fall time can be represented
by these expressions.
272
00:38:15,239 --> 00:38:22,239
Now, when the value of C L is large then other
factors can be neglected. So, t d r will become
273
00:38:23,229 --> 00:38:30,229
equal to this part R P by n into C L. And
of course, in the worst case when only 1 transistor
274
00:38:32,529 --> 00:38:38,700
is on remaining transistors is off this will
be equal to R P into C L similarly, the t
275
00:38:38,700 --> 00:38:45,700
d f will be will be equal to n R n C load
the other factors can be neglected when n
276
00:38:46,849 --> 00:38:48,819
is very large.
277
00:38:48,819 --> 00:38:55,819
Now, let us focus on the NOR gate in a similar,
way we can derive expressions for NOR gate.
278
00:38:58,709 --> 00:39:05,709
And this is the summary of the switching characteristics
of the NAND and NOR gates. So, t d r for NAND
279
00:39:05,940 --> 00:39:12,940
gate is equal to R P by n into n C out p plus
C out n by n plus C load. So, here not only
280
00:39:15,099 --> 00:39:20,059
output capacitance I mean, for the pMOS transistors
output capacitance of the nMOS transistor
281
00:39:20,059 --> 00:39:27,059
has also been taken into consideration. So,
we find that as the fan-in is increased this
282
00:39:30,579 --> 00:39:37,579
rise time will also increase; however, worst
case rise time will be equal to R P into C
283
00:39:41,910 --> 00:39:48,910
out p plus C out n plus C L only when 1 transistor
is on; that means, although n pMOS transistors
284
00:39:51,450 --> 00:39:57,369
are in parallel in the worst case the delay
with the rise time will maximum only only
285
00:39:57,369 --> 00:40:04,369
when 1 of them is on similarly, the fall time
is n R n into C out n by n plus n C out p
286
00:40:05,569 --> 00:40:11,209
plus C L.
And again in this case when the and also that
287
00:40:11,209 --> 00:40:16,819
expression for charging the input capacitance
is given here this is the expression. And
288
00:40:16,819 --> 00:40:23,819
when C L is large the t d f is equal to n
R n C L and t d r is equal to R P CL. So,
289
00:40:26,819 --> 00:40:33,089
here we find that the fall time for the NAND
gate is affected and it increases linearly
290
00:40:33,089 --> 00:40:40,089
with the value of n for large. And the rise
time is not affected much it is very it is
291
00:40:41,079 --> 00:40:47,519
very similar to that of an inverter.
Similarly, for the NOR gate we find that t
292
00:40:47,519 --> 00:40:54,519
d f is equal to R n by n into n C out p plus
C L in this case you know p n pMOS transistor
293
00:40:55,589 --> 00:41:02,589
are in series that is the reason why the fall
time will not be affected much and in for
294
00:41:03,940 --> 00:41:09,269
n is equal to I mean when only when one of
the transistors is on then it will be equal
295
00:41:09,269 --> 00:41:16,269
to R n C L R n C L as you can see; however,
the rise time will be affected with the value
296
00:41:16,380 --> 00:41:23,380
of n it. So, t d r is equal to n R P C l.
So, for large C L load capacitance it will
297
00:41:25,160 --> 00:41:32,160
be proportional to the fan-out is affected
by the I mean, the for delay that t d r will
298
00:41:33,109 --> 00:41:37,359
be affected by the number of inputs so n R
P C L.
299
00:41:37,359 --> 00:41:44,359
So, this is how the delay times are affected,
because of fan-in is demonstrated not only
300
00:41:44,359 --> 00:41:50,509
fan-in, but also it shows it is proportional
to C L; that means, the delay characteristics
301
00:41:50,509 --> 00:41:55,509
switching characteristics is affected not
only by fan-in, but also by the fan-out or
302
00:41:55,509 --> 00:42:02,229
load capacitance. You see whenever the fan-out
is increased essentially the load capacitance
303
00:42:02,229 --> 00:42:03,269
increases.
304
00:42:03,269 --> 00:42:10,269
So, here is the comparison of different parameters.
We find that the area increases linearly with
305
00:42:13,829 --> 00:42:20,759
increase in fan-in for both the gates. That
you have already seen, because we are increasing
306
00:42:20,759 --> 00:42:27,759
the number of transistors we have seen that
as the fan is in increased the number of transistors
307
00:42:28,809 --> 00:42:35,739
is increased, for 2 input it becomes double
that of an inverter and for n-input there
308
00:42:35,739 --> 00:42:42,739
are n pMOS and nMOS transistor. So, area increases
linearly as the value of n increases. What
309
00:42:44,369 --> 00:42:50,170
about noise margin for equal fan-in noise
margin is better for NAND gates neither compared
310
00:42:50,170 --> 00:42:56,819
to NOR gates. That you have already seen how
the noise margin is affected based on this
311
00:42:56,819 --> 00:43:03,819
particular table particularly, we find that
the noise margin is I mean; good I mean neither
312
00:43:05,289 --> 00:43:11,680
is better for NAND gate compared to NOR gate
for equal area. So, in that particular case
313
00:43:11,680 --> 00:43:17,670
we considered minimum area.
What about delay increases linearly with increase
314
00:43:17,670 --> 00:43:24,670
in fan-in and fan-out? And particularly for
NAND gate and NOR gate with respect to the
315
00:43:24,869 --> 00:43:31,869
inverter it is proportional to n, Where n
is the fan-in of any NAND or gate NAND or
316
00:43:32,170 --> 00:43:39,170
NOR gate in addition to that that. So, n is
the fan-in it has it has dependence on fan-out
317
00:43:42,819 --> 00:43:49,819
as well and that is the reason why the number
of fan is restricted to 4 although gates are
318
00:43:51,400 --> 00:43:58,400
available with fan-in starting from 2 to may
be 8, but whenever you realize practical VLSI
319
00:44:00,819 --> 00:44:07,079
circuits of reasonable performance then, fan
there is some restriction on the fan-in is
320
00:44:07,079 --> 00:44:13,930
usually restricted to 4; that means, whenever
you will choose standard gates from the library
321
00:44:13,930 --> 00:44:19,499
you will choose gates with fan-in less than
equal to 4.
322
00:44:19,499 --> 00:44:25,430
And you will realize multi-level circuits
using gates with fan-out fan-in is equal to
323
00:44:25,430 --> 00:44:32,430
2 or 3 or 4 not more than 4. So, what neither
is the conclusion conclusion neither is that
324
00:44:32,599 --> 00:44:39,599
for equal area design NAND gates are faster
and better alternative to NOR gates. So, this
325
00:44:40,489 --> 00:44:47,489
is the conclusion that we can make from the
comparison of area noise delay and other parameters.
326
00:44:49,509 --> 00:44:56,509
So, here is the summary of different types
of whatever we have discussed today. So, multi-input
327
00:45:00,440 --> 00:45:07,440
NAND and NOR gates are extension of basics
CMOS inverter we have discussed. How the how
328
00:45:09,890 --> 00:45:15,619
the multi-input NAND and NOR gates can be
realized by extending the basic concept of
329
00:45:15,619 --> 00:45:22,619
an inverter, by adding more and more number
of transistors as the fan-in increases. And
330
00:45:23,039 --> 00:45:30,039
we have seen the transfer characteristic does
not remain symmetric with fan-in. So, transfer
331
00:45:30,959 --> 00:45:37,160
characteristic is affected with the fan-in
that we have discussed in detail. Now for
332
00:45:37,160 --> 00:45:42,789
the second third conclusion is for the same
area NAND gates are superior to NOR in switching
333
00:45:42,789 --> 00:45:49,789
characteristic, another very interesting point
that we can consider we have seen that the
334
00:45:51,630 --> 00:45:58,630
switching characteristics is becoming asymmetrical
as the fan-in is increased.
335
00:45:58,890 --> 00:46:05,890
But if we consider say fan-in is equal to
3 let us consider a NAND NOR NAND gate. In
336
00:46:09,449 --> 00:46:16,449
case of NAND gate we know that we have 3 pMOS
transistors in parallel and three nMOS transistors
337
00:46:23,819 --> 00:46:30,819
in series. Now in this particular case if
we consider minimum size minimum size then;
338
00:46:41,329 --> 00:46:48,329
that means, W L is equal to W n is equal to
L n is equal to W p is equal to L p. So, in
339
00:46:53,609 --> 00:47:00,609
such a case what will be the switching characteristics
of this particularly the beta n by beta p
340
00:47:03,249 --> 00:47:10,249
ratio in this particular case, will be equal
to how much. As we know since they are of
341
00:47:10,979 --> 00:47:17,979
the same length and width, we know that for
n for n for a for this particular configuration
342
00:47:21,829 --> 00:47:28,719
beta n by beta p corresponding the equivalent
beta n by beta p will be is equal to 1 by
343
00:47:28,719 --> 00:47:35,269
n. What is n n is the number of inputs in
this case.
344
00:47:35,269 --> 00:47:42,269
Now, we know that beta n by beta p these value
is also 3 in this case n is also 3; that means,
345
00:47:42,999 --> 00:47:49,999
we can say this the this trans conductance
ratio
is equal to 1, because beta n by beta p is
346
00:47:59,660 --> 00:48:06,660
equal to 3 and n is also 3. So, this makes
it 1 so that means, for a 3 input NAND gate
347
00:48:08,099 --> 00:48:15,099
the inverters the switching point will be
exactly at Vdd by 2, because the equivalent
348
00:48:15,749 --> 00:48:21,349
beta n by beta p trans conductance ratio beta
n by beta p is equal to one we know that when
349
00:48:21,349 --> 00:48:28,349
this is 1 then the beta the V s p say NAND
3 will be equal to Vdd by 2.
350
00:48:34,209 --> 00:48:41,209
The reason for that is denominator will become
1 plus 1 and also numerator will be the t
351
00:48:42,709 --> 00:48:49,130
p and t n will cancel it will be Vdd. So,
it will be Vdd by 2. So, we find that for
352
00:48:49,130 --> 00:48:55,019
this particular case it is becoming perfectly
symmetric, but that will not be situation
353
00:48:55,019 --> 00:49:01,599
for NOR gate. And that is the reason why our
conclusion is for the same area NAND gates
354
00:49:01,599 --> 00:49:08,599
are superior for NOR gates in switching characteristic
particularly, the fan-in is the noise margin
355
00:49:10,410 --> 00:49:17,349
is better. And also for the same delay NAND
gates requires lesser area than NOR gates.
356
00:49:17,349 --> 00:49:24,349
We know that if we want to have the rise time
and fall time identical, then the W p has
357
00:49:28,140 --> 00:49:35,140
to be 3 times that of W n. So, this is the
requirement this is the requirement for equal
358
00:49:36,699 --> 00:49:43,699
rise and fall time. So, t d r is equal to
t d f if we want this then this is the requirement.
359
00:49:45,150 --> 00:49:51,559
So, in such a case the area increases that
is the reason why we can say that for the
360
00:49:51,559 --> 00:49:58,279
same delay NOR gates require lesser area than
NOR gate NOR gates and for the same area NAND
361
00:49:58,279 --> 00:50:04,369
gates are superior to NOR gates in switching
characteristics. The noise margin and switching
362
00:50:04,369 --> 00:50:08,529
characteristics are better for NAND gates
compared to NOR gates that we have already
363
00:50:08,529 --> 00:50:13,939
discussed in detail and NAND gates are better
alternative to NOR gates.
364
00:50:13,939 --> 00:50:18,089
From all these discussion this neither is
our conclusion NOR gates are better alternative
365
00:50:18,089 --> 00:50:25,089
to NOR gates. So, although this is our conclusion
from the by considering the noise margin,
366
00:50:27,339 --> 00:50:34,339
delay characteristics, area NAND gates are
superior, but in practice we shall be using
367
00:50:35,199 --> 00:50:42,199
both NAND and NOR gates together. So, you
will see that whenever you are you will be
368
00:50:43,670 --> 00:50:50,670
realizing multi-input, multi-out multi multi-level
gates, multi-level circuits, multi-level multi-input
369
00:50:51,890 --> 00:50:57,160
circuits. Then you will find that we shall
be using both NAND and NOR gates, because
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in that case, overall area, overall delay
characteristics is important rather than individual
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area or delay characteristics.
So, our conclusion is that we shall be using
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both NAND NOR and other types of gates in
realizing circuits, but if possible, we shall
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choose NAND over NOR whenever it will be permitted
by by the realization technique. So, with
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this, we have come to the end of today’s
lecture; in the next lecture, we shall continue
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our discussion on the same topic that is your
static CMOS circuits, and we shall consider,
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how we can realize other types of gates and
more complex types of static CMOS gates thank
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you.