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Hello and welcome to today’s lecture on
MOS transistors. This is the fourth lecture
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on the low power VLSI circuits and systems
course and third lecture on MOS transistors.
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In the last lecture we have discussed how
the operation of a MOS transistor can be visualized
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with the help of a very interesting model
known as fluid model and fluid model as we
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have seen can be applied to charge controlled
devices including MOS transistors. There we
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have seen how the MOS transistor operates
and how the the current flow through the channel
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between the source and drain can be controlled
with the help of gate voltage and also the
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drain voltage. And we have seen that there
are three modes of operation.
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One is the accumulation mode, another is the
linear mode and third one is the saturation
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mode. And based on that the characteristic
of MOS transistors can be divided into three
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regions as you have seen cut-off cut-off region,
linear region, linear or active or you know
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that that partially charge controlled device.
That means, partially that that is actually
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called when the inversion region is partial,
weak inversion region and then the strong
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inversion region is represented by saturation
region rather weak strong inversion mode is
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represented by saturation region.
And today I shall discuss the electrical characteristics
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of MOS transistors.
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And here is the agenda of today’s lecture
after a brief introduction I shall I shall
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show once again the structural view of a MOS
transistor and which I shall use to explain
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the operation and also derive expression for
MOS, the the the drain current and particularly
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which is known as the electrical characteristics
of MOS transistor.
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Then, I shall discuss some about some of the
important parameters like threshold voltage
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and another related subject related topic
is body effect and we shall see how this how
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the substrate voltage can be changed to change
the threshold voltage with the help of body
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effect. Then, another important phenomenon
is known as channel length modulation I shall
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discuss about that and finally, I shall discuss
about transistor trans-conductance.
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So, here is the introduction as I have already
mentioned the drain current IDS depends on
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two variable parameters; the gate-to-source
voltage V g s and drain-to-source voltage.
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Of course, here I did not mention about another
important electrical parameter. That is your
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body bias that is your body-to-drain body-to-source
voltage rather source-to-body voltage. That
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also affects the operation and with the help
of which the threshold voltage can be controlled.
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So, essentially three voltages; gate-to-source
voltage, drain-to-source voltage and the source-to-body
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voltage. These three voltages will control
the drain current.
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And as I have already mentioned there are
three regions of operation; the cut-off region
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and this is represented by the accumulation
mode where there is no effective flow of current
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between the source or drain source and drain.
And we have already seen in this mode actually
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gate voltage is less than the threshold voltage
and there is no channel formation. So, there
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is no inversion layer. So, there is no channel
through which current can flow. So, in this
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particular region there is no flow of current,
no effective flow of current between the source
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and drain.
Here I am telling effective flow. The reason
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for that is there is very small amount of
current that flows through the device. But,
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for all practical purposes we can neglect
it. That is why we are calling it effective
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flow of current I mean the no effective flow
of current. But, very small amount of current
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flows as we shall see that is represented
by the sub-threshold leakage current. Later
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on we shall discuss about it in more detail.
Then, we shall consider the non-saturated
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region. This is the so-called active linear
or weak inversion region as I have mentioned
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and here the drain current is dependent on
both the gate voltage and drain voltages.
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So, the the as we shall see the expression
for drain current will be dependent on both
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gate and drain voltages. Then the third region
which is represented by the saturation region;
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this is the so-called strong inversion region
where the drain current is dependent on the
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drain-to-source voltage. But, depends, but,
does not depend on the here there is a mistake
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does not depend on the gate voltage sorry
there is it does it is independent of the
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drain-to-source voltage, but, depends on the
gate voltage. That means, in the saturation
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region the drain current solely depends on
the gate voltage. It does not depend as we
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change the drain voltage as we shall see.
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So, these are the three different regions.
Now, I have already shown you this structural
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view in the last lecture and particularly
there are three important physical parameters.
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I am calling it physical because when you
do when you do the fabrication of a MOS transistor
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then you youyouyou will decide the length
of the channel, the width of the channel and
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thickness of the silicon dioxide. These three
are decided at the time of fabrication. So,
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these physical parameters will affect the
operation of a MOS transistor and obviously,
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the electrical characteristics of the MOS
transistor. So, we shall express the drain
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current in terms of these three physical parameters
L which is the length of the channel, W the
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width of the channel and D thickness of the
silicon dioxide layer.
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And as you can see on both sides of this channel
we have got the source. I mean the the the
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the diffusion regions, heavily diffusion regions
and here also we have got another diffusion
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region that is called as drain. So, you have
got source and drain and here is the gate
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on top of the silicon dioxide. We put polysilicon
layer to form the gate and we can take electrical
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connections from source gate and drain to
realize circuits. Later on we shall discuss
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about that.
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Coming to the electrical characteristics;
I shall try to derive the expression for drain
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current in the same line of the fluid model.
We have seen in the fluid model because of
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the voltage that we applied at the gate some
charge is induced. So, inversion layer is
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created. Charge of opposite polarity in case
of n MOS transistors it is the it is the electrons
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which are created and that charge can flow.
Rather current can flow between source and
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drain whenever you apply some voltage between
source and drain.
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So, charge is I mean that in weak, in the
inversion region is created because of the
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gate voltage that we apply. And then because
of that creation of charge a conducting path
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is obtained which is known as channel between
the source and drain and current will flow
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when you apply a voltage, you apply an electric
field between the source and drain by applying
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a voltage to the drain with respect to the
source.
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So, let me write down the drain current expression.
So, Ids drain-to-source current. So, Id s
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can be represented as charge induced in the
channel charge induced in the channel which
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you can call at I c rather Q c and that can
be divided by the electron transit time electron
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transit time transit time is t n. So, that
means, here as you can see not only creation
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of charge is important or formation of inversion
layer is is important; it is necessary that
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the electron will move from source to drain
as we apply a voltage electron will from from
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from one end source end to the drain end and
that will lead to a constant flow of current
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and as a consequence this electron transit
time is important. So, as you know that Q
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that charge that is accumulated in a parallel
plate capacitor is equal to c into V where
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C is the capacitance C is the capacitance
and as you have seen it can be consider as
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a parallel plate capacitor and V is the voltage
that is applied across the parallel plate
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capacitor.
And as you know this capacitance C is equal
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to epsilon V epsilon a, area of the plate
and the D thickness of the silicon dioxide
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layer. So, here epsilon is the permittivity
of the insulator permittivity permittivity
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of the insulator and this e will be equal
to you know in this case we shall be using
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silicon dioxide. So, epsilon o x is equal
to three point roughly approximately 3.9 epsilon
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0 where epsilon 0 is the permittivity of the
free space and this we shall use to represent
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the, to to find out the expression for the
current.
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Now, this is the expression for capacitance.
What about the electron transit time? T n
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t n will dependent on what what thing? First
of all it will depend on two things; number
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one is speed and second thing is the distance.
So, you can say that transit time t n will
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be equal to mu n into E d s. That means, mu
n is the mobility of electron mobility of
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electron. Here we are considering n MOS type
transistor. So, the charge carrier are electrons.
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That is why we are considering mobility of
electron and E d s is the, is a drain-to-source
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electric field. We shall find out what is
the drain-to-source electric field E d s it
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is dependent on what? It is dependent on the
voltage that we apply across the across the
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drain-to-source. So, the E d s will be equal
to V d s by length l. So, E d s by l.
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Now, based on this we can find out the the
electron transition time. So, electron transition
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time will be equal to.
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First of all let us find out the velocity
of electron tau n. Tau n is equal to mu n
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V d s by l and therefore, t n electron transition
time, this is the velocity of electron
and t n will be equal to electron transition
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time that will be equal to l by tau n, length
by tau n that will be equal to l square mu
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n by V d s. So, we have got the the expression
for the electron transition time and and it
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has been found that typical value typical
value of mu n mu n that is the mobility of
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electron is equal to 650 centimeter square
by volt and that is at room temperature.
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So, we have got the expression, we have got
the the value the the charge that we can obtain
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by C into V and we can we have, also found
out the electron transition time t. Now, we
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can find out the current I d s now to do that
we shall divide the entire region into three
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parts as we have seen. Number one is cut-off
region when the voltage is less than the threshold
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voltage, there is no channel formation. So,
there is no current. So, we are not writing
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any expression for current for that.
Now, we shall write down the expression for
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the non-saturated region. Non-saturated or
we also call it linear or weak inversion region.
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In this weak inversion region, we can find
out the the the the current. First of all
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let us find out the effective voltage that
is being applied between the source and drain.
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As you have seen, we are applying a voltage
V d s between the source and drain sorry on
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the gate I mean V d s between the source and
drain. Let me draw the diagram here little
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that will make it easier to understand. So,
here is your source and here is your drain.
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This is the channel then you have got the
silicon dioxide and top of that you have polysilicon.
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So, what you are doing? You are applying a
voltage V d s, positive voltage. So, this
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is your V d s between the source and drain
and you are all supplying a voltage V g s
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between source and gate. This is your source
drain and this is your gate. So, V g s, now
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although you are applying a voltage V g s
between the source and gate; the effective
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voltage across the channel is not same because
this drain voltage that you are applying is
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interacting with the voltage that you apply
at the gate. So, although you are applying
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a gate voltage V g s here, the effective the
effective voltage in this channel region will
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be different.
For example in here the voltage you know that
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the the the the voltage V d s will be will
will be across this length L and here you
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can say the voltage is 0 and here the voltage
is V d s. So, if you take the average value
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of 0 and V d s this will be equal to V d s
by 2. Therefore, the effective gate voltage
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will be equal to V g s that you apply here
minus V t threshold voltage as we know, you
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the you have to subtract that threshold voltage
because you know the before that there will
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be depletion region. You will you will require
a voltage V t only after that the inversion
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region starts and as a consequence the effective
gate voltage will be V g s minus V t minus
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V d s by 2. We have taken the average value.
Of course, it will be it will be varying across
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the channel, but, we are taking the average
value. This is the effective gate voltage.
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Now, the current, we can derive the expression
for current we can expression for current.
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For that purpose first we shall find out the
Q c. This Q c charge induced in the channel
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is equal to C into V. That means, C is equal
the Q c is equal to C into V that is equal
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to C. What is C value of C? Epsilon, this
is your oxide into into area that is equal
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to W into L because we have seen that parallel
plate capacitor has an area W width W and
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L is the length. So, area is equal to W into
L by D. This is the this is the capacitance
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and your effective voltage will be equal to
V g s minus V t minus V d s by 2. So, this
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is the this is this is a charge that will
be induced in the channel.
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So, this is the charge and now we know the
we already know the electron transit time.
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What was the electron transit time that you
find out? This is equal to L square by mu
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v d s. So, this we can substitute. That means,
I d s I d s is equal to Q c by t n that is
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equal to epsilon oxide into W into L by D
into V g s minus V t minus V d s by 2 and
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it will be divided by L square. This is the
expression for electron transit time. This
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is the L square t n is equal to L square by
mu n d V s.
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So, what will happen; here you will have L
square and mu will be here, mu n will be here
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in the numerator it will go to the numerator
and here you will have V d s. So, this is
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the this is the expression that we get. This
is mu n and this l will cancel with square.
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So, ultimately we get an expression that is
equal to W L. It was L square W L by d, the
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current expression that we get is equal to
W mu n. This is mu n epsilon o x. This is
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your permittivity of electron into D into
L and here you get V g s minus V t minus V
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d s by 2 into V d s. Now, this is the this
is the this is the current that flows through
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the electron. So, that will be the current
that will be flowing through the electron.
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Now, you can express in terms of two other
important parameters; one is known as K. K
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is a constant which depends on the fabrication.
So, what is the value of K? K is equal to
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we can express it this current in terms of
K which is equal to mu n. This mu n and epsilon
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o x by D. You know when you fabricate; these
three parameters are kept usually constant.
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We usually change the length, this L is changed,
width is changed, but, these three are usually
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kept constant. That is why this is sometimes
is replaced by K. That means, if we substitute
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this value of K we get I d s is equal to K
W by L V g s minus V t minus V d s by 2 into
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V d s.
Another we can also represent it in terms
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of what is known as the gate capacitance C
g. What is the value of C g? C g is equal
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to this is your e o x into W L by D. That
you have already seen that is a capacitance.
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This this is the, you have already seen epsilon
A by D here a is equal to W by L. So, we can
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also express I d s in terms of this capacitance.
So, in terms of K constant in terms of C g.
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So, I d s we can write as I d s is equal to
C g mu n by L square into V g s minus V t
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minus V d s by 2 into V d s . So, this is
the current that we get whenever the circuit
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is in the linear region.
It may, you may note that we are calling it
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linear region, but, it is not exactly linear.
Why it is not exactly linear because you can
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see, if we assume that V d s by 2 is too small
compared to V g s minus V t. Only then it
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becomes proportional to V d s. That means,
if we neglect this part only then it becomes
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linear and that is a reason why the this the
linear region is not exactly linear, but,
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it approximately linear, particularly when
the drain voltage is very close to 0. Only
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then it is linear so; that means, V d s is
negligible compared to V g s minus V t then
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is linear.
So, we have derived expression for the non-linear
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region.
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00:24:02,499 --> 00:24:09,499
Now, let us consider the saturated region.
So, you can say the second part is your saturated
192
00:24:12,710 --> 00:24:19,710
region. So, in the saturated region what is
the K difference between the linear region
193
00:24:22,499 --> 00:24:29,499
and saturated region? One important difference
is in the saturated region, the current is
194
00:24:30,279 --> 00:24:37,279
independent of the drain voltage and when
it happens? When the voltage drop across the
195
00:24:38,759 --> 00:24:45,749
channel is equal to the effective gate voltage.
That mean if the drain voltage is such which
196
00:24:45,749 --> 00:24:52,749
is equal to V d s is equal to V g s minus
V t. That means, this occurs when V d s is
197
00:24:53,049 --> 00:25:00,049
equal to V g s minus V t. This is the effective
gate voltage which is equal to the drain voltage
198
00:25:00,330 --> 00:25:07,299
beyond which, beyond this point the drain
current is independent of V d s. That means,
199
00:25:07,299 --> 00:25:13,289
this is the point from where we can consider
we can say that saturated region has started
200
00:25:13,289 --> 00:25:20,289
below that it is linear or non-saturated region.
So, what we can do, we can obtain the expression
201
00:25:21,220 --> 00:25:27,330
for drain current in the saturated region
by substituting V d s is equal to V g s minus
202
00:25:27,330 --> 00:25:34,330
V t. So, we can say that I d s is equal to
K W by L into V g s minus V t minus V g s
203
00:25:44,519 --> 00:25:51,519
by 2 into here you can substitute this. sorry
This is d s V d s minus sorry V g s minus
204
00:25:59,559 --> 00:26:06,559
V t. We are substituting this V g s minus
V t. So, this is equal to K W by L into V
205
00:26:07,619 --> 00:26:14,619
g s minus V t square and here it becomes,
here also it will be V g s minus V t. So,
206
00:26:15,730 --> 00:26:22,730
it will be equal to V g s minus V t square
by 2.
207
00:26:23,379 --> 00:26:30,379
So, this will be equal to K W L by 2 because
half this if we V g s minus V t square minus
208
00:26:32,720 --> 00:26:37,679
V g s minus V t square by 2 will become V
g s minus V t square by 2. So, this will be
209
00:26:37,679 --> 00:26:44,679
equal, this two we have taken here. So, K
W L K W by 2 L into V g s minus V t square.
210
00:26:48,269 --> 00:26:55,269
So, here indeed we find an expression where
it is independent of the drain voltage. So,
211
00:26:55,519 --> 00:27:02,379
but, it is there is a it is a there is a square
law dependence on V g s minus V t. That means,
212
00:27:02,379 --> 00:27:09,379
this saturation current will increase at the
square law as the gate voltage is increased.
213
00:27:11,720 --> 00:27:18,720
So, that is proportional to V g s minus V
t square. So, this is the expression for drain
214
00:27:19,259 --> 00:27:26,190
current and also you can express it in terms
of the capacitance that will be equal to C
215
00:27:26,190 --> 00:27:33,190
g mu n by 2 L square into V g s minus V t
square.
216
00:27:37,479 --> 00:27:44,479
So, this is the expression for that. That
in terms of C g gate capacitance and of course,
217
00:27:50,220 --> 00:27:55,289
you can you can represent it with the help
of another parameter. There is another parameter
218
00:27:55,289 --> 00:28:02,289
which is known as C o x C o x and C g these
two are different this C o x is the unit gate
219
00:28:03,259 --> 00:28:08,479
capacitance. That means, capacitance of unit
area. So, what is a relationship between C
220
00:28:08,479 --> 00:28:15,479
g and C o x? C g will be equal to C o x into
W that area you have to multiply W into L.
221
00:28:18,119 --> 00:28:23,269
So, C o x into W into L if we substitute it
here. We can write it in this way, this l
222
00:28:23,269 --> 00:28:29,669
it will become it l square this l will cancel
out. So, it will be mu n will be there in
223
00:28:29,669 --> 00:28:36,669
any case then w will be there and it will
be C o x by 2 into L and here it will be V
224
00:28:39,919 --> 00:28:46,919
g s minus V t square. So, this is in terms
of the unit gate capacitance C o x.
225
00:28:48,049 --> 00:28:55,049
So, we have seen the expression for saturation
current.
226
00:28:55,220 --> 00:29:02,220
Now, let us represent the n MOS electrical
characteristics n MOS characteristics. Let
227
00:29:09,239 --> 00:29:16,239
us now plot that saturation and non-saturation
current. We have seen that we can divide into
228
00:29:18,399 --> 00:29:25,399
three regions. Let us assume it varies from
1 2 3 4 5; 1 volt 2 volt 3 volt 4 volt and
229
00:29:27,989 --> 00:29:34,220
5 volt and this I d s usually varies in the
range of in the milliampere region. So, it
230
00:29:34,220 --> 00:29:41,220
is milliampere. So, 0 to let us assume it
is 0.30 milliampere. So, usually it will vary
231
00:29:44,429 --> 00:29:49,549
in this region.
Now, as you have seen there are three regions;
232
00:29:49,549 --> 00:29:56,549
I d s is equal to 0 for V g s less than V
t. We can write V t n if we consider it n
233
00:30:01,049 --> 00:30:08,049
MOS transistor. So, which part will represent
that? This line, that means, this line will
234
00:30:08,679 --> 00:30:15,679
correspond to this particular line will correspond
to this region. That means, irrespective of
235
00:30:15,919 --> 00:30:22,919
the drain voltage current is 0, I d s is 0.
So, this represents the cut-off region cut-off
236
00:30:27,239 --> 00:30:34,239
region. So, this this is your cut-off region.
Now, non-linear, linear region I d s is equal
237
00:30:38,350 --> 00:30:45,350
to we have already seen the expression. We
can write it K W by L into V g s minus V t
238
00:30:49,609 --> 00:30:56,609
minus V g s V d s by 2 into V d s. This part
as we have seen is separated by a line. I
239
00:30:59,889 --> 00:31:06,889
mean this corresponds to V d s is equal to
V g s minus V t. That means this part is your
240
00:31:10,859 --> 00:31:17,859
linear region. So, obviously, there will be
different curves for different gate voltages.
241
00:31:26,830 --> 00:31:33,830
Say this is this corresponds to V. Let us
assume V g s is equal to V t plus 0.5 volt.
242
00:31:35,659 --> 00:31:42,659
Let us assume this corresponds to V t plus
1 volt 1.0 volt. This will correspond to let
243
00:31:51,599 --> 00:31:58,599
us assume this is V t plus 1.5 volt. So, the
in this part the current is constant this
244
00:32:02,570 --> 00:32:07,119
part current is constant. So, this is a saturation
region. So, this is the linear region, this
245
00:32:07,119 --> 00:32:14,119
is the cut-off region and this is the saturation
region saturated region and in the saturated
246
00:32:17,179 --> 00:32:24,179
region the current expression is given by
and this is for this non-saturated region
247
00:32:24,519 --> 00:32:31,519
is for V g s is greater than equal to V t
and V d s is less than V g s minus V t. That
248
00:32:39,739 --> 00:32:45,960
means, V d s has to be less than V g s minus
V t in this region and V g s has to be greater
249
00:32:45,960 --> 00:32:49,599
than V t.
So, for these two we call it linear region.
250
00:32:49,599 --> 00:32:56,599
This is cut-off this is your cut-off region
cut-off. This corresponds to cut-off region.
251
00:32:58,460 --> 00:33:05,460
This corresponds to linear non-saturated or
weak inversion region and this correspond
252
00:33:05,580 --> 00:33:12,580
the third region this is your 1 2 and 3 I
d s is equal to, we have seen the expression
253
00:33:15,359 --> 00:33:22,359
is K W by 2 L into V g s minus V t square
and this happens when V g s is greater than
254
00:33:29,649 --> 00:33:36,649
equal to V t and also V d s has to be greater
than V g s minus V t. So, this is your saturated
255
00:33:42,070 --> 00:33:49,070
region. This corresponds to saturated.
So, we have seen, we have derived the expression
256
00:33:55,349 --> 00:34:02,349
for drain current for two regions; linear
and saturated regions and we have defined
257
00:34:03,080 --> 00:34:08,940
the regions based on the drain voltage and
gate voltage. Here, we have not taken into
258
00:34:08,940 --> 00:34:14,820
account the body voltage with respect to the
source. We have assumed that the body is connected
259
00:34:14,820 --> 00:34:17,080
to the source.
260
00:34:17,080 --> 00:34:24,080
That means, if we consider this diagram, this
simple diagram we can say this body is connected
261
00:34:24,340 --> 00:34:31,130
to ground. That means, this is connected to
ground. Source is connected to ground and
262
00:34:31,130 --> 00:34:38,130
body is also connected to ground and usually
this is done you know by having a region,
263
00:34:41,010 --> 00:34:48,010
this is called P plus and this P plus is actually
used to connect the substrate to ground or
264
00:34:49,770 --> 00:34:56,770
to some other voltage. Later on we shall see
how we can really apply this voltage to have
265
00:34:56,860 --> 00:35:03,860
different threshold voltages. So, for the
time being let us assume that this drain,
266
00:35:04,290 --> 00:35:10,870
that source to substrate voltage is 0.
267
00:35:10,870 --> 00:35:17,870
Now, we have considered the n MOS depletion
type, we have n enhancement type transistor.
268
00:35:20,660 --> 00:35:27,660
Let us now focus on n MOS depletion type transistor
and as we know in case of n MOS depletion
269
00:35:27,740 --> 00:35:34,740
type transistor, a channel formation is done
by implanting suitable type impurity in the
270
00:35:35,680 --> 00:35:40,380
channel region. So, a conducting layer already
exists and as a result you do not require
271
00:35:40,380 --> 00:35:47,380
a gate voltage to to form a channel. So, current
can flow even when the gate voltage is 0 and
272
00:35:47,600 --> 00:35:52,820
you can you can stop the flow of current by
applying a negative gate voltage and that
273
00:35:52,820 --> 00:35:58,680
is precisely shown in this diagram. You can
see here even when the gate voltage is 0;
274
00:35:58,680 --> 00:36:03,730
there is a flow of current and if you want
to stop it you have to apply negative voltage.
275
00:36:03,730 --> 00:36:08,620
That means, minus minus minus 1 volt minus
2 volt and so on.
276
00:36:08,620 --> 00:36:14,880
Otherwise, there is no difference in the characteristic
curve. I mean it is very similar to the n
277
00:36:14,880 --> 00:36:21,270
MOS depletion type. I mean enhancement type
transistor except that these gate voltages
278
00:36:21,270 --> 00:36:26,390
are different for different currents. That
means, normally in case of enhancement type
279
00:36:26,390 --> 00:36:31,290
transistor this will start when the gate voltage
is slightly more than the threshold voltage.
280
00:36:31,290 --> 00:36:36,250
But, here as you can see this is minus 2 volt.
So, in case of depletion mode of transistors
281
00:36:36,250 --> 00:36:42,140
only difference that we will get is the for
different gate voltages you will get different
282
00:36:42,140 --> 00:36:46,950
curves. That means, you have to apply a negative
voltage to stop the flow of current and if
283
00:36:46,950 --> 00:36:53,950
you apply positive gate voltage then current
will increase and obviously, as we know that
284
00:36:53,970 --> 00:36:59,700
it will increase following square law V g
s minus V t square.
285
00:36:59,700 --> 00:37:06,700
So, we have seen the characteristic curve
for n MOS type transistors both enhancement
286
00:37:06,790 --> 00:37:12,420
type and depletion type. What about the P
type transistors?
287
00:37:12,420 --> 00:37:19,420
Actually that can be drawn say P MOS transistors.
We shall not derive expression for that I
288
00:37:27,850 --> 00:37:34,850
shall simply show you the characteristic curve,
how it will look like. So, you have got four
289
00:37:40,020 --> 00:37:47,020
quadrants. You can see here, you have got
four quadrants. This is your I d s and this
290
00:37:51,550 --> 00:37:57,650
is your V g s. This is positive and this is
negative. For n MOS transistors, the curve
291
00:37:57,650 --> 00:38:04,640
is on this side. On the other hand for P MOS
transistors the curve will be on the negative
292
00:38:04,640 --> 00:38:11,640
side. That means, you will be applying your
the voltage, that drain voltage sorry this
293
00:38:11,710 --> 00:38:18,040
is your V d s. I have written wrongly V d
s. So, here it will be negative here also
294
00:38:18,040 --> 00:38:25,040
V d s, but, here it is say 0 1 2 here it is
minus 1 minus 2 minus 3 minus 4 minus 5 and
295
00:38:31,360 --> 00:38:34,710
so on
That means you will apply negative gate, negative
296
00:38:34,710 --> 00:38:40,010
voltage to the drain with respect to source
and current will flow in the opposite directions.
297
00:38:40,010 --> 00:38:46,970
And these are for different different gate
voltages and more negative they correspond
298
00:38:46,970 --> 00:38:53,970
to more negative gate voltages. And just like
your n MOS transistors here also, there is
299
00:38:56,670 --> 00:39:03,670
a there are three regions cut-off. So, just
like your n MOS n MOS transistor here also,
300
00:39:10,640 --> 00:39:17,640
you have got linear region, this is a saturation
region
and this line obviously, will represent the
301
00:39:22,050 --> 00:39:29,050
cut-off region. This is a cut-off region for
p MOS transistor, this is a cut-off region
302
00:39:29,760 --> 00:39:36,600
for n MOS transistor. So, on; that means,
this this this the the characteristic curve
303
00:39:36,600 --> 00:39:43,600
for p MOS transistor will be on this quadrant
both for enhancement type and depletion type.
304
00:39:44,130 --> 00:39:51,130
Now, let us focus on the threshold voltage.
This threshold voltage has been found to be
305
00:39:56,790 --> 00:40:03,420
one of one of the most crucial parameter which
controls the operation of a MOS transistors
306
00:40:03,420 --> 00:40:10,420
MOS transistor. So, here you can see this
corresponds to n MOS enhancement type transistor.
307
00:40:11,340 --> 00:40:18,340
You have to apply a threshold voltage I mean
V t n to start the flow of current and characteristic
308
00:40:18,830 --> 00:40:22,990
curve will be somewhat like this. That this
is the drain current will increase and as
309
00:40:22,990 --> 00:40:29,990
you know this essentially represents the the
the the drain current in the saturation mode.
310
00:40:32,330 --> 00:40:36,740
That means, in the saturation mode, although
I have drawn it linearly, but, it will be
311
00:40:36,740 --> 00:40:42,960
quadratic. As we have seen this current is
proportional to I d s is proportional to V
312
00:40:42,960 --> 00:40:46,460
g s minus V t square. So, it increases at
this rate.
313
00:40:46,460 --> 00:40:52,700
So, far as the depletion type transistor is
concerned; curve is somewhat similar, but,
314
00:40:52,700 --> 00:40:59,270
it will be shifted towards the towards the
negative quadrant. As you can see you have
315
00:40:59,270 --> 00:41:05,390
to apply a minus V t n, a threshold voltage
which is the minus V t n in this case to stop
316
00:41:05,390 --> 00:41:12,390
the flow of current and if you increase the
the I mean negative to less negative to 0
317
00:41:14,320 --> 00:41:19,950
and then positive; then the drain current
increases following the same nature of curve
318
00:41:19,950 --> 00:41:24,830
and of course, the the amount of current will
be dependent on the gate voltage. So, you
319
00:41:24,830 --> 00:41:31,830
can see the the thethe these two essentially
represent the the drain current with respect
320
00:41:32,530 --> 00:41:39,530
to gate-to-source voltage for enhancement
type transistor and for depletion type transistor.
321
00:41:39,540 --> 00:41:46,540
Similarly, you can consider the gate-to-source
voltage for p MOS type transistors. This corresponds
322
00:41:47,850 --> 00:41:53,690
to the characteristic curve for p MOS type
transistor. Here you can see the variation
323
00:41:53,690 --> 00:42:00,240
of drain current with respect to the gate
volt gate-to-source voltage. And a negative
324
00:42:00,240 --> 00:42:06,860
voltage is required to for the flow of current
and you can see the curve is somewhat similar,
325
00:42:06,860 --> 00:42:12,390
but, inverted in this case because in the
it is in the negative quadrant. Similarly,
326
00:42:12,390 --> 00:42:19,390
this is this this curve correspond to corresponds
to the p MOS depletion type transistor and
327
00:42:21,250 --> 00:42:27,020
here as you can see you have to apply a positive
voltage to stop the flow of current and as
328
00:42:27,020 --> 00:42:34,020
you as you make it smaller and smaller and
when it becomes 0; this side is the gate-to-source
329
00:42:34,190 --> 00:42:40,280
voltage. So, when it becomes 0 still there
is a flow of current and as you make it more
330
00:42:40,280 --> 00:42:45,640
and more negative; the current increases in
case of p MOS depletion type transistor.
331
00:42:45,640 --> 00:42:52,640
So, these four; these two and these two represent
the the variation of gate drain current with
332
00:42:56,590 --> 00:43:03,170
respect to the variation of gate-to-source
voltage and you can see the threshold voltage
333
00:43:03,170 --> 00:43:10,170
actually plays plays acts somewhat like the
cutting voltage of you know cutting voltage
334
00:43:10,850 --> 00:43:15,910
of bipolar junction transistors. As you know
in case of bipolar junction transistors flow
335
00:43:15,910 --> 00:43:20,640
of current is dependent you know, you require
a cutting voltage. For example, for silicon
336
00:43:20,640 --> 00:43:25,840
the base base voltage should be more than
0.6 or 0.7 volt. That is known as cutting
337
00:43:25,840 --> 00:43:32,020
voltage. Here also here also it is somewhat
similar to that, but, we call it threshold
338
00:43:32,020 --> 00:43:36,470
voltage not cutting voltage.
339
00:43:36,470 --> 00:43:43,470
Now, one one very important as I told threshold
voltage plays a very important role and on
340
00:43:48,040 --> 00:43:53,640
what factors or parameter it depends? You
can really derive an expression for threshold
341
00:43:53,640 --> 00:44:00,640
voltage in terms of various parameters, but,
here I have simply taken the expression without
342
00:44:00,890 --> 00:44:07,000
and I am not going to derive it and as you
can see V t, the threshold voltage is equal
343
00:44:07,000 --> 00:44:14,000
to V t 0 plus gamma into root 2 phi minus
2 phi plus V t V s b absolute value of that
344
00:44:17,880 --> 00:44:24,590
and minus absolute value of 2 phi b.
Here this gamma is known as substrate bias
345
00:44:24,590 --> 00:44:31,590
coefficient. Why substrate bias coefficient?
As you can see this V s b V s b is actually
346
00:44:32,990 --> 00:44:39,450
the source-to-body voltage that you are applying
source-to-body voltage that you’ll be applying.
347
00:44:39,450 --> 00:44:46,450
That means, if we consider a a curve here
you can apply a voltage between the source
348
00:44:47,970 --> 00:44:54,230
and body. That means, the this particular
source and this body you can apply positive
349
00:44:54,230 --> 00:45:00,420
voltage to the body with respect to the source
and that will actually increase the threshold
350
00:45:00,420 --> 00:45:06,480
voltage as we shall see.
So, by changing the body bias, substrate body
351
00:45:06,480 --> 00:45:10,950
bias the threshold voltage can be controlled
and in this expression you have got V s b.
352
00:45:10,950 --> 00:45:17,950
That is why it is called substrate bias coefficient
gamma. And gamma is equal to root 2 q. Q is
353
00:45:20,040 --> 00:45:26,980
the charge of electron epsilon s I which is
the permittivity of electron and n a n a is
354
00:45:26,980 --> 00:45:33,980
the carrier concentration in the in the in
the substrate. So, n a is the carrier concentration
355
00:45:36,230 --> 00:45:43,230
of the substrate and C o x C o x is the unit
unit capacitance of the gate region.
356
00:45:45,360 --> 00:45:50,720
So, this is the expression for gamma. So,
it will depend on these parameters and phi
357
00:45:50,720 --> 00:45:57,720
b is the fermi band potential which is equal
to K t by q. K is the Kelvin constant and
358
00:45:59,620 --> 00:46:05,340
t is the temperature in absolute value of
temperature not in degree or Fahrenheit this
359
00:46:05,340 --> 00:46:12,340
is the absolute value of temperature and Q
is the charge of electron and n i is the carrier
360
00:46:12,380 --> 00:46:17,160
concentration of the intrinsic silicon. So,
intrinsic silicon will have some carrier concentration.
361
00:46:17,160 --> 00:46:22,080
This is the n i and n a is the carrier concentration
of the substrate as I have already told.
362
00:46:22,080 --> 00:46:28,130
So, based on that you can find out the threshold
voltage by substituting different parameter
363
00:46:28,130 --> 00:46:35,130
values for a particular fabrication technology.
Obviously, So, far as this part is concerned
364
00:46:35,290 --> 00:46:42,290
Q epsilon s I, K these are constants. On the
other hand the C o x is the unit gate capacitance
365
00:46:48,760 --> 00:46:55,050
or these carrier concentrations you can will
vary from process one process technology to
366
00:46:55,050 --> 00:47:02,050
the other process technology and as a consequence
this threshold voltage will be different.
367
00:47:02,170 --> 00:47:09,170
Now, let us take up an example. Let us see
the, we can calculate the threshold voltage
368
00:47:10,970 --> 00:47:17,970
and we can see how exactly the threshold voltage
varies as you vary the substrate bias phi
369
00:47:19,070 --> 00:47:26,070
b is equal to you can substitute different
parameter values. This n i is equal to 1.45
370
00:47:26,500 --> 00:47:33,500
into ten to the power ten centimeter. I mean
per centimeter cube and n a is equal to 10
371
00:47:36,560 --> 00:47:43,560
the power 16. So, 0.26 actually this K t by
Q as you know is 26 millivolt. That is the
372
00:47:45,470 --> 00:47:52,470
K t by Q value and this is the ratio of the
n i by n a. Obviously, the intrinsic silicon
373
00:47:54,690 --> 00:48:00,130
has much layer lower carrier concentration
compared to the carrier concentration of this
374
00:48:00,130 --> 00:48:04,360
substrate.
That means as you know substrate is uniformly
375
00:48:04,360 --> 00:48:11,360
doped to have more carrier concentration compared
to the intrinsic substrate and phi b value
376
00:48:12,460 --> 00:48:19,460
is calculated. See this is the value of C
o x. This phi b is minus 0.35 and C o x is
377
00:48:22,810 --> 00:48:29,620
equal to epsilon o x by t o x and this is
the value 7.03 into 10 to the power minus
378
00:48:29,620 --> 00:48:36,000
8 farad per centimeter square and you can
substitute the various values to get gamma.
379
00:48:36,000 --> 00:48:43,000
Gamma is equal to, becomes 0.82. Here the
value of the charge of electron the permittivity
380
00:48:45,610 --> 00:48:52,610
of silicon dioxide n a, these are all substituted
and C o x these are all substituted and by
381
00:48:54,490 --> 00:49:01,490
substituting various values we get V t is
equal to roughly 0.4. Assuming that 0.4 is
382
00:49:03,550 --> 00:49:10,550
the threshold voltage whenever the body bias
is 0; that means, source is connected to the
383
00:49:12,440 --> 00:49:19,440
body and this part is is will this is the
0.82 this is your gamma into root 0.7 plus
384
00:49:23,070 --> 00:49:30,070
V s b. We have to take the absolute value
and minus root 0.7. Now, you can actually
385
00:49:31,280 --> 00:49:36,600
vary V s b to get different different value
of threshold voltage.
386
00:49:36,600 --> 00:49:41,820
So, threshold voltage v t is not constant
with respect to the voltage difference between
387
00:49:41,820 --> 00:49:48,620
the substrate and the source of the transistor.
As you can see using that expression how the
388
00:49:48,620 --> 00:49:54,360
threshold voltage can change as you as you
change the substrate body bias. So, you can
389
00:49:54,360 --> 00:50:00,090
see here, when the substrate bias is 0, as
you have seen the threshold voltage is 0.4
390
00:50:00,090 --> 00:50:07,090
volt. But, as you increase the substrate bias
say from say 0 to 1 volt to 2 volt to 3 volt,
391
00:50:07,280 --> 00:50:14,280
it can it can reach say 1.6. So, over a large
range 0.4 to 1.6, a large change in the threshold
392
00:50:15,070 --> 00:50:21,600
voltage that can take place as you vary the
threshold, the substrate bias with and threshold
393
00:50:21,600 --> 00:50:28,600
voltage will change and later on we shall
use this and see how the threshold voltage
394
00:50:30,310 --> 00:50:35,500
can be controlled to reduce what is known
as leakage current.
395
00:50:35,500 --> 00:50:40,150
Because the leakage current is heavily dependent
on the threshold voltage and later on we shall
396
00:50:40,150 --> 00:50:47,150
see instead of this positive bias, we shall
usually apply negative body bias to low to
397
00:50:47,880 --> 00:50:54,880
to to increase this. I mean with this is called
the reverse body bias we shall do that to
398
00:50:56,180 --> 00:51:02,760
increase the threshold voltage such that the
leakage current is lowered. That means, larger
399
00:51:02,760 --> 00:51:07,640
the threshold; voltage smaller is the leakage
current. Smaller the threshold voltage larger
400
00:51:07,640 --> 00:51:14,640
is the leakage current. Later on we shall
discuss more about it.
401
00:51:14,670 --> 00:51:21,670
So, this is a body effect
402
00:51:22,520 --> 00:51:29,520
Now, we shall consider another very important
parameter that is your channel-length rather
403
00:51:32,350 --> 00:51:39,350
phenomenon, channel-length modulation. Here
in our expression for drain current, we have
404
00:51:42,000 --> 00:51:47,970
assumed that this l is constant fixed. It
does not really change, but, in reality we
405
00:51:47,970 --> 00:51:54,970
will see this l is dependent on the drain
voltage. However, this dependence is not visible
406
00:52:01,200 --> 00:52:08,200
until the channel-length is small. That means,
it is, it becomes predominant in short channel
407
00:52:08,810 --> 00:52:09,530
devices.
408
00:52:09,530 --> 00:52:16,530
When the channel-length is say 0.25 micron
0.25 micron micro millimeter then this variation
409
00:52:19,650 --> 00:52:25,260
is so small that we do not really bother about
it. But, whenever you are considering say
410
00:52:25,260 --> 00:52:32,260
sixty nanometer nanometer or say 45 nanometer
technology instead of 250 nanometer technology,
411
00:52:37,480 --> 00:52:44,210
then this channel-length variation becomes
visible or it cannot be neglected any longer.
412
00:52:44,210 --> 00:52:51,210
First we shall show you why this variation
take place. You can see the channel region
413
00:52:52,000 --> 00:52:58,100
is not uniform throughout the channel the
reason for that is here the drain voltage
414
00:52:58,100 --> 00:53:04,280
is 0 here the drain voltage is high and because
of the interaction between the gate voltage
415
00:53:04,280 --> 00:53:09,670
and drain voltage; the dense the the thickness
of the channel region is not near the source
416
00:53:09,670 --> 00:53:15,910
and it is very narrow near the drain. And
as we further increase the drain voltage what
417
00:53:15,910 --> 00:53:22,910
happens at some point of time the very close
to the drain there is no carrier. That means,
418
00:53:24,230 --> 00:53:31,230
it becomes pinch-off. If we increase the drain
voltage further, we will find that that that
419
00:53:32,720 --> 00:53:38,650
pinch-off point moves towards source. So,
here there is small region where there is
420
00:53:38,650 --> 00:53:44,810
no charge carrier. So, essentially channel-length
is now becoming smaller than the the physical
421
00:53:44,810 --> 00:53:49,330
length of the device.
So, effective channel-length is smaller and
422
00:53:49,330 --> 00:53:54,240
this is the, that is why we call it channel-length
modulation. Essentially it is dependent on
423
00:53:54,240 --> 00:53:55,280
the drain voltage.
424
00:53:55,280 --> 00:54:01,240
How do you take into account? We can take
into account by substituting L effective which
425
00:54:01,240 --> 00:54:08,190
is equal to L minus delta L. So, n minus delta
L is actually we can represent it by this
426
00:54:08,190 --> 00:54:15,190
we can represent it by this 1 minus this is
the expression where we have substituted effective
427
00:54:15,520 --> 00:54:21,680
channel-length and we have got this expression.
And this this variation is proportional to
428
00:54:21,680 --> 00:54:27,380
V d s minus V d sat. Essentially, when the
saturation starts that is your V g s minus
429
00:54:27,380 --> 00:54:33,820
V t and this is the V d s. So, this change
in the channel-length is proportional to the
430
00:54:33,820 --> 00:54:39,300
drain voltage. When the drain voltage is large
only then this reduction occurs and this can
431
00:54:39,300 --> 00:54:45,670
be represented, this change 1 minus delta
L by L can be represented by one minus lambda
432
00:54:45,670 --> 00:54:50,910
V d s where lambda is the is known as channel-length
modulation coefficient.
433
00:54:50,910 --> 00:54:57,910
So, we can now express I d s in term in terms
of this lambda and it becomes like this, mu
434
00:54:58,640 --> 00:55:05,640
n C o x by 2 W n by L n into V g s minus V
t square into 1 plus lambda V d s. So, you
435
00:55:08,110 --> 00:55:15,110
can see here, it is no longer one. It is here
normally it is V d s. So, what it is 1 plus
436
00:55:15,380 --> 00:55:20,300
lambda V d s. So, it varies with drain voltage.
437
00:55:20,300 --> 00:55:26,510
And this can be depicted pictorially with
the help of this diagram as you can see in
438
00:55:26,510 --> 00:55:32,050
the saturation region, the although I have
drawn it in a little exaggerated form, it
439
00:55:32,050 --> 00:55:39,050
will not be the slope will not be so high.
What you can see the drain current is varying
440
00:55:39,800 --> 00:55:45,750
even in the saturation region because of channel-length
modulation effect and you can see here it
441
00:55:45,750 --> 00:55:51,490
is becoming the it is no longer parallel,
but, it is there is a point where it is touching
442
00:55:51,490 --> 00:55:56,670
and this is how the characteristic can be
represented.
443
00:55:56,670 --> 00:56:03,670
Now, another very important parameter that
is known as transistor trans-conductance for
444
00:56:03,880 --> 00:56:09,370
bipolar junction transistors which is a current
controlled device it is represented by gain
445
00:56:09,370 --> 00:56:15,000
of the transistor beta the collector current
by base current. On the other hand in case
446
00:56:15,000 --> 00:56:22,000
of MOS transistors it is a voltage controlled
device and similar parameter is known as trans-conductance.
447
00:56:22,170 --> 00:56:26,530
That means, rate of change of drain current
by rate of change of gate voltage. So, here
448
00:56:26,530 --> 00:56:31,450
you have seen the the drain current is controlled
by the gate voltage.
449
00:56:31,450 --> 00:56:38,450
So, this trans-conductance is represented
by delta I d s change of change of drain current
450
00:56:38,450 --> 00:56:45,190
by change of gate voltage delta V d s keeping
the drain-to-source voltage constant. So,
451
00:56:45,190 --> 00:56:51,420
that we can derive as we know I d s is equal
to Q c by t s D. So, delta I d s is equal
452
00:56:51,420 --> 00:56:57,850
to delta Q c by t s D and this is the t s
D. That expression we have already derived
453
00:56:57,850 --> 00:57:04,000
I am not going into the details of that. So,
delta I d delta I d s is equal to mu n C g
454
00:57:04,000 --> 00:57:10,710
s by L square into V d s into delta V g s
and g m is equal to delta I d s by delta V
455
00:57:10,710 --> 00:57:17,710
g s, as we have seen which is equal to C g
into mu n into V d s by L square.
456
00:57:17,910 --> 00:57:24,220
And finally, by substituting V d s is equal
to V g s minus V t, we get g m is equal to
457
00:57:24,220 --> 00:57:31,220
mu n epsilon I n s into epsilon 0 W by D into
L into V g s minus V t. So, you can see the
458
00:57:33,750 --> 00:57:39,630
the gain which is represented by transistor
trans-conductance. More the gain it is better.
459
00:57:39,630 --> 00:57:45,900
We can see it is dependent on the mobility
of the device, width of the device, thickness
460
00:57:45,900 --> 00:57:51,980
of the silicon dioxide length of the channel
and the effective gate voltage which is equal
461
00:57:51,980 --> 00:57:58,980
to V g s minus V t. So, this is the parameter
and we can, how we can increase the value
462
00:58:00,230 --> 00:58:06,410
of g m is clear from this expression which
parameter we can really; that means, if the
463
00:58:06,410 --> 00:58:11,140
width is more more current will flow. So,
that is why g m will be more. If the thickness
464
00:58:11,140 --> 00:58:16,260
is small of the silicon dioxide gate voltage
you will have more control and obviously,
465
00:58:16,260 --> 00:58:23,260
g m will be large. Similarly, the length is
small more current will flow. So, g m will
466
00:58:23,550 --> 00:58:24,310
be increase. So,
467
00:58:24,310 --> 00:58:30,740
So, here we can summarize. We have discussed
about three regions of the operation of MOS
468
00:58:30,740 --> 00:58:35,670
transistor. We have derived the expression
of threshold voltage and explained what is
469
00:58:35,670 --> 00:58:42,670
known as body effect and we have also considered
channel-length modulation phenomenon and then
470
00:58:43,000 --> 00:58:50,000
explain what is known as transistor trans-conductance.
So, with this, let us stop here. In the next
471
00:58:50,640 --> 00:58:57,180
lecture we shall discuss how a transistor
can be used as a switch. Thank you.