Course Name: MultiCore Computer Architecture-Storage and Interconnects

Course abstract

We are in the era of multi-core systems where even the simplest of handheld devices like a smart phone houses many processors in a single chip. The core counts are ever increasing from 8 to 10 in smart phones to over 100s in super computers. This course will introduce the students to the world of multi-core computer architectures. With the unprecedented growth of data science, on-chip storage systems and inter-core communication framework are getting equal attention as that of processors. This course will focus on delivering an in-depth exposure in memory-subsystems and interconnects of Tiled Chip Multi-Core Processors with few introductory sessions on advanced superscalar processors. The course concludes with pointers to current research standings and on-going research directions for motivating the students to explore further


Course Instructor

Media Object

Dr. John Jose

Dr. John Jose is an Assistant Professor in Department of Computer Science & Engineering, Indian Institute of Technology Guwahati, Assam since July 2015. Prior to this he has over 10 years of teaching experience at both undergraduate and graduate level in AICTE approved NBA/NACC accredited engineering institutes in Kerala. He did his B.Tech degree in CSE from Cochin University, Kerala. He was a rank holder in M.Tech degree from Vellore Institute of Technology (VIT University). He completed his Ph.D degree from Indian Institute of Technology Madras. He is currently supervising 5 Ph.D thesis and 5 M.Tech thesis. His area of interests is in on-chip interconnection networks and cache management techniques for large multicore systems. Recently he has started working on pre-fetching and compression techniques for Tiled Chip Multicore Processors.
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Teaching Assistant(s)

Abhijit Das

M.Tech. (Computer Science)

IITG

Dipika Deb

M. Tech (computer science and engineering)

IITG

 Course Duration : Aug-Sep 2018

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 Syllabus

 Enrollment : 18-Apr-2018 to 06-Aug-2018