Module 3 : Introduction to PIC Microcontrollers

Lecture 21 : Timer modules in PIC Microcontroller (contd.)

Timer - 1 Module

Timer 1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L) which are readable and writable. The TMR1 register pair (TMR1H:TMR1L) increments from 0000H to FFFFH and rolls over to 0000H. The TMR1 interrupt, if enabled, is generated on overflow, which sets the interrupt flag bit TMR1IF (bit-0 of PIR1 register). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (bit-0 of the PIE1 register).

The operating and control modes of Timer1 are determined by the special purpose register T1CON.

Various bits of T1CON register are given as follows:-

Fig 21.1  T1CON Register

TMR1 ON :     Timer1 ON bit
                         0 = stops Timer 1;          1 = Enables Timer 1
TMR1CS  :      Timer 1 Clock source Select Bit
                         1 = External Clock (RCO/T1OSO/T1CKI)
                         0 = Internal Clock ( )
:     Timer 1 External Clock Input Synchronization Bit
                          (Valid if TMR1CS = 1)
                          1 - Do not synchronize
                          0 - Synchronize

T1OSCEN:      Oscillator enable control bit
                          1 = Oscillator is enabled
                          0 = Oscillator is shut off

Timer 1 Input Clock Prescaler


Select bits

Prescaler Value















Fig 21.2    Operation of Timer 1

Timer 1 can operate in one of the two modes

  • As a timer (TMR1CS = 0). In the timer mode, Timer 1 increments in every instruction cycle. The timer 1 clock source is . Since the internal clock is selected, the timer is always synchronized and there is no further need of synchronization.
  • As a counter (TMR1CS = 1). In the counter mode, external clock input from the pin RCO/T1CKI is selected.
Reading and writing Timer 1

Reading TMR1H and TMR1L from Timer 1, when it is running from an external clock source, have to be done with care. Reading TMR1H or TMR1L for independent 8 - bit values does not pose any problem. When the 16-bit value of the Timer is required, the high byte (TMR1H) is read first followed by the low byte (THR1lL). It should be ensured that TMR1L does not overflow (that is goes from FFH to 00H) since THR1H was read. This condition is verified by reading TMR1H once again and comparing with previous value of TMR1H.

Example Program
Reading 16bit of free running Timer 1

movf TMR1H              ;              read high byte
movwf TMPH             ;              store in TMPH
movf TMR1L              ;              read low byte
movwf TMPL              ;              store in TMPL
movf TMR1H, W        ;              read high byte in W
subwf TMPH, W        ;              subtract 1 st read with 2 nd read
btfsc STATUS, Z       ;               and check for equality
goto next ;
;  if the high bytes differ, then there is an overflow
;  read the high byte again followed by the low byte
movf TMR1H, W        ;               read high byte
movwf TMPH
movf TMR1L, W         ;               read low byte
movwf TMPL
next : nop

Timer 2 Overview
Fig 21.3   Schematic diagram showing operation of Timer 2

Timer 2 is an 8 - bit timer with a pre-scaler and a post-scaler. It can be used as the PWM time base for PWM mode of capture compare PWM (CCP) modules. The TMR2 register is readable and writable and is cleared on device reset.

The input clock ( ) has a pre-scaler option of 1:1, 1:4 or 1:16 which is selected by bit 0 and bit 1 of T2CON register respectively.

The Timer 2 module has an 8bit period register (PR2). Timer-2 increments from 00H until it is equal to PR2 and then resets to 00H on the next clock cycle. PR2 is a readable and writable register. PR2 is initailised to FFH on reset.

The output of TMR2 goes through a 4bit post-scaler (1:1, 1:2, to 1:16) to generate a TMR2 interrupt by setting TMR2IF.

Fig 21.4  The T2CON Register

Interrupt Logic in PIC 16C74A

PIC 16C74A microcontroller has one vectored interrupt location (i.e., 0004H) but has 12 interrupt sources. There is no interrupt priority. Only one interrupt is served at a time. However interrupts can be masked. The interrupt logic is shown below :

Fig 21.5   Schematic diagram showing the interrupt logic for PIC