| Introduction and Overview of VLSI Design | week1 | week1 | 192 kb |
| Scheduling in High-Level Synthesis | week2 | week2 | 280 kb |
| Resource Sharing and Binding in HLS | week3 | week3 | 201 kb |
| Logic Synthesis and Physical Design | week4 | week4 | 579 kb |
| Introduction to Verification Techniques | week5 | week5 | 379 kb |
| Syntax and semantics of CTL, Equivalences between CTL formulas and Introduction to Model Checking | week6 | week6 | 339 kb |
| CTL Model checking Algorithms and Introduction to Binary Decision Diagrams | week7 | week7 | 387 kb |
| Binary Decision Diagram and Symbolic model checking | week8 | week8 | 233 kb |
| Introduction to Digital Testing | week9 | week9 | 580 kb |
| Fault Simulation and Testability Measures | week10 | week10 | 466 kb |
| Combinational Circuit Test Pattern Generation | week11 | week11 | 432 kb |
| Sequential Circuit Testing and Scan Chains and Built In Self Test (BIST) | week12 | week12 | 507 kb |