Modules / Lectures
Module NameDownloadDescriptionDownload Size
Introduction and Overview of VLSI Designweek1week1192 kb
Scheduling in High-Level Synthesisweek2week2280 kb
Resource Sharing and Binding in HLSweek3week3201 kb
Logic Synthesis and Physical Designweek4week4579 kb
Introduction to Verification Techniquesweek5week5379 kb
Syntax and semantics of CTL, Equivalences between CTL formulas and Introduction to Model Checkingweek6week6339 kb
CTL Model checking Algorithms and Introduction to Binary Decision Diagramsweek7week7387 kb
Binary Decision Diagram and Symbolic model checkingweek8week8233 kb
Introduction to Digital Testingweek9week9580 kb
Fault Simulation and Testability Measuresweek10week10466 kb
Combinational Circuit Test Pattern Generationweek11week11432 kb
Sequential Circuit Testing and Scan Chains and Built In Self Test (BIST)week12week12507 kb