Modules / Lectures

Sl.No Chapter Name English
1Introduction Part-1Download
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2Introduction Part-2Download
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3Overview of VLSI Design FlowDownload
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4High Level Synthesis Overview Part 1Download
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5High Level Synthesis Overview Part 2Download
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6Scheduling in HLS (Part-1)Download
To be verified
7Scheduling in HLS (Part-2) Download
To be verified
8Scheduling in HLS (Part-3) Download
To be verified
9Scheduling in HLS (Part-4)Download
To be verified
10Scheduling in HLS (Part-5)Download
To be verified
11Scheduling in HLS (Part-6)Download
To be verified
12Scheduling in HLS (Part-7)Download
To be verified
13Resource Sharing and Binding in HLS (Part-1)Download
To be verified
14Resource Sharing and Binding in HLS (Part-2)Download
To be verified
15Resource Sharing and Binding in HLS (Part-3)Download
To be verified
16Resource Sharing and Binding in HLS (Part-4)Download
To be verified
17Resource Sharing and Binding in HLS (Part-5)Download
To be verified
18Resource Sharing and Binding in HLS (Part-6)Download
To be verified
19Resource Sharing and Binding in HLS (Part-7)Download
To be verified
20Logic Synthesis (Part-1)Download
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21Logic Synthesis (Part-2)Download
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22Logic Synthesis (Part-3)Download
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23Physical Design (Part-1)Download
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24Physical Design (Part-2)Download
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25Physical Design (Part-3)Download
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26Introduction to formal methods for design verificationDownload
To be verified
27Temporal Logic: Introduction and Basic Operations on Temporal LogicDownload
To be verified
28Syntax and Semantics of CLTDownload
To be verified
29Syntax and semantics of CTL continuedDownload
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30Equivalences between CTL FormulasDownload
To be verified
31Introduction to Model CheckingDownload
To be verified
32Model checking AlgorithmsDownload
To be verified
33Model checking Algorithms continued.Download
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34Model Checking with FairnessDownload
To be verified
35Binary Decision Diagram: Introduction and ConstructionDownload
To be verified
36Ordered Binary Decision Diagram (OBDD)Download
To be verified
37Operation On OBDD Download
To be verified
38OBDD for State Transition Systems EDownload
To be verified
39Symbolic Model CheckingDownload
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40Introduction to Digital VLSI TestingDownload
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41Functional and Structural TestingDownload
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42Fault EquivalenceDownload
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43Fault Simulation IDownload
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44Fault Simulation IIDownload
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45Fault Simulation IIIDownload
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46Testability Measures (SCOAP)Download
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47Introduction to Automatic Test Pattern Generation (ATPG) and ATPG AlgebrasDownload
To be verified
48D-Algorithm IDownload
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49D-Algorithm IIDownload
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50ATPG for Synchronous Sequential Circuits Download
To be verified
51Scan Chain based Sequential Circuit Testing I Download
To be verified
52Scan Chain based Sequential Circuit Testing IIDownload
To be verified
53BIST IDownload
To be verified
54BIST II Download
To be verified


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2BengaliNot Available
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4HindiNot Available
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