1 | Introduction Part-1 | PDF unavailable |
2 | Introduction Part-2 | PDF unavailable |
3 | Overview of VLSI Design Flow | PDF unavailable |
4 | High Level Synthesis Overview Part 1 | PDF unavailable |
5 | High Level Synthesis Overview Part 2 | PDF unavailable |
6 | Scheduling in HLS (Part-1) | PDF unavailable |
7 | Scheduling in HLS (Part-2) | PDF unavailable |
8 | Scheduling in HLS (Part-3) | PDF unavailable |
9 | Scheduling in HLS (Part-4) | PDF unavailable |
10 | Scheduling in HLS (Part-5) | PDF unavailable |
11 | Scheduling in HLS (Part-6) | PDF unavailable |
12 | Scheduling in HLS (Part-7) | PDF unavailable |
13 | Resource Sharing and Binding in HLS (Part-1) | PDF unavailable |
14 | Resource Sharing and Binding in HLS (Part-2) | PDF unavailable |
15 | Resource Sharing and Binding in HLS (Part-3) | PDF unavailable |
16 | Resource Sharing and Binding in HLS (Part-4) | PDF unavailable |
17 | Resource Sharing and Binding in HLS (Part-5) | PDF unavailable |
18 | Resource Sharing and Binding in HLS (Part-6) | PDF unavailable |
19 | Resource Sharing and Binding in HLS (Part-7) | PDF unavailable |
20 | Logic Synthesis (Part-1) | PDF unavailable |
21 | Logic Synthesis (Part-2) | PDF unavailable |
22 | Logic Synthesis (Part-3) | PDF unavailable |
23 | Physical Design (Part-1) | PDF unavailable |
24 | Physical Design (Part-2) | PDF unavailable |
25 | Physical Design (Part-3) | PDF unavailable |
26 | Introduction to formal methods for design verification | PDF unavailable |
27 | Temporal Logic: Introduction and Basic Operations on Temporal Logic | PDF unavailable |
28 | Syntax and Semantics of CLT | PDF unavailable |
29 | Syntax and semantics of CTL continued | PDF unavailable |
30 | Equivalences between CTL Formulas | PDF unavailable |
31 | Introduction to Model Checking | PDF unavailable |
32 | Model checking Algorithms | PDF unavailable |
33 | Model checking Algorithms continued. | PDF unavailable |
34 | Model Checking with Fairness | PDF unavailable |
35 | Binary Decision Diagram: Introduction and Construction | PDF unavailable |
36 | Ordered Binary Decision Diagram (OBDD) | PDF unavailable |
37 | Operation On OBDD | PDF unavailable |
38 | OBDD for State Transition Systems E | PDF unavailable |
39 | Symbolic Model Checking | PDF unavailable |
40 | Introduction to Digital VLSI Testing | PDF unavailable |
41 | Functional and Structural Testing | PDF unavailable |
42 | Fault Equivalence | PDF unavailable |
43 | Fault Simulation I | PDF unavailable |
44 | Fault Simulation II | PDF unavailable |
45 | Fault Simulation III | PDF unavailable |
46 | Testability Measures (SCOAP) | PDF unavailable |
47 | Introduction to Automatic Test Pattern Generation (ATPG) and ATPG Algebras | PDF unavailable |
48 | D-Algorithm I | PDF unavailable |
49 | D-Algorithm II | PDF unavailable |
50 | ATPG for Synchronous Sequential Circuits | PDF unavailable |
51 | Scan Chain based Sequential Circuit Testing I | PDF unavailable |
52 | Scan Chain based Sequential Circuit Testing II | PDF unavailable |
53 | BIST I | PDF unavailable |
54 | BIST II | PDF unavailable |