Modules / Lectures
Module NameDownload
noc21_ee39_assignment_Week_1noc21_ee39_assignment_Week_1
noc21_ee39_assignment_Week_10noc21_ee39_assignment_Week_10
noc21_ee39_assignment_Week_11noc21_ee39_assignment_Week_11
noc21_ee39_assignment_Week_12noc21_ee39_assignment_Week_12
noc21_ee39_assignment_Week_2noc21_ee39_assignment_Week_2
noc21_ee39_assignment_Week_3noc21_ee39_assignment_Week_3
noc21_ee39_assignment_Week_4noc21_ee39_assignment_Week_4
noc21_ee39_assignment_Week_5noc21_ee39_assignment_Week_5
noc21_ee39_assignment_Week_6noc21_ee39_assignment_Week_6
noc21_ee39_assignment_Week_7noc21_ee39_assignment_Week_7
noc21_ee39_assignment_Week_8noc21_ee39_assignment_Week_8
noc21_ee39_assignment_Week_9noc21_ee39_assignment_Week_9


Sl.No Chapter Name MP4 Download
1IntroductionDownload
2Analog vs DigitalDownload
3Binary number system-1Download
4Binary number system-2Download
5Negative number representation-1Download
6Negative number representation-2Download
7Other number systemsDownload
8Floating point number-1Download
9Floating point numbers-2Download
10Floating point numbers-3Download
11Floating point numbers-4Download
12Floating point numbers-5Download
13Boolean functionsDownload
14Boolean AlgebraDownload
15SOP and POS RepresentationDownload
16Algebraic simplificationsDownload
17Canonical formDownload
18Boolean minimization using K-MapsDownload
19More Logic gatesDownload
20Hardware description language:VerilogDownload
21Verilog simulation demoDownload
22K-maps Download
23QM-methodDownload
24Area delay modelDownload
25Multi-level logicDownload
26MultiplexerDownload
27Four state logicDownload
28Decoders-1Download
29Decoders-2Download
30EncodersDownload
31Programmable hardwareDownload
32Ripple carry adderDownload
33Carry look ahead adderDownload
34Modeling BUS in VerilogDownload
35Fast adder:Carry select adderDownload
36Multiple operand adderDownload
37MultiplicationDownload
38Iterative circuits-1Download
39Iterative circuits-2Download
40Introduction to sequential circuitsDownload
41LatchesDownload
42D-Flip-flopsDownload
43More Flip-flopsDownload
44CountersDownload
45Verilog-Behavior model-1Download
46Verilog-Behavior model-2Download
47Registers-1Download
48Registers-2Download
49MemoryDownload
50Sequential circuit analysisDownload
51Derivation state graphDownload
52Sequence detector: Example 1Download
53Sequence detector: Example 2Download
54State machine reductionDownload
55State encodingDownload
56Multi-cycle adder designDownload
57Pipelined adder designDownload
58Multiplication designDownload
59Division hardware designDownload
60Interacting state machinesDownload
61Register Transfer Level designDownload
62GCD computer at RTL LevelDownload
63RTL Design-Bubble sortDownload
64RTL Design - Traffic light controllerDownload
65FPGADownload
66Xilinx CLBDownload
67FPGA - Design flow Download
68FPGA design demoDownload
69Introduction to ASIC design flow Part - 1Download
70Introduction to ASIC design flow Part - 2Download
71Future directionsDownload

Sl.No Chapter Name English
1IntroductionDownload
Verified
2Analog vs DigitalDownload
Verified
3Binary number system-1Download
Verified
4Binary number system-2Download
Verified
5Negative number representation-1Download
Verified
6Negative number representation-2Download
Verified
7Other number systemsDownload
Verified
8Floating point number-1Download
Verified
9Floating point numbers-2Download
Verified
10Floating point numbers-3Download
Verified
11Floating point numbers-4Download
Verified
12Floating point numbers-5Download
Verified
13Boolean functionsDownload
Verified
14Boolean AlgebraDownload
Verified
15SOP and POS RepresentationDownload
Verified
16Algebraic simplificationsDownload
Verified
17Canonical formDownload
Verified
18Boolean minimization using K-MapsDownload
Verified
19More Logic gatesDownload
Verified
20Hardware description language:VerilogDownload
Verified
21Verilog simulation demoDownload
Verified
22K-maps Download
Verified
23QM-methodDownload
Verified
24Area delay modelDownload
Verified
25Multi-level logicDownload
Verified
26MultiplexerDownload
Verified
27Four state logicDownload
Verified
28Decoders-1Download
Verified
29Decoders-2Download
Verified
30EncodersDownload
Verified
31Programmable hardwareDownload
Verified
32Ripple carry adderDownload
Verified
33Carry look ahead adderDownload
Verified
34Modeling BUS in VerilogDownload
Verified
35Fast adder:Carry select adderDownload
Verified
36Multiple operand adderDownload
Verified
37MultiplicationDownload
Verified
38Iterative circuits-1Download
Verified
39Iterative circuits-2Download
Verified
40Introduction to sequential circuitsDownload
Verified
41LatchesDownload
Verified
42D-Flip-flopsDownload
Verified
43More Flip-flopsDownload
Verified
44CountersDownload
Verified
45Verilog-Behavior model-1Download
Verified
46Verilog-Behavior model-2Download
Verified
47Registers-1Download
Verified
48Registers-2Download
Verified
49MemoryDownload
Verified
50Sequential circuit analysisDownload
Verified
51Derivation state graphDownload
Verified
52Sequence detector: Example 1Download
Verified
53Sequence detector: Example 2Download
Verified
54State machine reductionDownload
Verified
55State encodingDownload
Verified
56Multi-cycle adder designDownload
Verified
57Pipelined adder designDownload
Verified
58Multiplication designDownload
Verified
59Division hardware designDownload
Verified
60Interacting state machinesDownload
Verified
61Register Transfer Level designDownload
Verified
62GCD computer at RTL LevelDownload
Verified
63RTL Design-Bubble sortDownload
Verified
64RTL Design - Traffic light controllerDownload
Verified
65FPGADownload
Verified
66Xilinx CLBDownload
Verified
67FPGA - Design flow Download
Verified
68FPGA design demoDownload
Verified
69Introduction to ASIC design flow Part - 1Download
Verified
70Introduction to ASIC design flow Part - 2Download
Verified
71Future directionsDownload
Verified


Sl.No Language Book link
1EnglishNot Available
2BengaliNot Available
3GujaratiNot Available
4HindiNot Available
5KannadaNot Available
6MalayalamNot Available
7MarathiNot Available
8TamilNot Available
9TeluguNot Available