Module Name | Download |
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Sl.No | Chapter Name | MP4 Download |
---|---|---|
1 | Introduction | Download |
2 | Analog vs Digital | Download |
3 | Binary number system-1 | Download |
4 | Binary number system-2 | Download |
5 | Negative number representation-1 | Download |
6 | Negative number representation-2 | Download |
7 | Other number systems | Download |
8 | Floating point number-1 | Download |
9 | Floating point numbers-2 | Download |
10 | Floating point numbers-3 | Download |
11 | Floating point numbers-4 | Download |
12 | Floating point numbers-5 | Download |
13 | Boolean functions | Download |
14 | Boolean Algebra | Download |
15 | SOP and POS Representation | Download |
16 | Algebraic simplifications | Download |
17 | Canonical form | Download |
18 | Boolean minimization using K-Maps | Download |
19 | More Logic gates | Download |
20 | Hardware description language:Verilog | Download |
21 | Verilog simulation demo | Download |
22 | K-maps | Download |
23 | QM-method | Download |
24 | Area delay model | Download |
25 | Multi-level logic | Download |
26 | Multiplexer | Download |
27 | Four state logic | Download |
28 | Decoders-1 | Download |
29 | Decoders-2 | Download |
30 | Encoders | Download |
31 | Programmable hardware | Download |
32 | Ripple carry adder | Download |
33 | Carry look ahead adder | Download |
34 | Modeling BUS in Verilog | Download |
35 | Fast adder:Carry select adder | Download |
36 | Multiple operand adder | Download |
37 | Multiplication | Download |
38 | Iterative circuits-1 | Download |
39 | Iterative circuits-2 | Download |
40 | Introduction to sequential circuits | Download |
41 | Latches | Download |
42 | D-Flip-flops | Download |
43 | More Flip-flops | Download |
44 | Counters | Download |
45 | Verilog-Behavior model-1 | Download |
46 | Verilog-Behavior model-2 | Download |
47 | Registers-1 | Download |
48 | Registers-2 | Download |
49 | Memory | Download |
50 | Sequential circuit analysis | Download |
51 | Derivation state graph | Download |
52 | Sequence detector: Example 1 | Download |
53 | Sequence detector: Example 2 | Download |
54 | State machine reduction | Download |
55 | State encoding | Download |
56 | Multi-cycle adder design | Download |
57 | Pipelined adder design | Download |
58 | Multiplication design | Download |
59 | Division hardware design | Download |
60 | Interacting state machines | Download |
61 | Register Transfer Level design | Download |
62 | GCD computer at RTL Level | Download |
63 | RTL Design-Bubble sort | Download |
64 | RTL Design - Traffic light controller | Download |
65 | FPGA | Download |
66 | Xilinx CLB | Download |
67 | FPGA - Design flow | Download |
68 | FPGA design demo | Download |
69 | Introduction to ASIC design flow Part - 1 | Download |
70 | Introduction to ASIC design flow Part - 2 | Download |
71 | Future directions | Download |
Sl.No | Chapter Name | English |
---|---|---|
1 | Introduction | Download Verified |
2 | Analog vs Digital | Download Verified |
3 | Binary number system-1 | Download Verified |
4 | Binary number system-2 | Download Verified |
5 | Negative number representation-1 | Download Verified |
6 | Negative number representation-2 | Download Verified |
7 | Other number systems | Download Verified |
8 | Floating point number-1 | Download Verified |
9 | Floating point numbers-2 | Download Verified |
10 | Floating point numbers-3 | Download Verified |
11 | Floating point numbers-4 | Download Verified |
12 | Floating point numbers-5 | Download Verified |
13 | Boolean functions | Download Verified |
14 | Boolean Algebra | Download Verified |
15 | SOP and POS Representation | Download Verified |
16 | Algebraic simplifications | Download Verified |
17 | Canonical form | Download Verified |
18 | Boolean minimization using K-Maps | Download Verified |
19 | More Logic gates | Download Verified |
20 | Hardware description language:Verilog | Download Verified |
21 | Verilog simulation demo | Download Verified |
22 | K-maps | Download Verified |
23 | QM-method | PDF unavailable |
24 | Area delay model | PDF unavailable |
25 | Multi-level logic | PDF unavailable |
26 | Multiplexer | PDF unavailable |
27 | Four state logic | PDF unavailable |
28 | Decoders-1 | PDF unavailable |
29 | Decoders-2 | PDF unavailable |
30 | Encoders | PDF unavailable |
31 | Programmable hardware | PDF unavailable |
32 | Ripple carry adder | PDF unavailable |
33 | Carry look ahead adder | PDF unavailable |
34 | Modeling BUS in Verilog | PDF unavailable |
35 | Fast adder:Carry select adder | PDF unavailable |
36 | Multiple operand adder | PDF unavailable |
37 | Multiplication | PDF unavailable |
38 | Iterative circuits-1 | PDF unavailable |
39 | Iterative circuits-2 | PDF unavailable |
40 | Introduction to sequential circuits | PDF unavailable |
41 | Latches | PDF unavailable |
42 | D-Flip-flops | PDF unavailable |
43 | More Flip-flops | PDF unavailable |
44 | Counters | PDF unavailable |
45 | Verilog-Behavior model-1 | PDF unavailable |
46 | Verilog-Behavior model-2 | PDF unavailable |
47 | Registers-1 | PDF unavailable |
48 | Registers-2 | PDF unavailable |
49 | Memory | PDF unavailable |
50 | Sequential circuit analysis | PDF unavailable |
51 | Derivation state graph | PDF unavailable |
52 | Sequence detector: Example 1 | PDF unavailable |
53 | Sequence detector: Example 2 | PDF unavailable |
54 | State machine reduction | PDF unavailable |
55 | State encoding | PDF unavailable |
56 | Multi-cycle adder design | PDF unavailable |
57 | Pipelined adder design | PDF unavailable |
58 | Multiplication design | PDF unavailable |
59 | Division hardware design | PDF unavailable |
60 | Interacting state machines | PDF unavailable |
61 | Register Transfer Level design | PDF unavailable |
62 | GCD computer at RTL Level | PDF unavailable |
63 | RTL Design-Bubble sort | PDF unavailable |
64 | RTL Design - Traffic light controller | PDF unavailable |
65 | FPGA | PDF unavailable |
66 | Xilinx CLB | PDF unavailable |
67 | FPGA - Design flow | PDF unavailable |
68 | FPGA design demo | PDF unavailable |
69 | Introduction to ASIC design flow Part - 1 | PDF unavailable |
70 | Introduction to ASIC design flow Part - 2 | PDF unavailable |
71 | Future directions | PDF unavailable |
Sl.No | Language | Book link |
---|---|---|
1 | English | Not Available |
2 | Bengali | Not Available |
3 | Gujarati | Not Available |
4 | Hindi | Not Available |
5 | Kannada | Not Available |
6 | Malayalam | Not Available |
7 | Marathi | Not Available |
8 | Tamil | Not Available |
9 | Telugu | Not Available |