| Module Name | Download |
|---|---|
| noc21_ee39_assignment_Week_1 | noc21_ee39_assignment_Week_1 |
| noc21_ee39_assignment_Week_10 | noc21_ee39_assignment_Week_10 |
| noc21_ee39_assignment_Week_11 | noc21_ee39_assignment_Week_11 |
| noc21_ee39_assignment_Week_12 | noc21_ee39_assignment_Week_12 |
| noc21_ee39_assignment_Week_2 | noc21_ee39_assignment_Week_2 |
| noc21_ee39_assignment_Week_3 | noc21_ee39_assignment_Week_3 |
| noc21_ee39_assignment_Week_4 | noc21_ee39_assignment_Week_4 |
| noc21_ee39_assignment_Week_5 | noc21_ee39_assignment_Week_5 |
| noc21_ee39_assignment_Week_6 | noc21_ee39_assignment_Week_6 |
| noc21_ee39_assignment_Week_7 | noc21_ee39_assignment_Week_7 |
| noc21_ee39_assignment_Week_8 | noc21_ee39_assignment_Week_8 |
| noc21_ee39_assignment_Week_9 | noc21_ee39_assignment_Week_9 |
| Sl.No | Chapter Name | MP4 Download |
|---|---|---|
| 1 | Introduction | Download |
| 2 | Analog vs Digital | Download |
| 3 | Binary number system-1 | Download |
| 4 | Binary number system-2 | Download |
| 5 | Negative number representation-1 | Download |
| 6 | Negative number representation-2 | Download |
| 7 | Other number systems | Download |
| 8 | Floating point number-1 | Download |
| 9 | Floating point numbers-2 | Download |
| 10 | Floating point numbers-3 | Download |
| 11 | Floating point numbers-4 | Download |
| 12 | Floating point numbers-5 | Download |
| 13 | Boolean functions | Download |
| 14 | Boolean Algebra | Download |
| 15 | SOP and POS Representation | Download |
| 16 | Algebraic simplifications | Download |
| 17 | Canonical form | Download |
| 18 | Boolean minimization using K-Maps | Download |
| 19 | More Logic gates | Download |
| 20 | Hardware description language:Verilog | Download |
| 21 | Verilog simulation demo | Download |
| 22 | K-maps | Download |
| 23 | QM-method | Download |
| 24 | Area delay model | Download |
| 25 | Multi-level logic | Download |
| 26 | Multiplexer | Download |
| 27 | Four state logic | Download |
| 28 | Decoders-1 | Download |
| 29 | Decoders-2 | Download |
| 30 | Encoders | Download |
| 31 | Programmable hardware | Download |
| 32 | Ripple carry adder | Download |
| 33 | Carry look ahead adder | Download |
| 34 | Modeling BUS in Verilog | Download |
| 35 | Fast adder:Carry select adder | Download |
| 36 | Multiple operand adder | Download |
| 37 | Multiplication | Download |
| 38 | Iterative circuits-1 | Download |
| 39 | Iterative circuits-2 | Download |
| 40 | Introduction to sequential circuits | Download |
| 41 | Latches | Download |
| 42 | D-Flip-flops | Download |
| 43 | More Flip-flops | Download |
| 44 | Counters | Download |
| 45 | Verilog-Behavior model-1 | Download |
| 46 | Verilog-Behavior model-2 | Download |
| 47 | Registers-1 | Download |
| 48 | Registers-2 | Download |
| 49 | Memory | Download |
| 50 | Sequential circuit analysis | Download |
| 51 | Derivation state graph | Download |
| 52 | Sequence detector: Example 1 | Download |
| 53 | Sequence detector: Example 2 | Download |
| 54 | State machine reduction | Download |
| 55 | State encoding | Download |
| 56 | Multi-cycle adder design | Download |
| 57 | Pipelined adder design | Download |
| 58 | Multiplication design | Download |
| 59 | Division hardware design | Download |
| 60 | Interacting state machines | Download |
| 61 | Register Transfer Level design | Download |
| 62 | GCD computer at RTL Level | Download |
| 63 | RTL Design-Bubble sort | Download |
| 64 | RTL Design - Traffic light controller | Download |
| 65 | FPGA | Download |
| 66 | Xilinx CLB | Download |
| 67 | FPGA - Design flow | Download |
| 68 | FPGA design demo | Download |
| 69 | Introduction to ASIC design flow Part - 1 | Download |
| 70 | Introduction to ASIC design flow Part - 2 | Download |
| 71 | Future directions | Download |
| Sl.No | Chapter Name | English |
|---|---|---|
| 1 | Introduction | Download Verified |
| 2 | Analog vs Digital | Download Verified |
| 3 | Binary number system-1 | Download Verified |
| 4 | Binary number system-2 | Download Verified |
| 5 | Negative number representation-1 | Download Verified |
| 6 | Negative number representation-2 | Download Verified |
| 7 | Other number systems | Download Verified |
| 8 | Floating point number-1 | Download Verified |
| 9 | Floating point numbers-2 | Download Verified |
| 10 | Floating point numbers-3 | Download Verified |
| 11 | Floating point numbers-4 | Download Verified |
| 12 | Floating point numbers-5 | Download Verified |
| 13 | Boolean functions | Download Verified |
| 14 | Boolean Algebra | Download Verified |
| 15 | SOP and POS Representation | Download Verified |
| 16 | Algebraic simplifications | Download Verified |
| 17 | Canonical form | Download Verified |
| 18 | Boolean minimization using K-Maps | Download Verified |
| 19 | More Logic gates | Download Verified |
| 20 | Hardware description language:Verilog | Download Verified |
| 21 | Verilog simulation demo | Download Verified |
| 22 | K-maps | Download Verified |
| 23 | QM-method | Download Verified |
| 24 | Area delay model | Download Verified |
| 25 | Multi-level logic | Download Verified |
| 26 | Multiplexer | Download Verified |
| 27 | Four state logic | Download Verified |
| 28 | Decoders-1 | Download Verified |
| 29 | Decoders-2 | Download Verified |
| 30 | Encoders | Download Verified |
| 31 | Programmable hardware | Download Verified |
| 32 | Ripple carry adder | Download Verified |
| 33 | Carry look ahead adder | Download Verified |
| 34 | Modeling BUS in Verilog | Download Verified |
| 35 | Fast adder:Carry select adder | Download Verified |
| 36 | Multiple operand adder | Download Verified |
| 37 | Multiplication | Download Verified |
| 38 | Iterative circuits-1 | Download Verified |
| 39 | Iterative circuits-2 | Download Verified |
| 40 | Introduction to sequential circuits | Download Verified |
| 41 | Latches | Download Verified |
| 42 | D-Flip-flops | Download Verified |
| 43 | More Flip-flops | Download Verified |
| 44 | Counters | Download Verified |
| 45 | Verilog-Behavior model-1 | Download Verified |
| 46 | Verilog-Behavior model-2 | Download Verified |
| 47 | Registers-1 | Download Verified |
| 48 | Registers-2 | Download Verified |
| 49 | Memory | Download Verified |
| 50 | Sequential circuit analysis | Download Verified |
| 51 | Derivation state graph | Download Verified |
| 52 | Sequence detector: Example 1 | Download Verified |
| 53 | Sequence detector: Example 2 | Download Verified |
| 54 | State machine reduction | Download Verified |
| 55 | State encoding | Download Verified |
| 56 | Multi-cycle adder design | Download Verified |
| 57 | Pipelined adder design | Download Verified |
| 58 | Multiplication design | Download Verified |
| 59 | Division hardware design | Download Verified |
| 60 | Interacting state machines | Download Verified |
| 61 | Register Transfer Level design | Download Verified |
| 62 | GCD computer at RTL Level | Download Verified |
| 63 | RTL Design-Bubble sort | Download Verified |
| 64 | RTL Design - Traffic light controller | Download Verified |
| 65 | FPGA | Download Verified |
| 66 | Xilinx CLB | Download Verified |
| 67 | FPGA - Design flow | Download Verified |
| 68 | FPGA design demo | Download Verified |
| 69 | Introduction to ASIC design flow Part - 1 | Download Verified |
| 70 | Introduction to ASIC design flow Part - 2 | Download Verified |
| 71 | Future directions | Download Verified |
| Sl.No | Language | Book link |
|---|---|---|
| 1 | English | Not Available |
| 2 | Bengali | Not Available |
| 3 | Gujarati | Not Available |
| 4 | Hindi | Not Available |
| 5 | Kannada | Not Available |
| 6 | Malayalam | Not Available |
| 7 | Marathi | Not Available |
| 8 | Tamil | Not Available |
| 9 | Telugu | Not Available |