Modules / Lectures
Module NameDownload


Sl.No Chapter Name MP4 Download
1IntroductionDownload
2Analog vs DigitalDownload
3Binary number system-1Download
4Binary number system-2Download
5Negative number representation-1Download
6Negative number representation-2Download
7Other number systemsDownload
8Floating point number-1Download
9Floating point numbers-2Download
10Floating point numbers-3Download
11Floating point numbers-4Download
12Floating point numbers-5Download
13Boolean functionsDownload
14Boolean AlgebraDownload
15SOP and POS RepresentationDownload
16Algebraic simplificationsDownload
17Canonical formDownload
18Boolean minimization using K-MapsDownload
19More Logic gatesDownload
20Hardware description language:VerilogDownload
21Verilog simulation demoDownload
22K-maps Download
23QM-methodDownload
24Area delay modelDownload
25Multi-level logicDownload
26MultiplexerDownload
27Four state logicDownload
28Decoders-1Download
29Decoders-2Download
30EncodersDownload
31Programmable hardwareDownload
32Ripple carry adderDownload
33Carry look ahead adderDownload
34Modeling BUS in VerilogDownload
35Fast adder:Carry select adderDownload
36Multiple operand adderDownload
37MultiplicationDownload
38Iterative circuits-1Download
39Iterative circuits-2Download
40Introduction to sequential circuitsDownload
41LatchesDownload
42D-Flip-flopsDownload
43More Flip-flopsDownload
44CountersDownload
45Verilog-Behavior model-1Download
46Verilog-Behavior model-2Download
47Registers-1Download
48Registers-2Download
49MemoryDownload
50Sequential circuit analysisDownload
51Derivation state graphDownload
52Sequence detector: Example 1Download
53Sequence detector: Example 2Download
54State machine reductionDownload
55State encodingDownload
56Multi-cycle adder designDownload
57Pipelined adder designDownload
58Multiplication designDownload
59Division hardware designDownload
60Interacting state machinesDownload
61Register Transfer Level designDownload
62GCD computer at RTL LevelDownload
63RTL Design-Bubble sortDownload
64RTL Design - Traffic light controllerDownload
65FPGADownload
66Xilinx CLBDownload
67FPGA - Design flow Download
68FPGA design demoDownload
69Introduction to ASIC design flow Part - 1Download
70Introduction to ASIC design flow Part - 2Download
71Future directionsDownload

Sl.No Chapter Name English
1IntroductionDownload
Verified
2Analog vs DigitalDownload
Verified
3Binary number system-1Download
Verified
4Binary number system-2Download
Verified
5Negative number representation-1Download
Verified
6Negative number representation-2Download
Verified
7Other number systemsDownload
Verified
8Floating point number-1Download
Verified
9Floating point numbers-2Download
Verified
10Floating point numbers-3Download
Verified
11Floating point numbers-4Download
Verified
12Floating point numbers-5Download
Verified
13Boolean functionsDownload
Verified
14Boolean AlgebraDownload
Verified
15SOP and POS RepresentationDownload
Verified
16Algebraic simplificationsDownload
Verified
17Canonical formDownload
Verified
18Boolean minimization using K-MapsDownload
Verified
19More Logic gatesDownload
Verified
20Hardware description language:VerilogDownload
Verified
21Verilog simulation demoDownload
Verified
22K-maps Download
Verified
23QM-methodDownload
Verified
24Area delay modelDownload
Verified
25Multi-level logicDownload
Verified
26MultiplexerDownload
Verified
27Four state logicDownload
Verified
28Decoders-1Download
Verified
29Decoders-2Download
Verified
30EncodersDownload
Verified
31Programmable hardwareDownload
Verified
32Ripple carry adderDownload
Verified
33Carry look ahead adderDownload
Verified
34Modeling BUS in VerilogDownload
Verified
35Fast adder:Carry select adderDownload
Verified
36Multiple operand adderDownload
Verified
37MultiplicationDownload
Verified
38Iterative circuits-1Download
Verified
39Iterative circuits-2Download
Verified
40Introduction to sequential circuitsPDF unavailable
41LatchesPDF unavailable
42D-Flip-flopsPDF unavailable
43More Flip-flopsPDF unavailable
44CountersPDF unavailable
45Verilog-Behavior model-1PDF unavailable
46Verilog-Behavior model-2PDF unavailable
47Registers-1PDF unavailable
48Registers-2PDF unavailable
49MemoryPDF unavailable
50Sequential circuit analysisPDF unavailable
51Derivation state graphPDF unavailable
52Sequence detector: Example 1PDF unavailable
53Sequence detector: Example 2PDF unavailable
54State machine reductionPDF unavailable
55State encodingPDF unavailable
56Multi-cycle adder designPDF unavailable
57Pipelined adder designPDF unavailable
58Multiplication designPDF unavailable
59Division hardware designPDF unavailable
60Interacting state machinesPDF unavailable
61Register Transfer Level designPDF unavailable
62GCD computer at RTL LevelPDF unavailable
63RTL Design-Bubble sortPDF unavailable
64RTL Design - Traffic light controllerPDF unavailable
65FPGAPDF unavailable
66Xilinx CLBPDF unavailable
67FPGA - Design flow PDF unavailable
68FPGA design demoPDF unavailable
69Introduction to ASIC design flow Part - 1PDF unavailable
70Introduction to ASIC design flow Part - 2PDF unavailable
71Future directionsPDF unavailable


Sl.No Language Book link
1EnglishNot Available
2BengaliNot Available
3GujaratiNot Available
4HindiNot Available
5KannadaNot Available
6MalayalamNot Available
7MarathiNot Available
8TamilNot Available
9TeluguNot Available