Modules / Lectures
Module NameDownload


Sl.No Chapter Name MP4 Download
1Introduction - Digital IC DesignDownload
2PN JunctionDownload
3MOS Capacitor Threshold VoltageDownload
4MOS Transistor Current ExpressionDownload
5Body Effect and I-V PlotsDownload
6Short Channel Transistors - Channel Length ModulationDownload
7Velocity Saturation and Level-1 SPICE ModelDownload
8Drain Induced Barrier LoweringDownload
9Sub-Threshold LeakageDownload
10Substrate and Gate LeakageDownload
11The PMOS TransistorDownload
12Transistor CapacitanceDownload
13Transistor Capacitance Download
14CMOS Inverter ConstructionDownload
15Voltage Transfer CharacteristicsDownload
16Load Line AnalysisDownload
17Trip Point for Short Channel Device InverterDownload
18Trip Point for Long Channel Device Inverter Download
19Noise Margin Analysis-1Download
20Noise Margin Analysis-2Download
21Noise Margin Analysis-3Download
22Noise Margin Analysis-Long Channel Device Inverter-1Download
23Noise Margin Analysis-Long Channel Device Inverter-2Download
24Pass TransistorsDownload
25NMOS Transistor ON Resistance and Fall DelayDownload
26Elmore Delay ModelDownload
27Inverter: Transient ResponseDownload
28Inverter: Dynmaic PowerDownload
29Inverter: Short Circuit PowerDownload
30Inverter: Leakage Power and Transistor StacksDownload
31Stacking Effect and Sleep TransistorsDownload
32Ring Oscillators and Process VariationsDownload
33Implementing Any Boolean Logic FunctionDownload
34Implementing Any Boolean Logic Function: Examples. Gate sizingDownload
35Gate Sizing Download
36Logic Gate CapacitanceDownload
37Gate DelayDownload
38Parasitic DelayDownload
39Gate Delay with a Load CapacitanceDownload
40Logical EffortDownload
41Gate Delay Download
42Path Delay Calculation and Optimization FormulationDownload
43Buffer InsertionDownload
44Input Ordering and Asymmetric GatesDownload
45Skewed GatesDownload
46Special FunctionsDownload
47Pseudo NMOS LogicDownload
48Pseudo NMOS InverterDownload
49Pseudo NMOS Logical Effort and CVSLDownload
50Dynamic Circuits and Input MonotonicityDownload
51Domino Logic and Weak KeepersDownload
52Transmission Gate LogicDownload
53Gate Sizing for Large CircuitsDownload
54Ripple Adder IntroductionDownload
55Full Adder Circuit ImplementationDownload
56Full Adder OptimizationDownload
57Carry Skip AdderDownload
58Carry Select AdderDownload
59Linear and Square Root Carry Select AdderDownload

Sl.No Chapter Name English
1Introduction - Digital IC DesignPDF unavailable
2PN JunctionPDF unavailable
3MOS Capacitor Threshold VoltagePDF unavailable
4MOS Transistor Current ExpressionPDF unavailable
5Body Effect and I-V PlotsPDF unavailable
6Short Channel Transistors - Channel Length ModulationPDF unavailable
7Velocity Saturation and Level-1 SPICE ModelPDF unavailable
8Drain Induced Barrier LoweringPDF unavailable
9Sub-Threshold LeakagePDF unavailable
10Substrate and Gate LeakagePDF unavailable
11The PMOS TransistorPDF unavailable
12Transistor CapacitancePDF unavailable
13Transistor Capacitance PDF unavailable
14CMOS Inverter ConstructionPDF unavailable
15Voltage Transfer CharacteristicsPDF unavailable
16Load Line AnalysisPDF unavailable
17Trip Point for Short Channel Device InverterPDF unavailable
18Trip Point for Long Channel Device Inverter PDF unavailable
19Noise Margin Analysis-1PDF unavailable
20Noise Margin Analysis-2PDF unavailable
21Noise Margin Analysis-3PDF unavailable
22Noise Margin Analysis-Long Channel Device Inverter-1PDF unavailable
23Noise Margin Analysis-Long Channel Device Inverter-2PDF unavailable
24Pass TransistorsPDF unavailable
25NMOS Transistor ON Resistance and Fall DelayPDF unavailable
26Elmore Delay ModelPDF unavailable
27Inverter: Transient ResponsePDF unavailable
28Inverter: Dynmaic PowerPDF unavailable
29Inverter: Short Circuit PowerPDF unavailable
30Inverter: Leakage Power and Transistor StacksPDF unavailable
31Stacking Effect and Sleep TransistorsPDF unavailable
32Ring Oscillators and Process VariationsPDF unavailable
33Implementing Any Boolean Logic FunctionPDF unavailable
34Implementing Any Boolean Logic Function: Examples. Gate sizingPDF unavailable
35Gate Sizing PDF unavailable
36Logic Gate CapacitancePDF unavailable
37Gate DelayPDF unavailable
38Parasitic DelayPDF unavailable
39Gate Delay with a Load CapacitancePDF unavailable
40Logical EffortPDF unavailable
41Gate Delay PDF unavailable
42Path Delay Calculation and Optimization FormulationPDF unavailable
43Buffer InsertionPDF unavailable
44Input Ordering and Asymmetric GatesPDF unavailable
45Skewed GatesPDF unavailable
46Special FunctionsPDF unavailable
47Pseudo NMOS LogicPDF unavailable
48Pseudo NMOS InverterPDF unavailable
49Pseudo NMOS Logical Effort and CVSLPDF unavailable
50Dynamic Circuits and Input MonotonicityPDF unavailable
51Domino Logic and Weak KeepersPDF unavailable
52Transmission Gate LogicPDF unavailable
53Gate Sizing for Large CircuitsPDF unavailable
54Ripple Adder IntroductionPDF unavailable
55Full Adder Circuit ImplementationPDF unavailable
56Full Adder OptimizationPDF unavailable
57Carry Skip AdderPDF unavailable
58Carry Select AdderPDF unavailable
59Linear and Square Root Carry Select AdderPDF unavailable


Sl.No Language Book link
1EnglishNot Available
2BengaliNot Available
3GujaratiNot Available
4HindiNot Available
5KannadaNot Available
6MalayalamNot Available
7MarathiNot Available
8TamilNot Available
9TeluguNot Available