Modules / Lectures
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Lecture NoteDownload as zip file35M
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Sl.No Chapter Name MP4 Download
1Introduction - Digital IC DesignDownload
2PN JunctionDownload
3MOS Capacitor Threshold VoltageDownload
4MOS Transistor Current ExpressionDownload
5Body Effect and I-V PlotsDownload
6Short Channel Transistors - Channel Length ModulationDownload
7Velocity Saturation and Level-1 SPICE ModelDownload
8Drain Induced Barrier LoweringDownload
9Sub-Threshold LeakageDownload
10Substrate and Gate LeakageDownload
11The PMOS TransistorDownload
12Transistor CapacitanceDownload
13Transistor Capacitance Download
14CMOS Inverter ConstructionDownload
15Voltage Transfer CharacteristicsDownload
16Load Line AnalysisDownload
17Trip Point for Short Channel Device InverterDownload
18Trip Point for Long Channel Device Inverter Download
19Noise Margin Analysis-1Download
20Noise Margin Analysis-2Download
21Noise Margin Analysis-3Download
22Noise Margin Analysis-Long Channel Device Inverter-1Download
23Noise Margin Analysis-Long Channel Device Inverter-2Download
24Pass TransistorsDownload
25NMOS Transistor ON Resistance and Fall DelayDownload
26Elmore Delay ModelDownload
27Inverter: Transient ResponseDownload
28Inverter: Dynmaic PowerDownload
29Inverter: Short Circuit PowerDownload
30Inverter: Leakage Power and Transistor StacksDownload
31Stacking Effect and Sleep TransistorsDownload
32Ring Oscillators and Process VariationsDownload
33Implementing Any Boolean Logic FunctionDownload
34Implementing Any Boolean Logic Function: Examples. Gate sizingDownload
35Gate Sizing Download
36Logic Gate CapacitanceDownload
37Gate DelayDownload
38Parasitic DelayDownload
39Gate Delay with a Load CapacitanceDownload
40Logical EffortDownload
41Gate Delay Download
42Path Delay Calculation and Optimization FormulationDownload
43Buffer InsertionDownload
44Input Ordering and Asymmetric GatesDownload
45Skewed GatesDownload
46Special FunctionsDownload
47Pseudo NMOS LogicDownload
48Pseudo NMOS InverterDownload
49Pseudo NMOS Logical Effort and CVSLDownload
50Dynamic Circuits and Input MonotonicityDownload
51Domino Logic and Weak KeepersDownload
52Transmission Gate LogicDownload
53Gate Sizing for Large CircuitsDownload
54Ripple Adder IntroductionDownload
55Full Adder Circuit ImplementationDownload
56Full Adder OptimizationDownload
57Carry Skip AdderDownload
58Carry Select AdderDownload
59Linear and Square Root Carry Select AdderDownload
60Two's Complement ArithmeticDownload
61Two's Complement Sign ExtensionDownload
62Array MultiplierDownload
63Array Multiplier - Timing AnalysisDownload
64Carry Save MultiplierDownload
65Carry Save Multiplier - Signed MultiplicationDownload
66Introduction to PipeliningDownload
67Time BorrowingDownload
68Master Slave Flip FlopDownload
69Flop Timing ParametersDownload
70Alternate Circuit ImplementationsDownload
71Clock OverlapDownload
72C2MOS FlopDownload
73Max and Min Delay of Flop Based SystemsDownload
74Flop Min Delay ConstraintDownload
75Latch - Max and Min Delay ConstraintsDownload
76Latch-Timing Analysis with SkewDownload
77Time Borrowing Download

Sl.No Chapter Name English
1Introduction - Digital IC DesignDownload
To be verified
2PN JunctionDownload
To be verified
3MOS Capacitor Threshold VoltageDownload
To be verified
4MOS Transistor Current ExpressionDownload
To be verified
5Body Effect and I-V PlotsDownload
To be verified
6Short Channel Transistors - Channel Length ModulationDownload
To be verified
7Velocity Saturation and Level-1 SPICE ModelDownload
To be verified
8Drain Induced Barrier LoweringDownload
To be verified
9Sub-Threshold LeakageDownload
To be verified
10Substrate and Gate LeakageDownload
To be verified
11The PMOS TransistorDownload
To be verified
12Transistor CapacitanceDownload
To be verified
13Transistor Capacitance Download
To be verified
14CMOS Inverter ConstructionDownload
To be verified
15Voltage Transfer CharacteristicsDownload
To be verified
16Load Line AnalysisDownload
To be verified
17Trip Point for Short Channel Device InverterDownload
To be verified
18Trip Point for Long Channel Device Inverter Download
To be verified
19Noise Margin Analysis-1Download
To be verified
20Noise Margin Analysis-2Download
To be verified
21Noise Margin Analysis-3Download
To be verified
22Noise Margin Analysis-Long Channel Device Inverter-1Download
To be verified
23Noise Margin Analysis-Long Channel Device Inverter-2Download
To be verified
24Pass TransistorsDownload
To be verified
25NMOS Transistor ON Resistance and Fall DelayDownload
To be verified
26Elmore Delay ModelDownload
To be verified
27Inverter: Transient ResponseDownload
To be verified
28Inverter: Dynmaic PowerDownload
To be verified
29Inverter: Short Circuit PowerDownload
To be verified
30Inverter: Leakage Power and Transistor StacksDownload
To be verified
31Stacking Effect and Sleep TransistorsDownload
To be verified
32Ring Oscillators and Process VariationsDownload
To be verified
33Implementing Any Boolean Logic FunctionDownload
To be verified
34Implementing Any Boolean Logic Function: Examples. Gate sizingDownload
To be verified
35Gate Sizing Download
To be verified
36Logic Gate CapacitanceDownload
To be verified
37Gate DelayDownload
To be verified
38Parasitic DelayDownload
To be verified
39Gate Delay with a Load CapacitanceDownload
To be verified
40Logical EffortDownload
To be verified
41Gate Delay Download
To be verified
42Path Delay Calculation and Optimization FormulationDownload
To be verified
43Buffer InsertionDownload
To be verified
44Input Ordering and Asymmetric GatesDownload
To be verified
45Skewed GatesDownload
To be verified
46Special FunctionsDownload
To be verified
47Pseudo NMOS LogicDownload
To be verified
48Pseudo NMOS InverterDownload
To be verified
49Pseudo NMOS Logical Effort and CVSLDownload
To be verified
50Dynamic Circuits and Input MonotonicityDownload
To be verified
51Domino Logic and Weak KeepersDownload
To be verified
52Transmission Gate LogicDownload
To be verified
53Gate Sizing for Large CircuitsDownload
To be verified
54Ripple Adder IntroductionDownload
To be verified
55Full Adder Circuit ImplementationDownload
To be verified
56Full Adder OptimizationDownload
To be verified
57Carry Skip AdderDownload
To be verified
58Carry Select AdderDownload
To be verified
59Linear and Square Root Carry Select AdderDownload
To be verified
60Two's Complement ArithmeticDownload
To be verified
61Two's Complement Sign ExtensionDownload
To be verified
62Array MultiplierDownload
To be verified
63Array Multiplier - Timing AnalysisDownload
To be verified
64Carry Save MultiplierDownload
To be verified
65Carry Save Multiplier - Signed MultiplicationDownload
To be verified
66Introduction to PipeliningDownload
To be verified
67Time BorrowingDownload
To be verified
68Master Slave Flip FlopDownload
To be verified
69Flop Timing ParametersDownload
To be verified
70Alternate Circuit ImplementationsDownload
To be verified
71Clock OverlapDownload
To be verified
72C2MOS FlopDownload
To be verified
73Max and Min Delay of Flop Based SystemsDownload
To be verified
74Flop Min Delay ConstraintDownload
To be verified
75Latch - Max and Min Delay ConstraintsDownload
To be verified
76Latch-Timing Analysis with SkewDownload
To be verified
77Time Borrowing Download
To be verified


Sl.No Language Book link
1EnglishNot Available
2BengaliNot Available
3GujaratiNot Available
4HindiNot Available
5KannadaNot Available
6MalayalamNot Available
7MarathiNot Available
8TamilNot Available
9TeluguNot Available