Modules / Lectures
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Sl.No Chapter Name MP4 Download
1Lecture 01: Introduction Download
2Lecture 02: Transistor as a switchDownload
3Lecture 03: Performance Issues and Introduction to TTLDownload
4Lecture 04: Transistor Transistor Logic (TTL)Download
5Lecture 05: CMOS LogicDownload
6Lecture 06: Basic Gates and their representationsDownload
7Lecture 07: Fundamentals of Boolean AlgebraDownload
8Lecture 08: Boolean Function to Truth Table and Implementaion IssuesDownload
9Lecture 09: Truth Table to Boolean Function and Implementaion IssuesDownload
10Lecture 10: Karnugh Map and Digital Circuit RealizationDownload
11Lecture 11: Karnaugh Map to Entered Variable MapDownload
12Lecture 12: Quine - McClusky (QM) Algorithm Download
13Lecture13: Cost Criteria and Minimization of Multiple Output FunctionsDownload
14Lecture 14: Static 1 HazardDownload
15Lecture 15: Static 0 Hazard and Dynamic HazardDownload
16Lecture 16 : Multiplexer: Part IDownload
17Lecture 17 : Multiplexer: Part IIDownload
18Lecture 18 : Demultiplexer / DecoderDownload
19Lecture 19 : Decoder with BCD Input and EncoderDownload
20Lecture 20 : Parity Generator and CheckerDownload
21Lecture 21 : Number SystemDownload
22Lecture 22 : Negative Number and 2’s Complement ArithmeticDownload
23Lecture 23 : Arithmetic Building Blocks - IDownload
24Lecture 24 : Arithmetic Building Blocks - IIDownload
25Lecture 25 : Overflow Detection and BCD ArithmeticDownload
26Lecture 26 : Magnitude ComparatorDownload
27Lecture 27 : Arithmetic Logic Unit (ALU)Download
28Lecture 28 : Unweighted CodeDownload
29Lecture 29 : Error Detection and Correction CodeDownload
30Lecture 30 : Multiplication and DivisionDownload
31Lecture 31: SR Latch and Introduction to Clocked Flip-FlopDownload
32Lecture 32: Edge-Triggered Flip-FlopDownload
33Lecture 33: Representations of Flip-FlopsDownload
34Lecture 34: Analysis of Sequential Logic CircuitDownload
35Lecture 35: Conversion of Flip-Flops and Flip-Flop Timing ParametersDownload
36Lecture 36: Register and Shift Register: PIPO and SISODownload
37Lecture 37: Shift Register: SIPO, PISO and Universal Shift RegisterDownload
38Lecture 38: Application of Shift RegisterDownload
39Lecture 39: Linear Feedback Shift RegisterDownload
40Lecture 40: Serial Addition, Multiplication and DivisionDownload
41Lecture 41: Asynchronous CounterDownload
42Lecture 42: Decoding Logic and Synchronous CounterDownload
43Lecture 43: Cascading: Mod 2, 3, 5 to Mod 6, 10, 1000 CounterDownload
44Lecture 44: Counter Design with Asynchronous Reset and PresetDownload
45Lecture 45: Counter Design as Synthesis Problem and Few Other Uses of CounterDownload
46Lecture 46 : Synthesis of Sequential Logic Circuit: Moore Model and Mealy ModelDownload
47Lecture 47 : Moore Model and Mealy Model: Realization of Digital Logic CircuitDownload
48Lecture 48 : Algorithmic State Machine (ASM) Chart and Synthesis of Sequential Logic CircuitDownload
49Lecture 49 : Circuit Realization from ASM Chart and State MinimizationDownload
50Lecture 50 : State Minimization by Implication Table and Partitioning MethodDownload
51Lecture 51 : Digital to Analog Conversion - IDownload
52Lecture 52 : Digital to Analog Conversion - IIDownload
53Lecture 53 : Analog to Digital Conversion - IDownload
54Lecture 54 : Analog to Digital Conversion - IIDownload
55Lecture 55 : Certain Performance Issue of ADC and DACDownload
56Lecture 56: Introduction to MemoryDownload
57Lecture 57: Static Random Access Memory (SRAM)Download
58Lecture 58: Dynamic RAM(DRAM) and Memory ExpansionDownload
59Lecture 59: Read Only Memory (ROM)Download
60Lecture 60: PAL, PLA, CPLD, FPGADownload

Sl.No Chapter Name English
1Lecture 01: Introduction Download
Verified
2Lecture 02: Transistor as a switchDownload
Verified
3Lecture 03: Performance Issues and Introduction to TTLDownload
Verified
4Lecture 04: Transistor Transistor Logic (TTL)Download
Verified
5Lecture 05: CMOS LogicDownload
Verified
6Lecture 06: Basic Gates and their representationsDownload
Verified
7Lecture 07: Fundamentals of Boolean AlgebraDownload
Verified
8Lecture 08: Boolean Function to Truth Table and Implementaion IssuesDownload
Verified
9Lecture 09: Truth Table to Boolean Function and Implementaion IssuesDownload
Verified
10Lecture 10: Karnugh Map and Digital Circuit RealizationDownload
Verified
11Lecture 11: Karnaugh Map to Entered Variable MapDownload
Verified
12Lecture 12: Quine - McClusky (QM) Algorithm Download
Verified
13Lecture13: Cost Criteria and Minimization of Multiple Output FunctionsDownload
Verified
14Lecture 14: Static 1 HazardDownload
Verified
15Lecture 15: Static 0 Hazard and Dynamic HazardDownload
Verified
16Lecture 16 : Multiplexer: Part IDownload
Verified
17Lecture 17 : Multiplexer: Part IIDownload
Verified
18Lecture 18 : Demultiplexer / DecoderDownload
Verified
19Lecture 19 : Decoder with BCD Input and EncoderDownload
Verified
20Lecture 20 : Parity Generator and CheckerDownload
Verified
21Lecture 21 : Number SystemDownload
Verified
22Lecture 22 : Negative Number and 2’s Complement ArithmeticDownload
Verified
23Lecture 23 : Arithmetic Building Blocks - IDownload
Verified
24Lecture 24 : Arithmetic Building Blocks - IIDownload
Verified
25Lecture 25 : Overflow Detection and BCD ArithmeticDownload
Verified
26Lecture 26 : Magnitude ComparatorDownload
Verified
27Lecture 27 : Arithmetic Logic Unit (ALU)Download
Verified
28Lecture 28 : Unweighted CodeDownload
Verified
29Lecture 29 : Error Detection and Correction CodeDownload
Verified
30Lecture 30 : Multiplication and DivisionDownload
Verified
31Lecture 31: SR Latch and Introduction to Clocked Flip-FlopDownload
Verified
32Lecture 32: Edge-Triggered Flip-FlopDownload
Verified
33Lecture 33: Representations of Flip-FlopsDownload
Verified
34Lecture 34: Analysis of Sequential Logic CircuitDownload
Verified
35Lecture 35: Conversion of Flip-Flops and Flip-Flop Timing ParametersDownload
Verified
36Lecture 36: Register and Shift Register: PIPO and SISODownload
Verified
37Lecture 37: Shift Register: SIPO, PISO and Universal Shift RegisterDownload
Verified
38Lecture 38: Application of Shift RegisterDownload
Verified
39Lecture 39: Linear Feedback Shift RegisterDownload
Verified
40Lecture 40: Serial Addition, Multiplication and DivisionDownload
Verified
41Lecture 41: Asynchronous CounterDownload
Verified
42Lecture 42: Decoding Logic and Synchronous CounterDownload
Verified
43Lecture 43: Cascading: Mod 2, 3, 5 to Mod 6, 10, 1000 CounterDownload
Verified
44Lecture 44: Counter Design with Asynchronous Reset and PresetDownload
Verified
45Lecture 45: Counter Design as Synthesis Problem and Few Other Uses of CounterDownload
Verified
46Lecture 46 : Synthesis of Sequential Logic Circuit: Moore Model and Mealy ModelDownload
Verified
47Lecture 47 : Moore Model and Mealy Model: Realization of Digital Logic CircuitDownload
Verified
48Lecture 48 : Algorithmic State Machine (ASM) Chart and Synthesis of Sequential Logic CircuitDownload
Verified
49Lecture 49 : Circuit Realization from ASM Chart and State MinimizationDownload
Verified
50Lecture 50 : State Minimization by Implication Table and Partitioning MethodDownload
Verified
51Lecture 51 : Digital to Analog Conversion - IDownload
Verified
52Lecture 52 : Digital to Analog Conversion - IIDownload
Verified
53Lecture 53 : Analog to Digital Conversion - IDownload
Verified
54Lecture 54 : Analog to Digital Conversion - IIDownload
Verified
55Lecture 55 : Certain Performance Issue of ADC and DACDownload
Verified
56Lecture 56: Introduction to MemoryDownload
Verified
57Lecture 57: Static Random Access Memory (SRAM)Download
Verified
58Lecture 58: Dynamic RAM(DRAM) and Memory ExpansionDownload
Verified
59Lecture 59: Read Only Memory (ROM)Download
Verified
60Lecture 60: PAL, PLA, CPLD, FPGADownload
Verified


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2BengaliNot Available
3GujaratiNot Available
4HindiNot Available
5KannadaNot Available
6MalayalamNot Available
7MarathiNot Available
8TamilNot Available
9TeluguNot Available