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noc20-ee37_Week_03_Assignment_01noc20-ee37_Week_03_Assignment_01
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noc20-ee37_Week_04_Assignment_01noc20-ee37_Week_04_Assignment_01
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Sl.No Chapter Name MP4 Download
1Lecture 1 : Introduction to VLSI Design FlowDownload
2Lecture 2 : Introduction to VLSI Design FlowDownload
3Lecture 3 : Introduction to VLSI Design FlowDownload
4Lecture 4 : Algorithm to Efficient Architecture MappingDownload
5Lecture 5 : Algorithm to Efficient Architecture Mapping(Contd.)Download
6Lecture 6 : Algorithm to Efficient Architecture Mapping(Contd.Download
7Lecture 7 : Tutorial on Algorithm to Efficient Architecture MappingDownload
8Lecture 8 : Algorithm to Efficient Architecture Mapping(Contd.Download
9Lecture 9 : Algorithm to Efficient Architecture Mapping(Contd.Download
10Lecture 10 : Algorithm to Efficient Architecture Mapping(Contd.Download
11Lecture 11 : Algorithm to Efficient Architecture Mapping(Contd.Download
12Lecture 12 : Algorithm to Efficient Architecture Mapping(Contd.Download
13Lecture 13 : Algorithm to Efficient Architecture MappingDownload
14Lecture 14 : Algorithm to Efficient Architecture Mapping(Contd.)Download
15Lecture 15 : Efficient Adder ArchitectureDownload
16Lecture 16 : Efficient Adder Architecture (Contd.)Download
17Lecture 17 : Efficient Adder Architecture (Contd.)Download
18Lecture 18 : Efficient Adder ArchitectureDownload
19Lecture 19 : Efficient Adder ArchitectureDownload
20Lecture 20 : Efficient Adder ArchitectureDownload
21Lecture 21 : Efficient Adder ArchitectureDownload
22Lecture 22 : Efficient Adder ArchitectureDownload
23Lecture 23 : Efficient Adder ArchitectureDownload
24Lecture 24 : Efficient Adder ArchitectureDownload
25Lecture 25 : Pipelining and Parallel ProcessingDownload
26Lecture 26 : Pipelining and Parallel ProcessingDownload
27Lecture 27 : Multiplier ArchitectureDownload
28Lecture 28 : Multiplier ArchitectureDownload
29Lecture 29 : Multiplier ArchitectureDownload
30Lecture 30 : Multiplier ArchitectureDownload
31Lecture 31: Multiplier ArchitectureDownload
32Lecture 32: Multiplier ArchitectureDownload
33Lecture 33: Multiplier ArchitectureDownload
34Lecture 34: Multiplier ArchitectureDownload
35Lecture 35: Squaring Circuit DesignDownload
36Lecture 36: Reconfigurable Constant Multiplier DesignDownload
37Lecture 37 : Reconfigurable Constant Multiplier DesignDownload
38Lecture 38 : Reconfigurable Constant Multiplier DesignDownload
39Lecture 39 : Fixed Point Number RepresentationDownload
40Lecture 40 : Fixed Point Number RepresentationDownload
41Lecture 41 : CORDIC ArchitectureDownload
42Lecture 42 : CORDIC ArchitectureDownload
43Lecture 43 : CORDIC ArchitectureDownload
44Lecture 44 : CORDIC ArchitectureDownload
45Lecture 45 : Timing AnalysisDownload
46Lecture 46 : Timing AnalysisDownload
47Lecture 47 : Timing AnalysisDownload
48Lecture 48 : Logic HazardDownload
49Lecture 49: FFT ArchitectureDownload
50Lecture 50: FFT Architecture (Contd.)Download
51Lecture 51: Timing analysis BasicsDownload
52Lecture 52: Timing analysis Basics (Contd.)Download
53Lecture 53: Timing analysis Basics (Contd.)Download
54Lecture 54: Timing Issuesin Digital IC DesignDownload
55Lecture 55: Timing Issuesin Digital IC Design (Contd.)Download
56Lecture 56: Timing Issuesin Digital IC Design (Contd.)Download
57Lecture 57: Timing Issuesin Digital IC Design (Contd.)Download
58Lecture 58: Architectural Design of Digital Integrated CircuitsDownload
59Lecture 59: Design Tips for Basic Circuits Design ( Contd. )Download
60Lecture 60: Design Tips for Basic Circuits Design ( Contd. )Download
61Lecture 61: Design Tips for Basic Circuits Design ( Contd. )Download
62Lecture 62: Low Power Digital DesignDownload
63Lecture 63: Low Power Digital Design ( Contd. )Download
64Lecture 64: Low Power Digital Design Download
65Lecture 65: Low Power Digital Design ( Contd. )Download
66Lecture 66: Hardware for Machine Learning : Design Considerations Design TipsDownload
67Lecture 67: Hardware for Machine Learning : Design Considerations Design Tips ( Contd. )Download

Sl.No Chapter Name English
1Lecture 1 : Introduction to VLSI Design FlowDownload
To be verified
2Lecture 2 : Introduction to VLSI Design FlowDownload
To be verified
3Lecture 3 : Introduction to VLSI Design FlowDownload
To be verified
4Lecture 4 : Algorithm to Efficient Architecture MappingDownload
To be verified
5Lecture 5 : Algorithm to Efficient Architecture Mapping(Contd.)Download
To be verified
6Lecture 6 : Algorithm to Efficient Architecture Mapping(Contd.Download
To be verified
7Lecture 7 : Tutorial on Algorithm to Efficient Architecture MappingDownload
To be verified
8Lecture 8 : Algorithm to Efficient Architecture Mapping(Contd.Download
To be verified
9Lecture 9 : Algorithm to Efficient Architecture Mapping(Contd.Download
To be verified
10Lecture 10 : Algorithm to Efficient Architecture Mapping(Contd.Download
To be verified
11Lecture 11 : Algorithm to Efficient Architecture Mapping(Contd.Download
To be verified
12Lecture 12 : Algorithm to Efficient Architecture Mapping(Contd.Download
To be verified
13Lecture 13 : Algorithm to Efficient Architecture MappingDownload
To be verified
14Lecture 14 : Algorithm to Efficient Architecture Mapping(Contd.)Download
To be verified
15Lecture 15 : Efficient Adder ArchitectureDownload
To be verified
16Lecture 16 : Efficient Adder Architecture (Contd.)Download
To be verified
17Lecture 17 : Efficient Adder Architecture (Contd.)Download
To be verified
18Lecture 18 : Efficient Adder ArchitectureDownload
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19Lecture 19 : Efficient Adder ArchitectureDownload
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20Lecture 20 : Efficient Adder ArchitectureDownload
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21Lecture 21 : Efficient Adder ArchitectureDownload
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22Lecture 22 : Efficient Adder ArchitectureDownload
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23Lecture 23 : Efficient Adder ArchitectureDownload
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24Lecture 24 : Efficient Adder ArchitectureDownload
To be verified
25Lecture 25 : Pipelining and Parallel ProcessingDownload
To be verified
26Lecture 26 : Pipelining and Parallel ProcessingDownload
To be verified
27Lecture 27 : Multiplier ArchitectureDownload
To be verified
28Lecture 28 : Multiplier ArchitectureDownload
To be verified
29Lecture 29 : Multiplier ArchitectureDownload
To be verified
30Lecture 30 : Multiplier ArchitectureDownload
To be verified
31Lecture 31: Multiplier ArchitectureDownload
To be verified
32Lecture 32: Multiplier ArchitectureDownload
To be verified
33Lecture 33: Multiplier ArchitectureDownload
To be verified
34Lecture 34: Multiplier ArchitectureDownload
To be verified
35Lecture 35: Squaring Circuit DesignDownload
To be verified
36Lecture 36: Reconfigurable Constant Multiplier DesignDownload
To be verified
37Lecture 37 : Reconfigurable Constant Multiplier DesignDownload
To be verified
38Lecture 38 : Reconfigurable Constant Multiplier DesignDownload
To be verified
39Lecture 39 : Fixed Point Number RepresentationDownload
To be verified
40Lecture 40 : Fixed Point Number RepresentationDownload
To be verified
41Lecture 41 : CORDIC ArchitectureDownload
To be verified
42Lecture 42 : CORDIC ArchitectureDownload
To be verified
43Lecture 43 : CORDIC ArchitectureDownload
To be verified
44Lecture 44 : CORDIC ArchitectureDownload
To be verified
45Lecture 45 : Timing AnalysisDownload
To be verified
46Lecture 46 : Timing AnalysisDownload
To be verified
47Lecture 47 : Timing AnalysisDownload
To be verified
48Lecture 48 : Logic HazardDownload
To be verified
49Lecture 49: FFT ArchitectureDownload
To be verified
50Lecture 50: FFT Architecture (Contd.)Download
To be verified
51Lecture 51: Timing analysis BasicsDownload
To be verified
52Lecture 52: Timing analysis Basics (Contd.)Download
To be verified
53Lecture 53: Timing analysis Basics (Contd.)Download
To be verified
54Lecture 54: Timing Issuesin Digital IC DesignDownload
To be verified
55Lecture 55: Timing Issuesin Digital IC Design (Contd.)Download
To be verified
56Lecture 56: Timing Issuesin Digital IC Design (Contd.)Download
To be verified
57Lecture 57: Timing Issuesin Digital IC Design (Contd.)Download
To be verified
58Lecture 58: Architectural Design of Digital Integrated CircuitsDownload
To be verified
59Lecture 59: Design Tips for Basic Circuits Design ( Contd. )Download
To be verified
60Lecture 60: Design Tips for Basic Circuits Design ( Contd. )Download
To be verified
61Lecture 61: Design Tips for Basic Circuits Design ( Contd. )Download
To be verified
62Lecture 62: Low Power Digital DesignDownload
To be verified
63Lecture 63: Low Power Digital Design ( Contd. )Download
To be verified
64Lecture 64: Low Power Digital Design Download
To be verified
65Lecture 65: Low Power Digital Design ( Contd. )Download
To be verified
66Lecture 66: Hardware for Machine Learning : Design Considerations Design TipsDownload
To be verified
67Lecture 67: Hardware for Machine Learning : Design Considerations Design Tips ( Contd. )Download
To be verified


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3GujaratiNot Available
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