Sl.No Chapter Name MP4 Download
1Lec 1: Verilog Operators and ModulesDownload
2Lec 2: Verilog Ports, Data types and AssignmentsDownload
3Lec 3: Basics of gate level modelingDownload
4Lec 4: Half adder, full adder and ripple carry adderDownload
5Lec 5: Parallel adder/subtractorDownload
6Lec 6: Multiplier and comparatorDownload
7Lec 7: Decoder, encoder and multiplexerDownload
8Lec 8: Demultiplexer, read only memoryDownload
9Lec 9: Review of flip-flopsDownload
10Lec 10: Verilog modeling of flip-flopsDownload
11Lec 11: Modeling of CMOS gates and Boolean functionsDownload
12Lec 12: Modeling using transmission gates, CMOS dalay timesDownload
13Lec 13: Signal strengthsDownload
14Lec 14: Basics of dataflow modelingDownload
15Lec 15: Examples of dataflow modelingDownload
16Lec 16: Basics of behavioral modelingDownload
17Lec 17: Examples of behavioral modelingDownload
18Lec 18: Verilog modeling of countersDownload
19Lec 19: Verilog modeling of sequence detectorDownload
20Lec 20: Verilog modeling FSMs and shift registersDownload
21Lec 21: Combinational circuit examplesDownload
22Lec 22: Sequential circuit examplesDownload
23Lec 23: Arithmetic and Logic Unit (ALU)Download
24Lec 24: Static RAM and Braun MultiplierDownload
25Lec 25: FIR filter implementationDownload
26Lec 26: Baugh-Wooley signed multiplier architectureDownload
27Lec 27: IIR filter implementationDownload

Sl.No Chapter Name English
1Lec 1: Verilog Operators and ModulesDownload
Verified
2Lec 2: Verilog Ports, Data types and AssignmentsDownload
Verified
3Lec 3: Basics of gate level modelingDownload
Verified
4Lec 4: Half adder, full adder and ripple carry adderDownload
Verified
5Lec 5: Parallel adder/subtractorDownload
Verified
6Lec 6: Multiplier and comparatorDownload
Verified
7Lec 7: Decoder, encoder and multiplexerDownload
Verified
8Lec 8: Demultiplexer, read only memoryDownload
Verified
9Lec 9: Review of flip-flopsDownload
Verified
10Lec 10: Verilog modeling of flip-flopsDownload
Verified
11Lec 11: Modeling of CMOS gates and Boolean functionsDownload
Verified
12Lec 12: Modeling using transmission gates, CMOS dalay timesDownload
Verified
13Lec 13: Signal strengthsDownload
Verified
14Lec 14: Basics of dataflow modelingPDF unavailable
15Lec 15: Examples of dataflow modelingPDF unavailable
16Lec 16: Basics of behavioral modelingPDF unavailable
17Lec 17: Examples of behavioral modelingPDF unavailable
18Lec 18: Verilog modeling of countersPDF unavailable
19Lec 19: Verilog modeling of sequence detectorPDF unavailable
20Lec 20: Verilog modeling FSMs and shift registersPDF unavailable
21Lec 21: Combinational circuit examplesPDF unavailable
22Lec 22: Sequential circuit examplesPDF unavailable
23Lec 23: Arithmetic and Logic Unit (ALU)PDF unavailable
24Lec 24: Static RAM and Braun MultiplierPDF unavailable
25Lec 25: FIR filter implementationPDF unavailable
26Lec 26: Baugh-Wooley signed multiplier architecturePDF unavailable
27Lec 27: IIR filter implementationPDF unavailable


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