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Sl.No Chapter Name English
1Introduction to Digital VLSI Design FlowPDF unavailable
2High-level Synthesis (HLS) flow with an examplePDF unavailable
3Automation of High-level Synthesis Steps PDF unavailable
4Impact of Coding Style on HLS Results PDF unavailable
5Impact of Compiler Optimizations on HLS ResultsPDF unavailable
6RTL Optimizations for TimingPDF unavailable
7RetimingPDF unavailable
8RTL Optimizations for AreaPDF unavailable
9RTL Optimizations for PowerPDF unavailable
10High Level Synthesis: Introduction to Logic SynthesisPDF unavailable
11Overview of FPGA Technology MappingPDF unavailable
12 Introduction to Physical SynthesisPDF unavailable
13Introduction to Digital VLSI Testing-IPDF unavailable
14Introduction to Digital VLSI Testing-IIPDF unavailable
15Optimization Techniques for ATPGPDF unavailable
16Optimization Techniques for ATPG [Part II]PDF unavailable
17Optimization Techniques for Design for TestabilityPDF unavailable
18High-level fault modeling and RTL level TestingPDF unavailable
19LTL/CTL based VerificationPDF unavailable
20Verification of Large Scale SystemsPDF unavailable
21BDD based verificationPDF unavailable
22Verification: ADD based verification, HDD based verificationPDF unavailable
23Verification: Symbolic Model CheckingPDF unavailable
24Verification: Bounded Model CheckingPDF unavailable

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