Modules / Lectures

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noc19_cs74_assessment_id_Week_11noc19_cs74_assessment_id_Week_11
noc19_cs74_assessment_id_Week_12noc19_cs74_assessment_id_Week_12
noc19_cs74_assessment_id_Week_2noc19_cs74_assessment_id_Week_2
noc19_cs74_assessment_id_Week_3noc19_cs74_assessment_id_Week_3
noc19_cs74_assessment_id_Week_4noc19_cs74_assessment_id_Week_4
noc19_cs74_assessment_id_Week_5noc19_cs74_assessment_id_Week_5
noc19_cs74_assessment_id_Week_6noc19_cs74_assessment_id_Week_6
noc19_cs74_assessment_id_Week_7noc19_cs74_assessment_id_Week_7
noc19_cs74_assessment_id_Week_8noc19_cs74_assessment_id_Week_8
noc19_cs74_assessment_id_Week_9noc19_cs74_assessment_id_Week_9


Sl.No Chapter Name MP4 Download
1Lecture 01: IntroductionDownload
2Lecture 02: Octal and Hexadecimal Number SystemsDownload
3Lecture 03: Signed and Unsigned Binary Number RepresentationDownload
4Lecture 04: Binary Addition and SubtractionDownload
5Lecture 05: BCD and Gray Code RepresentationsDownload
6Lecture 06: Error Detection and CorrectionDownload
7Lecture 07: Logic GatesDownload
8Lecture 08: Logic Families to Implement GatesDownload
9Lecture 09: Emerging Technologies (Part I)Download
10Lecture 10: Emerging Technologies (Part II)Download
11Lecture 11 : Switching AlgebraDownload
12Lecture 12 : Algebraic ManipulationDownload
13Lecture 13 : Properties of Switching FunctionsDownload
14Lecture 14 : Obtaining Canonical Representations of FunctionsDownload
15Lecture 15 : Functional CompletenessDownload
16Lecture 16: Minimization Using Karnaugh Maps (Part I)Download
17Lecture 17: Minimization Using Karnaugh Maps (Part II)Download
18Lecture 21: Design of Adders (Part I)Download
19Lecture 22: Design of Adders (Part II)Download
20Lecture 23: Design of Adders (Part III)Download
21Lecture 24: Logic Design(Part I)Download
22Lecture 25: Logic Design(Part II)Download
23Lecture 26: Logic Design(Part III)Download
24Lecture 27: Binary Decision Diagrams (Part I)Download
25Lecture 28: Binary Decision Diagrams (Part II)Download
26Lecture 29: Logic Design using AND-EXOR NetworkDownload
27Lecture 30: Threshold Logic and Threshold GatesDownload
28Lecture 31: Latches and Flip-Flops (Part I)Download
29Lecture 32: Latches and Flip-Flops (Part II)Download
30Lecture 33: Latches and Flip-Flops (Part III)Download
31Lecture 34: Clocking and Timing (Part I)Download
32Lecture 35: Clocking and Timing (Part II)Download
33Lecture 36: Synthesis of Synchronous Sequential Circuits (Part I)Download
34Lecture 37: Synthesis of Synchronous Sequential Circuits (Part II)Download
35Lecture 38: Synthesis of Synchronous Sequential Circuits (Part III)Download
36Lecture 39: Synthesis of Synchronous Sequential Circuits (Part IV)Download
37Lecture 40: Minimization of Finite State Machines (Part I)Download
38Lecture 41: Minimization of Finite State Machines (Part II)Download
39Lecture 42: Design of Registers (Part I)Download
40Lecture 43: Design of Registers (Part II)Download
41Lecture 44: Design of Registers (Part III)Download
42Lecture 45: Design of Counters (Part I)Download
43Lecture 46: Design of Counters (Part II)Download
44Lecture 47: Digital-to-Analog Converter (Part I)Download
45Lecture 48: Digital-to-Analog Converter (Part II)Download
46Lecture 49: Analog-to-Digital Converter (Part I)Download
47Lecture 50: Analog-to-Digital Converter (Part II)Download
48Lecture 51: Analog-to-Digital Converter (Part III)Download
49Lecture 52: Asynchronous Sequential Circuits (Part I)Download
50Lecture 53: Asynchronous Sequential Circuits (Part II)Download
51Lecture 54: Algorithmic State Machine (ASM) ChartDownload
52Lecture 55 : Testing of Digital CircuitsDownload
53Lecture 56 : Fault ModelingDownload
54Lecture 57 : Test Pattern GenerationDownload
55Lecture 58 : Design for TestabilityDownload
56Lecture 59 : Built-in Self-Test (Part I)Download
57Lecture 60 : Built-in Self-Test (Part II)Download

Sl.No Chapter Name English
1Lecture 01: IntroductionDownload
Verified
2Lecture 02: Octal and Hexadecimal Number SystemsDownload
Verified
3Lecture 03: Signed and Unsigned Binary Number RepresentationDownload
Verified
4Lecture 04: Binary Addition and SubtractionDownload
Verified
5Lecture 05: BCD and Gray Code RepresentationsDownload
Verified
6Lecture 06: Error Detection and CorrectionDownload
Verified
7Lecture 07: Logic GatesDownload
Verified
8Lecture 08: Logic Families to Implement GatesDownload
Verified
9Lecture 09: Emerging Technologies (Part I)Download
Verified
10Lecture 10: Emerging Technologies (Part II)Download
Verified
11Lecture 11 : Switching AlgebraDownload
Verified
12Lecture 12 : Algebraic ManipulationDownload
Verified
13Lecture 13 : Properties of Switching FunctionsDownload
Verified
14Lecture 14 : Obtaining Canonical Representations of FunctionsDownload
Verified
15Lecture 15 : Functional CompletenessDownload
Verified
16Lecture 16: Minimization Using Karnaugh Maps (Part I)Download
Verified
17Lecture 17: Minimization Using Karnaugh Maps (Part II)Download
Verified
18Lecture 21: Design of Adders (Part I)Download
Verified
19Lecture 22: Design of Adders (Part II)Download
Verified
20Lecture 23: Design of Adders (Part III)Download
Verified
21Lecture 24: Logic Design(Part I)Download
Verified
22Lecture 25: Logic Design(Part II)Download
Verified
23Lecture 26: Logic Design(Part III)Download
Verified
24Lecture 27: Binary Decision Diagrams (Part I)Download
Verified
25Lecture 28: Binary Decision Diagrams (Part II)Download
Verified
26Lecture 29: Logic Design using AND-EXOR NetworkDownload
Verified
27Lecture 30: Threshold Logic and Threshold GatesDownload
Verified
28Lecture 31: Latches and Flip-Flops (Part I)Download
Verified
29Lecture 32: Latches and Flip-Flops (Part II)Download
Verified
30Lecture 33: Latches and Flip-Flops (Part III)Download
Verified
31Lecture 34: Clocking and Timing (Part I)Download
Verified
32Lecture 35: Clocking and Timing (Part II)Download
Verified
33Lecture 36: Synthesis of Synchronous Sequential Circuits (Part I)Download
Verified
34Lecture 37: Synthesis of Synchronous Sequential Circuits (Part II)Download
Verified
35Lecture 38: Synthesis of Synchronous Sequential Circuits (Part III)Download
Verified
36Lecture 39: Synthesis of Synchronous Sequential Circuits (Part IV)Download
Verified
37Lecture 40: Minimization of Finite State Machines (Part I)Download
Verified
38Lecture 41: Minimization of Finite State Machines (Part II)Download
Verified
39Lecture 42: Design of Registers (Part I)Download
Verified
40Lecture 43: Design of Registers (Part II)Download
Verified
41Lecture 44: Design of Registers (Part III)Download
Verified
42Lecture 45: Design of Counters (Part I)Download
Verified
43Lecture 46: Design of Counters (Part II)Download
Verified
44Lecture 47: Digital-to-Analog Converter (Part I)Download
Verified
45Lecture 48: Digital-to-Analog Converter (Part II)Download
Verified
46Lecture 49: Analog-to-Digital Converter (Part I)Download
Verified
47Lecture 50: Analog-to-Digital Converter (Part II)Download
Verified
48Lecture 51: Analog-to-Digital Converter (Part III)Download
Verified
49Lecture 52: Asynchronous Sequential Circuits (Part I)Download
Verified
50Lecture 53: Asynchronous Sequential Circuits (Part II)Download
Verified
51Lecture 54: Algorithmic State Machine (ASM) ChartDownload
Verified
52Lecture 55 : Testing of Digital CircuitsDownload
Verified
53Lecture 56 : Fault ModelingDownload
Verified
54Lecture 57 : Test Pattern GenerationDownload
Verified
55Lecture 58 : Design for TestabilityDownload
Verified
56Lecture 59 : Built-in Self-Test (Part I)Download
Verified
57Lecture 60 : Built-in Self-Test (Part II)Download
Verified
Sl.No Chapter Name Tamil
1Lecture 01: IntroductionDownload
2Lecture 02: Octal and Hexadecimal Number SystemsDownload
3Lecture 03: Signed and Unsigned Binary Number RepresentationDownload
4Lecture 04: Binary Addition and SubtractionDownload
5Lecture 05: BCD and Gray Code RepresentationsDownload
6Lecture 06: Error Detection and CorrectionDownload
7Lecture 07: Logic GatesDownload
8Lecture 08: Logic Families to Implement GatesDownload
9Lecture 09: Emerging Technologies (Part I)Download
10Lecture 10: Emerging Technologies (Part II)Download
11Lecture 11 : Switching AlgebraDownload
12Lecture 12 : Algebraic ManipulationDownload
13Lecture 13 : Properties of Switching FunctionsDownload
14Lecture 14 : Obtaining Canonical Representations of FunctionsDownload
15Lecture 15 : Functional CompletenessDownload
16Lecture 16: Minimization Using Karnaugh Maps (Part I)Download
17Lecture 17: Minimization Using Karnaugh Maps (Part II)Download
18Lecture 21: Design of Adders (Part I)Download
19Lecture 22: Design of Adders (Part II)Download
20Lecture 23: Design of Adders (Part III)Download
21Lecture 24: Logic Design(Part I)Download
22Lecture 25: Logic Design(Part II)Download
23Lecture 26: Logic Design(Part III)Download
24Lecture 27: Binary Decision Diagrams (Part I)Download
25Lecture 28: Binary Decision Diagrams (Part II)Download
26Lecture 29: Logic Design using AND-EXOR NetworkDownload
27Lecture 30: Threshold Logic and Threshold GatesDownload
28Lecture 31: Latches and Flip-Flops (Part I)Download
29Lecture 32: Latches and Flip-Flops (Part II)Download
30Lecture 33: Latches and Flip-Flops (Part III)Download
31Lecture 34: Clocking and Timing (Part I)Download
32Lecture 35: Clocking and Timing (Part II)Download
33Lecture 36: Synthesis of Synchronous Sequential Circuits (Part I)Download
34Lecture 37: Synthesis of Synchronous Sequential Circuits (Part II)Download
35Lecture 38: Synthesis of Synchronous Sequential Circuits (Part III)Download
36Lecture 39: Synthesis of Synchronous Sequential Circuits (Part IV)Download
37Lecture 40: Minimization of Finite State Machines (Part I)Download
38Lecture 41: Minimization of Finite State Machines (Part II)Download
39Lecture 42: Design of Registers (Part I)Download
40Lecture 43: Design of Registers (Part II)Download
41Lecture 44: Design of Registers (Part III)Download
42Lecture 45: Design of Counters (Part I)Download
43Lecture 46: Design of Counters (Part II)Download
44Lecture 47: Digital-to-Analog Converter (Part I)Download
45Lecture 48: Digital-to-Analog Converter (Part II)Download
46Lecture 49: Analog-to-Digital Converter (Part I)Download
47Lecture 50: Analog-to-Digital Converter (Part II)Download
48Lecture 51: Analog-to-Digital Converter (Part III)Download
49Lecture 52: Asynchronous Sequential Circuits (Part I)Download
50Lecture 53: Asynchronous Sequential Circuits (Part II)Download
51Lecture 54: Algorithmic State Machine (ASM) ChartDownload
52Lecture 55 : Testing of Digital CircuitsDownload
53Lecture 56 : Fault ModelingDownload
54Lecture 57 : Test Pattern GenerationDownload
55Lecture 58 : Design for TestabilityDownload
56Lecture 59 : Built-in Self-Test (Part I)Download
57Lecture 60 : Built-in Self-Test (Part II)Download


Sl.No Language Book link
1EnglishDownload
2BengaliNot Available
3GujaratiNot Available
4HindiNot Available
5KannadaNot Available
6MalayalamNot Available
7MarathiNot Available
8TamilNot Available
9TeluguNot Available