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Sl.No Chapter Name MP4 Download
1Lecture 1: Download
2Lecture 2: Download
3Lecture 3: Download
4Lecture 4 : Download
5Lecture 5: Download
6Lecture 6: VERILOG LANGUAGE FEATURES (PART 1)Download
7Lecture 7: VERILOG LANGUAGE FEATURES (PART 2)Download
8Lecture 8: VERILOG LANGUAGE FEATURES (PART 3)Download
9Lecture 9: VERILOG OPERATORSDownload
10Lecture 10:VERILOG MODELING EXAMPLESDownload
11Lecture 11: VERILOG MODELING EXAMPLES (Contd)Download
12Lecture 12: VERILOG DESCRIPTION STYLESDownload
13Lecture 13: PROCEDURAL ASSIGNMENTDownload
14Lecture 14: PROCEDURAL ASSIGNMENT (Contd.)Download
15Lecture 15: PROCEDURAL ASSIGNMENT (EXAMPLES)Download
16Lecture 17:BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 2)Download
17Lecture 17: BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 2)Download
18Lecture 18:BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 3)Download
19Lecture 19:BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 4)Download
20Lecture 20:USER DEFINED PRIMITIVESDownload
21Lecture 21 : VERILOG TEST BENCHDownload
22Lecture 22 : WRITING VERILOG TEST BENCHESDownload
23Lecture 23 : MODELING FINITE STATE MACHINESDownload
24Lecture 24 : MODELING FINITE STATE MACHINES (Contd.)Download
25Lecture 25 : DATAPATH AND CONTROLLER DESIGN (PART 1)Download
26Lecture 26 : DATAPATH AND CONTROLLER DESIGN (PART 2)Download
27Lecture 27: DATAPATH AND CONTROLLER DESIGN (PART 3)Download
28Lecture 28 : SYNTHESIZABLE VERILOGDownload
29Lecture 29 : SOME RECOMMENDED PRACTICESDownload
30Lecture 30: MODELING MEMORYDownload
31Lecture 31: MODELING REGISTER BANKSDownload
32Lecture 32: BASIC PIPELINING CONCEPTSDownload
33Lecture 33: PIPELINE MODELING (PART 1)Download
34Lecture 34: PIPELINE MODELING (PART 2)Download
35Lecture 35: SWITCH LEVEL MODELING (PART 1)Download
36Lecture 36: SWITCH LEVEL MODDELING (PART 2)Download
37Lecture 37 : PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 1)Download
38Lecture 38 : PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 2)Download
39Lecture 39 : PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 3)Download
40Lecture 40 : VERILOG MODELING OF THE PROCESSOR (PART 1)Download
41Lecture 41 : VERILOG MODELING OF THE PROCESSOR (PART 2)Download

Sl.No Chapter Name English
1Lecture 1: Download
Verified
2Lecture 2: Download
Verified
3Lecture 3: Download
Verified
4Lecture 4 : Download
Verified
5Lecture 5: Download
Verified
6Lecture 6: VERILOG LANGUAGE FEATURES (PART 1)Download
Verified
7Lecture 7: VERILOG LANGUAGE FEATURES (PART 2)Download
Verified
8Lecture 8: VERILOG LANGUAGE FEATURES (PART 3)Download
Verified
9Lecture 9: VERILOG OPERATORSDownload
Verified
10Lecture 10:VERILOG MODELING EXAMPLESDownload
Verified
11Lecture 11: VERILOG MODELING EXAMPLES (Contd)Download
Verified
12Lecture 12: VERILOG DESCRIPTION STYLESDownload
Verified
13Lecture 13: PROCEDURAL ASSIGNMENTDownload
Verified
14Lecture 14: PROCEDURAL ASSIGNMENT (Contd.)Download
Verified
15Lecture 15: PROCEDURAL ASSIGNMENT (EXAMPLES)Download
Verified
16Lecture 17:BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 2)Download
Verified
17Lecture 17: BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 2)Download
Verified
18Lecture 18:BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 3)Download
Verified
19Lecture 19:BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 4)Download
Verified
20Lecture 20:USER DEFINED PRIMITIVESDownload
Verified
21Lecture 21 : VERILOG TEST BENCHDownload
Verified
22Lecture 22 : WRITING VERILOG TEST BENCHESDownload
Verified
23Lecture 23 : MODELING FINITE STATE MACHINESDownload
Verified
24Lecture 24 : MODELING FINITE STATE MACHINES (Contd.)Download
Verified
25Lecture 25 : DATAPATH AND CONTROLLER DESIGN (PART 1)Download
Verified
26Lecture 26 : DATAPATH AND CONTROLLER DESIGN (PART 2)Download
Verified
27Lecture 27: DATAPATH AND CONTROLLER DESIGN (PART 3)Download
Verified
28Lecture 28 : SYNTHESIZABLE VERILOGDownload
Verified
29Lecture 29 : SOME RECOMMENDED PRACTICESDownload
Verified
30Lecture 30: MODELING MEMORYDownload
Verified
31Lecture 31: MODELING REGISTER BANKSDownload
Verified
32Lecture 32: BASIC PIPELINING CONCEPTSDownload
Verified
33Lecture 33: PIPELINE MODELING (PART 1)Download
Verified
34Lecture 34: PIPELINE MODELING (PART 2)Download
Verified
35Lecture 35: SWITCH LEVEL MODELING (PART 1)Download
Verified
36Lecture 36: SWITCH LEVEL MODDELING (PART 2)Download
Verified
37Lecture 37 : PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 1)Download
Verified
38Lecture 38 : PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 2)Download
Verified
39Lecture 39 : PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 3)Download
Verified
40Lecture 40 : VERILOG MODELING OF THE PROCESSOR (PART 1)Download
Verified
41Lecture 41 : VERILOG MODELING OF THE PROCESSOR (PART 2)Download
Verified


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