Modules / Lectures
Module NameDownloadDescriptionDownload Size
Week 1Week 1 Assignment and solutionsWeek 1 Assignment and solutions89 kb
Week 2Week 2 Assignment and solutionsWeek 2 Assignment and solutions85 kb
Week 3Week 3 Assignment and solutionsWeek 3 Assignment and solutions77 kb
Week 4Week 4 Assignment and solutionsWeek 4 Assignment and solutions74 kb
Week 5Week 5 Assignment and solutionsWeek 5 Assignment and solutions80 kb
Week 6Week 6 Assignment and solutionsWeek 6 Assignment and solutions54 kb
Week 7Week 7 Assignment and solutionsWeek 7 Assignment and solutions82 kb
Week 8Week 8 Assignment and solutionsWeek 8 Assignment and solutions71 kb


New Assignments
Module NameDownload
Week_01_Assignment_01Week_01_Assignment_01
Week_02_Assignment_02Week_02_Assignment_02
Week_02_Assignment_02aWeek_02_Assignment_02a
Week_02_Assignment_2bWeek_02_Assignment_2b
Week_02_Assignment_2cWeek_02_Assignment_2c
Week_02_Assignment_2dWeek_02_Assignment_2d
Week_03_Assignment_03Week_03_Assignment_03
Week_03_Assignment_3aWeek_03_Assignment_3a
Week_03_Assignment_3bWeek_03_Assignment_3b
Week_03_Assignment_3cWeek_03_Assignment_3c
Week_04_Assignment_04Week_04_Assignment_04
Week_04_Assignment_4aWeek_04_Assignment_4a
Week_04_Assignment_4bWeek_04_Assignment_4b
Week_04_Assignment_4cWeek_04_Assignment_4c
Week_05_Assignment_05Week_05_Assignment_05
Week_05_Assignment_5aWeek_05_Assignment_5a
Week_06_Assignment_06Week_06_Assignment_06
Week_06_Assignment_6aWeek_06_Assignment_6a
Week_07_Assignment_07Week_07_Assignment_07
Week_07_Assignment_7aWeek_07_Assignment_7a
Week_07_Assignment_7bWeek_07_Assignment_7b
Week_08_Assignment_08Week_08_Assignment_08
noc18_cs48_Assignment1noc18_cs48_Assignment1
noc18_cs48_Assignment10noc18_cs48_Assignment10
noc18_cs48_Assignment11noc18_cs48_Assignment11
noc18_cs48_Assignment12noc18_cs48_Assignment12
noc18_cs48_Assignment13noc18_cs48_Assignment13
noc18_cs48_Assignment14noc18_cs48_Assignment14
noc18_cs48_Assignment15noc18_cs48_Assignment15
noc18_cs48_Assignment16noc18_cs48_Assignment16
noc18_cs48_Assignment17noc18_cs48_Assignment17
noc18_cs48_Assignment18noc18_cs48_Assignment18
noc18_cs48_Assignment19noc18_cs48_Assignment19
noc18_cs48_Assignment2noc18_cs48_Assignment2
noc18_cs48_Assignment20noc18_cs48_Assignment20
noc18_cs48_Assignment21noc18_cs48_Assignment21
noc18_cs48_Assignment22noc18_cs48_Assignment22
noc18_cs48_Assignment3noc18_cs48_Assignment3
noc18_cs48_Assignment4noc18_cs48_Assignment4
noc18_cs48_Assignment5noc18_cs48_Assignment5
noc18_cs48_Assignment6noc18_cs48_Assignment6
noc18_cs48_Assignment7noc18_cs48_Assignment7
noc18_cs48_Assignment8noc18_cs48_Assignment8
noc18_cs48_Assignment9noc18_cs48_Assignment9


Sl.No Chapter Name MP4 Download
1Lecture 1: Download
2Lecture 2: Download
3Lecture 3: Download
4Lecture 4 : Download
5Lecture 5: Download
6Lecture 6: VERILOG LANGUAGE FEATURES (PART 1)Download
7Lecture 7: VERILOG LANGUAGE FEATURES (PART 2)Download
8Lecture 8: VERILOG LANGUAGE FEATURES (PART 3)Download
9Lecture 9: VERILOG OPERATORSDownload
10Lecture 10:VERILOG MODELING EXAMPLESDownload
11Lecture 11: VERILOG MODELING EXAMPLES (Contd)Download
12Lecture 12: VERILOG DESCRIPTION STYLESDownload
13Lecture 13: PROCEDURAL ASSIGNMENTDownload
14Lecture 14: PROCEDURAL ASSIGNMENT (Contd.)Download
15Lecture 15: PROCEDURAL ASSIGNMENT (EXAMPLES)Download
16Lecture 17:BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 2)Download
17Lecture 17: BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 2)Download
18Lecture 18:BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 3)Download
19Lecture 19:BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 4)Download
20Lecture 20:USER DEFINED PRIMITIVESDownload
21Lecture 21 : VERILOG TEST BENCHDownload
22Lecture 22 : WRITING VERILOG TEST BENCHESDownload
23Lecture 23 : MODELING FINITE STATE MACHINESDownload
24Lecture 24 : MODELING FINITE STATE MACHINES (Contd.)Download
25Lecture 25 : DATAPATH AND CONTROLLER DESIGN (PART 1)Download
26Lecture 26 : DATAPATH AND CONTROLLER DESIGN (PART 2)Download
27Lecture 27: DATAPATH AND CONTROLLER DESIGN (PART 3)Download
28Lecture 28 : SYNTHESIZABLE VERILOGDownload
29Lecture 29 : SOME RECOMMENDED PRACTICESDownload
30Lecture 30: MODELING MEMORYDownload
31Lecture 31: MODELING REGISTER BANKSDownload
32Lecture 32: BASIC PIPELINING CONCEPTSDownload
33Lecture 33: PIPELINE MODELING (PART 1)Download
34Lecture 34: PIPELINE MODELING (PART 2)Download
35Lecture 35: SWITCH LEVEL MODELING (PART 1)Download
36Lecture 36: SWITCH LEVEL MODDELING (PART 2)Download
37Lecture 37 : PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 1)Download
38Lecture 38 : PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 2)Download
39Lecture 39 : PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 3)Download
40Lecture 40 : VERILOG MODELING OF THE PROCESSOR (PART 1)Download
41Lecture 41 : VERILOG MODELING OF THE PROCESSOR (PART 2)Download

Sl.No Chapter Name English
1Lecture 1: Download
Verified
2Lecture 2: Download
Verified
3Lecture 3: Download
Verified
4Lecture 4 : Download
Verified
5Lecture 5: Download
Verified
6Lecture 6: VERILOG LANGUAGE FEATURES (PART 1)Download
Verified
7Lecture 7: VERILOG LANGUAGE FEATURES (PART 2)Download
Verified
8Lecture 8: VERILOG LANGUAGE FEATURES (PART 3)Download
Verified
9Lecture 9: VERILOG OPERATORSDownload
Verified
10Lecture 10:VERILOG MODELING EXAMPLESDownload
Verified
11Lecture 11: VERILOG MODELING EXAMPLES (Contd)Download
Verified
12Lecture 12: VERILOG DESCRIPTION STYLESPDF unavailable
13Lecture 13: PROCEDURAL ASSIGNMENTPDF unavailable
14Lecture 14: PROCEDURAL ASSIGNMENT (Contd.)PDF unavailable
15Lecture 15: PROCEDURAL ASSIGNMENT (EXAMPLES)PDF unavailable
16Lecture 17:BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 2)PDF unavailable
17Lecture 17: BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 2)PDF unavailable
18Lecture 18:BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 3)PDF unavailable
19Lecture 19:BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 4)PDF unavailable
20Lecture 20:USER DEFINED PRIMITIVESPDF unavailable
21Lecture 21 : VERILOG TEST BENCHPDF unavailable
22Lecture 22 : WRITING VERILOG TEST BENCHESPDF unavailable
23Lecture 23 : MODELING FINITE STATE MACHINESPDF unavailable
24Lecture 24 : MODELING FINITE STATE MACHINES (Contd.)PDF unavailable
25Lecture 25 : DATAPATH AND CONTROLLER DESIGN (PART 1)PDF unavailable
26Lecture 26 : DATAPATH AND CONTROLLER DESIGN (PART 2)PDF unavailable
27Lecture 27: DATAPATH AND CONTROLLER DESIGN (PART 3)PDF unavailable
28Lecture 28 : SYNTHESIZABLE VERILOGPDF unavailable
29Lecture 29 : SOME RECOMMENDED PRACTICESPDF unavailable
30Lecture 30: MODELING MEMORYPDF unavailable
31Lecture 31: MODELING REGISTER BANKSPDF unavailable
32Lecture 32: BASIC PIPELINING CONCEPTSPDF unavailable
33Lecture 33: PIPELINE MODELING (PART 1)PDF unavailable
34Lecture 34: PIPELINE MODELING (PART 2)PDF unavailable
35Lecture 35: SWITCH LEVEL MODELING (PART 1)PDF unavailable
36Lecture 36: SWITCH LEVEL MODDELING (PART 2)PDF unavailable
37Lecture 37 : PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 1)PDF unavailable
38Lecture 38 : PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 2)PDF unavailable
39Lecture 39 : PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 3)PDF unavailable
40Lecture 40 : VERILOG MODELING OF THE PROCESSOR (PART 1)PDF unavailable
41Lecture 41 : VERILOG MODELING OF THE PROCESSOR (PART 2)PDF unavailable


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1EnglishNot Available
2BengaliNot Available
3GujaratiNot Available
4HindiNot Available
5KannadaNot Available
6MalayalamNot Available
7MarathiNot Available
8TamilNot Available
9TeluguNot Available