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Sl.No Chapter Name English
1Lecture 1 : Evolution of Computer SystemsPDF unavailable
2Lecture 2 : Basic Operation of a ComputerPDF unavailable
3Lecture 3 : Memory Addressing and LanguagesPDF unavailable
4Lecture 4 : Software and Architecture TypesPDF unavailable
5Lecture 5 : Instruction Set Architecture PDF unavailable
6Lecture 6 : Number Representation PDF unavailable
7Lecture 7 : Instruction Format and Addressing ModesPDF unavailable
8Lecture 8 : CISC and RISC Architecture PDF unavailable
9Lecture 9 : MIPS32 Instruction SetPDF unavailable
10Lecture 10 MIPS Programming ExamplesPDF unavailable
11Lecture 11 : SPIM – A MIPS32 SIMULATORPDF unavailable
12Lecture 12 : MEASURING CPU PERFORMANCEPDF unavailable
13Lecture 13 : CHOICE OF BENCHMARKSPDF unavailable
14Lecture 14 : SUMMARIZING PERFORMANCE RESULTSPDF unavailable
15Lecture 15 : AMADAHL’S LAW (PART 1)PDF unavailable
16Lecture 16 : AMADAHL’S LAW (PART 2)PDF unavailable
17Lecture 17 : DESIGN OF CONTROL UNIT (PART 1)PDF unavailable
18Lecture 18 :DESIGN OF CONTROL UNIT (PART 2)PDF unavailable
19Lecture 19 : DESIGN OF CONTROL UNIT (PART 3)PDF unavailable
20Lecture 20 : DESIGN OF CONTROL UNIT (PART 4)PDF unavailable
21Lecture 21 : MIPS IMPLEMENTATION (PART 1)PDF unavailable
22Lecture 22 : MIPS IMPLEMENTATION (PART 2)PDF unavailable
23Lecture 23 : PROCESSOR MEMORY INTERACTIONPDF unavailable
24Lecture 24 : STATIC AND DYNAMIC RAMPDF unavailable
25Lecture 25 : ASYNCHRONOUS DRAMPDF unavailable
26Lecture 26 : SYNCHRONOUS DRAMPDF unavailable
27Lecture 27 :MEMORY INTERFACING AND ADDRESSINGPDF unavailable
28Lecture 28 : MEMORY HIERARCHY DESIGN (PART 1)PDF unavailable
29Lecture 29 : MEMORY HIERARCHY DESIGN (PART 2)PDF unavailable
30Lecture 30 : CACHE MEMORY (PART 1)PDF unavailable
31Lecture 31 : CACHE MEMORY (PART 2)PDF unavailable
32Lecture 32 : IMPROVING CACHE PERFORMANCEPDF unavailable
33Lecture 33 : DESIGN OF ADDERS (PART 1)PDF unavailable
34Lecture 34 : DESIGN OF ADDERS (PART 2)PDF unavailable
35Lecture 35 : DESIGN OF MULTIPLIERS (PART 1)PDF unavailable
36Lecture 36 : DESIGN OF MULTIPLIERS (PART 2)PDF unavailable
37Lecture 37 : DESIGN OF DIVIDERSPDF unavailable
38Lecture 38 : FLOATING-POINT NUMBERSPDF unavailable
39Lecture 39 : FLOATING-POINT ARITHMETICPDF unavailable
40Lecture 40 : BASIC PIPELINING CONCEPTSPDF unavailable
41Lecture 41 : PIPELINE SCHEDULINGPDF unavailable
42Lecture 42 : ARITHMETIC PIPELINEPDF unavailable
43Lecture 43 : SECONDARY STORAGE DEVICESPDF unavailable
44Lecture 44 : INPUT-OUTPUT ORGANIZATIONPDF unavailable
45Lecture 45 : DATA TRANSFER TECHNIQUESPDF unavailable
46Lecture 46 : INTERRUPT HANDLING (PART 1)PDF unavailable
47Lecture 47 : INTERRUPT HANDLING (PART 2)PDF unavailable
48Lecture 48 : DIRECT MEMORY ACCESSPDF unavailable
49Lecture 49 : SOME EXAMPLE DEVICE INTERFACINGPDF unavailable
50Lecture 50: EXERCISES ON I/O TRANSFERPDF unavailable
51Lecture 51 : BUS STANDARDSPDF unavailable
52Lecture 52 : BUS STANDARDSPDF unavailable
53Lecture 53: PIPELINING THE MIPS32 DATA PATH PDF unavailable
54Lecture 54: MIPS PIPELINE (Contd.)PDF unavailable
55Lecture 55: PIPELINE HAZARDS (PART 1)PDF unavailable
56Lecture 56: PIPELINE HAZARDS (PART 2)PDF unavailable
57Lecture 57: PIPELINE HAZARDS (PART 3)PDF unavailable
58Lecture 58: PIPELINE HAZARDS (PART 4)PDF unavailable
59Lecture 59 : MULTICYCLE OPERATIONS IN MIPS32PDF unavailable
60Lecture 60 : EXPLOITING INSTRUCTION LEVEL PARALLELISMPDF unavailable
61Lecture 61 : VECTOR PROCESSORSPDF unavailable
62Lecture 62: MULTI-CORE PROCESSORSPDF unavailable
63Lecture 63 : SOME CASE STUDIESPDF unavailable
64Lecture 64 : SUMMARIZATION OF THE COURSEPDF unavailable


Sl.No Language Book link
1EnglishNot Available
2BengaliNot Available
3GujaratiNot Available
4HindiNot Available
5KannadaNot Available
6MalayalamNot Available
7MarathiNot Available
8TamilNot Available
9TeluguNot Available