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Sl.No Chapter Name MP4 Download
1Lecture 1 : Evolution of Computer SystemsDownload
2Lecture 2 : Basic Operation of a ComputerDownload
3Lecture 3 : Memory Addressing and LanguagesDownload
4Lecture 4 : Software and Architecture TypesDownload
5Lecture 5 : Instruction Set Architecture Download
6Lecture 6 : Number Representation Download
7Lecture 7 : Instruction Format and Addressing ModesDownload
8Lecture 8 : CISC and RISC Architecture Download
9Lecture 9 : MIPS32 Instruction SetDownload
10Lecture 10 MIPS Programming ExamplesDownload
11Lecture 11 : SPIM – A MIPS32 SIMULATORDownload
12Lecture 12 : MEASURING CPU PERFORMANCEDownload
13Lecture 13 : CHOICE OF BENCHMARKSDownload
14Lecture 14 : SUMMARIZING PERFORMANCE RESULTSDownload
15Lecture 15 : AMADAHL’S LAW (PART 1)Download
16Lecture 16 : AMADAHL’S LAW (PART 2)Download
17Lecture 17 : DESIGN OF CONTROL UNIT (PART 1)Download
18Lecture 18 :DESIGN OF CONTROL UNIT (PART 2)Download
19Lecture 19 : DESIGN OF CONTROL UNIT (PART 3)Download
20Lecture 20 : DESIGN OF CONTROL UNIT (PART 4)Download
21Lecture 21 : MIPS IMPLEMENTATION (PART 1)Download
22Lecture 22 : MIPS IMPLEMENTATION (PART 2)Download
23Lecture 23 : PROCESSOR MEMORY INTERACTIONDownload
24Lecture 24 : STATIC AND DYNAMIC RAMDownload
25Lecture 25 : ASYNCHRONOUS DRAMDownload
26Lecture 26 : SYNCHRONOUS DRAMDownload
27Lecture 27 :MEMORY INTERFACING AND ADDRESSINGDownload
28Lecture 28 : MEMORY HIERARCHY DESIGN (PART 1)Download
29Lecture 29 : MEMORY HIERARCHY DESIGN (PART 2)Download
30Lecture 30 : CACHE MEMORY (PART 1)Download
31Lecture 31 : CACHE MEMORY (PART 2)Download
32Lecture 32 : IMPROVING CACHE PERFORMANCEDownload
33Lecture 33 : DESIGN OF ADDERS (PART 1)Download
34Lecture 34 : DESIGN OF ADDERS (PART 2)Download
35Lecture 35 : DESIGN OF MULTIPLIERS (PART 1)Download
36Lecture 36 : DESIGN OF MULTIPLIERS (PART 2)Download
37Lecture 37 : DESIGN OF DIVIDERSDownload
38Lecture 38 : FLOATING-POINT NUMBERSDownload
39Lecture 39 : FLOATING-POINT ARITHMETICDownload
40Lecture 40 : BASIC PIPELINING CONCEPTSDownload
41Lecture 41 : PIPELINE SCHEDULINGDownload
42Lecture 42 : ARITHMETIC PIPELINEDownload
43Lecture 43 : SECONDARY STORAGE DEVICESDownload
44Lecture 44 : INPUT-OUTPUT ORGANIZATIONDownload
45Lecture 45 : DATA TRANSFER TECHNIQUESDownload
46Lecture 46 : INTERRUPT HANDLING (PART 1)Download
47Lecture 47 : INTERRUPT HANDLING (PART 2)Download
48Lecture 48 : DIRECT MEMORY ACCESSDownload
49Lecture 49 : SOME EXAMPLE DEVICE INTERFACINGDownload
50Lecture 50: EXERCISES ON I/O TRANSFERDownload
51Lecture 51 : BUS STANDARDSDownload
52Lecture 52 : BUS STANDARDSDownload
53Lecture 53: PIPELINING THE MIPS32 DATA PATH Download
54Lecture 54: MIPS PIPELINE (Contd.)Download
55Lecture 55: PIPELINE HAZARDS (PART 1)Download
56Lecture 56: PIPELINE HAZARDS (PART 2)Download
57Lecture 57: PIPELINE HAZARDS (PART 3)Download
58Lecture 58: PIPELINE HAZARDS (PART 4)Download
59Lecture 59 : MULTICYCLE OPERATIONS IN MIPS32Download
60Lecture 60 : EXPLOITING INSTRUCTION LEVEL PARALLELISMDownload
61Lecture 61 : VECTOR PROCESSORSDownload
62Lecture 62: MULTI-CORE PROCESSORSDownload
63Lecture 63 : SOME CASE STUDIESDownload
64Lecture 64 : SUMMARIZATION OF THE COURSEDownload

Sl.No Chapter Name English
1Lecture 1 : Evolution of Computer SystemsDownload
Verified
2Lecture 2 : Basic Operation of a ComputerDownload
Verified
3Lecture 3 : Memory Addressing and LanguagesDownload
Verified
4Lecture 4 : Software and Architecture TypesDownload
Verified
5Lecture 5 : Instruction Set Architecture Download
Verified
6Lecture 6 : Number Representation Download
Verified
7Lecture 7 : Instruction Format and Addressing ModesDownload
Verified
8Lecture 8 : CISC and RISC Architecture Download
Verified
9Lecture 9 : MIPS32 Instruction SetDownload
Verified
10Lecture 10 MIPS Programming ExamplesDownload
Verified
11Lecture 11 : SPIM – A MIPS32 SIMULATORDownload
Verified
12Lecture 12 : MEASURING CPU PERFORMANCEDownload
Verified
13Lecture 13 : CHOICE OF BENCHMARKSDownload
Verified
14Lecture 14 : SUMMARIZING PERFORMANCE RESULTSDownload
Verified
15Lecture 15 : AMADAHL’S LAW (PART 1)Download
Verified
16Lecture 16 : AMADAHL’S LAW (PART 2)Download
Verified
17Lecture 17 : DESIGN OF CONTROL UNIT (PART 1)Download
Verified
18Lecture 18 :DESIGN OF CONTROL UNIT (PART 2)Download
Verified
19Lecture 19 : DESIGN OF CONTROL UNIT (PART 3)Download
Verified
20Lecture 20 : DESIGN OF CONTROL UNIT (PART 4)Download
Verified
21Lecture 21 : MIPS IMPLEMENTATION (PART 1)Download
Verified
22Lecture 22 : MIPS IMPLEMENTATION (PART 2)Download
Verified
23Lecture 23 : PROCESSOR MEMORY INTERACTIONDownload
Verified
24Lecture 24 : STATIC AND DYNAMIC RAMDownload
Verified
25Lecture 25 : ASYNCHRONOUS DRAMDownload
Verified
26Lecture 26 : SYNCHRONOUS DRAMDownload
Verified
27Lecture 27 :MEMORY INTERFACING AND ADDRESSINGDownload
Verified
28Lecture 28 : MEMORY HIERARCHY DESIGN (PART 1)Download
Verified
29Lecture 29 : MEMORY HIERARCHY DESIGN (PART 2)Download
Verified
30Lecture 30 : CACHE MEMORY (PART 1)Download
Verified
31Lecture 31 : CACHE MEMORY (PART 2)Download
Verified
32Lecture 32 : IMPROVING CACHE PERFORMANCEDownload
Verified
33Lecture 33 : DESIGN OF ADDERS (PART 1)Download
Verified
34Lecture 34 : DESIGN OF ADDERS (PART 2)Download
Verified
35Lecture 35 : DESIGN OF MULTIPLIERS (PART 1)Download
Verified
36Lecture 36 : DESIGN OF MULTIPLIERS (PART 2)Download
Verified
37Lecture 37 : DESIGN OF DIVIDERSDownload
Verified
38Lecture 38 : FLOATING-POINT NUMBERSDownload
Verified
39Lecture 39 : FLOATING-POINT ARITHMETICDownload
Verified
40Lecture 40 : BASIC PIPELINING CONCEPTSDownload
Verified
41Lecture 41 : PIPELINE SCHEDULINGDownload
Verified
42Lecture 42 : ARITHMETIC PIPELINEDownload
Verified
43Lecture 43 : SECONDARY STORAGE DEVICESDownload
Verified
44Lecture 44 : INPUT-OUTPUT ORGANIZATIONDownload
Verified
45Lecture 45 : DATA TRANSFER TECHNIQUESDownload
Verified
46Lecture 46 : INTERRUPT HANDLING (PART 1)Download
Verified
47Lecture 47 : INTERRUPT HANDLING (PART 2)Download
Verified
48Lecture 48 : DIRECT MEMORY ACCESSDownload
Verified
49Lecture 49 : SOME EXAMPLE DEVICE INTERFACINGDownload
Verified
50Lecture 50: EXERCISES ON I/O TRANSFERDownload
Verified
51Lecture 51 : BUS STANDARDSDownload
Verified
52Lecture 52 : BUS STANDARDSDownload
Verified
53Lecture 53: PIPELINING THE MIPS32 DATA PATH Download
Verified
54Lecture 54: MIPS PIPELINE (Contd.)Download
Verified
55Lecture 55: PIPELINE HAZARDS (PART 1)Download
Verified
56Lecture 56: PIPELINE HAZARDS (PART 2)Download
Verified
57Lecture 57: PIPELINE HAZARDS (PART 3)Download
Verified
58Lecture 58: PIPELINE HAZARDS (PART 4)Download
Verified
59Lecture 59 : MULTICYCLE OPERATIONS IN MIPS32Download
Verified
60Lecture 60 : EXPLOITING INSTRUCTION LEVEL PARALLELISMDownload
Verified
61Lecture 61 : VECTOR PROCESSORSDownload
Verified
62Lecture 62: MULTI-CORE PROCESSORSDownload
Verified
63Lecture 63 : SOME CASE STUDIESDownload
Verified
64Lecture 64 : SUMMARIZATION OF THE COURSEDownload
Verified


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2BengaliNot Available
3GujaratiNot Available
4HindiNot Available
5KannadaNot Available
6MalayalamNot Available
7MarathiNot Available
8TamilNot Available
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