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Sl.No Chapter Name MP4 Download
1Lecture 1: IntroductionDownload
2Lecture 2: Design RepresentationDownload
3Lecture 3: VLSI Design Styles (Part 1)Download
4Lecture 4: VLSI Design Styles (Part 2)Download
5Lecture 5: VLSI Physical Design Automation (Part 1)Download
6Lecture 6: VLSI Physical Design Automation (Part 2)Download
7Lecture 7: PartitioningDownload
8Lecture 8: FloorplanningDownload
9Lecture 9: "Floorplanning AlgorithmsDownload
10Lecture 10: Pin AssignmentDownload
11Lecture 11: Placement (Part 1)Download
12Lecture 12: Placement (Part 2)Download
13Lecture 13: Placement (Part 3)Download
14Lecture 14: Placement (Part 4)Download
15Lecture 15: Grid Routing (Part 1)Download
16Lecture 16: Grid Routing (Part 2)Download
17Lecture 17: Grid Routing (Part 3)Download
18Lecture 18: Global Routing (Part 1)Download
19Lecture 19: Global Routing (Part 2)Download
20Lecture 20 : Detailed Routing (Part 1)Download
21Lecture 21: Detailed Routing (Part 2)Download
22Lecture 22: Detailed Routing (Part 3) Download
23Lecture 23 : Detailed Routing (Part 4)Download
24Lecture 24 : Clock Design (Part 1)Download
25Lecture 25 : Clock Design (Part 2) Download
26Lecture 26 : Clock Design (Part 3) Download
27Lecture 27: CLOCK NETWORK SYNTHESIS (PART 1)Download
28Lecture 28: CLOCK NETWORK SYNTHESIS (PART 2)Download
29Lecture 29: CLOCK NETWORK SYNTHESIS (PART 3)Download
30Lecture 30: CLOCK NETWORK SYNTHESIS (PART 4)Download
31Lecture 31: POWER AND GROUND ROUTINGDownload
32Lecture 32: Time Closure (Part 1)Download
33Lecture 33: Time Closure (Part 2)Download
34Lecture 34: Time Closure (Part 3)Download
35Lecture 35: Time Closure (Part 4)Download
36Lecture 36: Time Closure (Part 5)Download
37Lecture 37: Timing Driven PlacementDownload
38Lecture 38: Timing Driven RoutingDownload
39Lecture 39: Physical Synthesis (Part 1)Download
40Lecture 40 : Physical Synthesis (Part 2)Download
41Lecture 41: Performance-Driven Design FlowDownload
42Lecture 42 : Miscellaneous Approaches to Timing Optimization Download
43Lecture 43 :Interconnect Modeling (Part 1)Download
44Lecture 44 : Interconnect Modeling (Part 2)Download
45Lecture 45 : Design Rule CheckDownload
46Lecture 46 : Layout Compaction (Part 1)Download
47Lecture 47 : Layout Compaction (Part 2)Download
48Lecture 48 : Download
49Lecture 49 : Download
50Lecture 50 : Download
51Lecture 51 : Download
52Lecture 52 : Download
53Lecture 53 : Test Pattern GenerationDownload
54Lecture 54: Design for TestabilityDownload
55Lecture 55: Boundary Scan StandardDownload
56Lecture 56: Built-in Self-Test (Part 1)Download
57Lecture 57: Built-in Self-Test (Part 2)Download
58Lecture 58 : Low Power VLSI DesignDownload
59Lecture 59 : Techniques to Reduce PowerDownload
60Lecture 60 : Gate Level Design for Low Power (Part 1)Download
61Lecture 61 : Gate Level Design for Low Power (Part 2)Download
62Lecture 62 : Other Low Power Design TechniquesDownload
63Lecture 63 : Algorithmic Level Techniques for Low Power DesignDownload
64Lecture 64 : Summarization of the CourseDownload

Sl.No Chapter Name English
1Lecture 1: IntroductionDownload
Verified
2Lecture 2: Design RepresentationDownload
Verified
3Lecture 3: VLSI Design Styles (Part 1)Download
Verified
4Lecture 4: VLSI Design Styles (Part 2)Download
Verified
5Lecture 5: VLSI Physical Design Automation (Part 1)Download
Verified
6Lecture 6: VLSI Physical Design Automation (Part 2)Download
Verified
7Lecture 7: PartitioningDownload
Verified
8Lecture 8: FloorplanningDownload
Verified
9Lecture 9: "Floorplanning AlgorithmsDownload
Verified
10Lecture 10: Pin AssignmentDownload
Verified
11Lecture 11: Placement (Part 1)Download
Verified
12Lecture 12: Placement (Part 2)Download
Verified
13Lecture 13: Placement (Part 3)Download
Verified
14Lecture 14: Placement (Part 4)Download
Verified
15Lecture 15: Grid Routing (Part 1)Download
Verified
16Lecture 16: Grid Routing (Part 2)Download
Verified
17Lecture 17: Grid Routing (Part 3)Download
Verified
18Lecture 18: Global Routing (Part 1)Download
Verified
19Lecture 19: Global Routing (Part 2)Download
Verified
20Lecture 20 : Detailed Routing (Part 1)Download
Verified
21Lecture 21: Detailed Routing (Part 2)Download
Verified
22Lecture 22: Detailed Routing (Part 3) Download
Verified
23Lecture 23 : Detailed Routing (Part 4)Download
Verified
24Lecture 24 : Clock Design (Part 1)Download
Verified
25Lecture 25 : Clock Design (Part 2) Download
Verified
26Lecture 26 : Clock Design (Part 3) Download
Verified
27Lecture 27: CLOCK NETWORK SYNTHESIS (PART 1)Download
Verified
28Lecture 28: CLOCK NETWORK SYNTHESIS (PART 2)Download
Verified
29Lecture 29: CLOCK NETWORK SYNTHESIS (PART 3)Download
Verified
30Lecture 30: CLOCK NETWORK SYNTHESIS (PART 4)Download
Verified
31Lecture 31: POWER AND GROUND ROUTINGDownload
Verified
32Lecture 32: Time Closure (Part 1)Download
Verified
33Lecture 33: Time Closure (Part 2)Download
Verified
34Lecture 34: Time Closure (Part 3)Download
Verified
35Lecture 35: Time Closure (Part 4)Download
Verified
36Lecture 36: Time Closure (Part 5)Download
Verified
37Lecture 37: Timing Driven PlacementDownload
Verified
38Lecture 38: Timing Driven RoutingDownload
Verified
39Lecture 39: Physical Synthesis (Part 1)Download
Verified
40Lecture 40 : Physical Synthesis (Part 2)Download
Verified
41Lecture 41: Performance-Driven Design FlowDownload
Verified
42Lecture 42 : Miscellaneous Approaches to Timing Optimization Download
Verified
43Lecture 43 :Interconnect Modeling (Part 1)Download
Verified
44Lecture 44 : Interconnect Modeling (Part 2)Download
Verified
45Lecture 45 : Design Rule CheckDownload
Verified
46Lecture 46 : Layout Compaction (Part 1)Download
Verified
47Lecture 47 : Layout Compaction (Part 2)Download
Verified
48Lecture 48 : Download
Verified
49Lecture 49 : Download
Verified
50Lecture 50 : Download
Verified
51Lecture 51 : Download
Verified
52Lecture 52 : Download
Verified
53Lecture 53 : Test Pattern GenerationDownload
Verified
54Lecture 54: Design for TestabilityDownload
Verified
55Lecture 55: Boundary Scan StandardDownload
Verified
56Lecture 56: Built-in Self-Test (Part 1)Download
Verified
57Lecture 57: Built-in Self-Test (Part 2)Download
Verified
58Lecture 58 : Low Power VLSI DesignDownload
Verified
59Lecture 59 : Techniques to Reduce PowerDownload
Verified
60Lecture 60 : Gate Level Design for Low Power (Part 1)Download
Verified
61Lecture 61 : Gate Level Design for Low Power (Part 2)Download
Verified
62Lecture 62 : Other Low Power Design TechniquesDownload
Verified
63Lecture 63 : Algorithmic Level Techniques for Low Power DesignDownload
Verified
64Lecture 64 : Summarization of the CourseDownload
Verified


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