Modules / Lectures
Module NameDownloadDescriptionDownload Size
Week 1Week 1 Assignment SolutionWeek 1 Assignment Solution142 kb
Week 1Week 1 AssignmentWeek 1 Assignment115 kb
Week 2Week 2 Assignment SolutionWeek 2 Assignment Solution153 kb
Week 2Week 2 AssignmentWeek 2 Assignment121 kb
Week 3Week 3 Assignment SolutionWeek 3 Assignment Solution254 kb
Week 3Week 3 AssignmentWeek 3 Assignment109 kb
Week 4Week 4 Assignment solutionWeek 4 Assignment solution83 kb
Week 4Week 4 AssignmentWeek 4 Assignment95 kb
Week 5Week 5 AssignmentWeek 5 Assignment213 kb
Week 5Week 5 Assignment SolutionWeek 5 Assignment Solution10 kb
Week 6Week 6 AssignmentWeek 6 Assignment425 kb
Week 6Week 6 Assignment SolutionWeek 6 Assignment Solution339 kb
Week 7Week 7 AssignmentWeek 7 Assignment263 kb
Week 7Week 7 Assignment solutionWeek 7 Assignment solution220 kb
Week 8Week 8 AssignmentWeek 8 Assignment340 kb
Week 8Week 8 Assignment solutionWeek 8 Assignment solution262 kb
Week 9Week 9 AssignmentWeek 9 Assignment132 kb
Week 9Week 9 Assignment solutionWeek 9 Assignment solution86 kb
Week 10Week 10 AssignmentWeek 10 Assignment257 kb
Week 10Week 10 Assignment solutionWeek 10 Assignment solution215 kb
Week 11Week 11 AssignmentWeek 11 Assignment196 kb
Week 11Week 11 Assignment SolutionWeek 11 Assignment Solution83 kb
Week 12Week 12 AssignmentWeek 12 Assignment151 kb
Week 12Week 12 Assignment SolutionWeek 12 Assignment Solution83 kb


Sl.No Chapter Name MP4 Download
1Lecture 1: IntroductionDownload
2Lecture 2: ProcessorsDownload
3Lecture 3: General Purpose and ASIPs ProcessorDownload
4Lecture 4: Designing a Single Purpose ProcessorDownload
5Lecture 5: Optimization IssuesDownload
6Lecture 6: Introduction to FPFADownload
7Lecture 7: FPGA Contd.Download
8Lecture 8: Behaviour Synthesis on FPGA using VHDLDownload
9Lecture 9: Tutorial - IDownload
10Lecture 10: Tutorial - IIDownload
11Lecture 11: Tutorial - IIIDownload
12Lecture 12: Tutorial - IVDownload
13Lecture 13: Sensors and SignalsDownload
14Lecture 14: Discretization of Signals and A/D ConverterDownload
15Lecture 15: Quantization Noise, SNR and D/A ConverterDownload
16Lecture 16: Arduino UnoDownload
17Lecture 17: Arduino Uno (Contd.), Serial Communication and TimerDownload
18Lecture 18: Controller Design using ArduinoDownload
19Lecture 19: Tutorial - VDownload
20Lecture 20:Power Aware Embedded System - I Download
21Lecture 21: Power Aware Embedded System - IIDownload
22Lecture 22: SD and DD AlgorithmDownload
23Lecture 23: Parallel Operations and VLIWDownload
24Lecture 24: Code EfficiencyDownload
25Lecture 25: DSP Application and Address Generation UnitDownload
26Lecture 26: Real Time O.S - IDownload
27Lecture 27: Real Time O.S - IIDownload
28Lecture 28: RMS AlgorithmDownload
29Lecture 29 : EDF Algorithm and Resource Constraint IssueDownload
30Lecture 30 : Priority Inversion and Priority Inheritance ProtocolDownload
31Lecture 31 : Modeling and Specification - IDownload
32Lecture 32 : Modeling and Specification - IIDownload
33Lecture 33 : FSM and StatechartDownload
34Lecture 34 : Statechart and Statemate SemanticsDownload
35Lecture 35 : Statecharts (Contd.)Download
36Lecture 36 : Program State MachinesDownload
37Lecture 37 : SDLDownload
38Lecture 38 : Data Flow Model - IDownload
39Lecture 39 : Data Flow Model - IIDownload
40Lecture 40 : Hardware Synthesis - IDownload
41Lecture 41 : Hardware Synthesis - IIDownload
42Lecture 42 : SchedulingDownload
43Lecture 43 : Digital Camera DesignDownload
44Lecture 44 : Digital Camera - Iterative DesignDownload
45Lecture 45 : HW-SW PartitioningDownload
46Lecture 46 : Optimization - IDownload
47Lecture 47 : Optimization - IIDownload
48Lecture 48 : SimulationDownload
49Lecture 49 : Formal VerificationDownload

Sl.No Chapter Name English
1Lecture 1: IntroductionDownload
To be verified
2Lecture 2: ProcessorsDownload
To be verified
3Lecture 3: General Purpose and ASIPs ProcessorDownload
To be verified
4Lecture 4: Designing a Single Purpose ProcessorDownload
To be verified
5Lecture 5: Optimization IssuesDownload
To be verified
6Lecture 6: Introduction to FPFADownload
To be verified
7Lecture 7: FPGA Contd.Download
To be verified
8Lecture 8: Behaviour Synthesis on FPGA using VHDLDownload
To be verified
9Lecture 9: Tutorial - IDownload
To be verified
10Lecture 10: Tutorial - IIDownload
To be verified
11Lecture 11: Tutorial - IIIDownload
To be verified
12Lecture 12: Tutorial - IVDownload
To be verified
13Lecture 13: Sensors and SignalsDownload
To be verified
14Lecture 14: Discretization of Signals and A/D ConverterDownload
To be verified
15Lecture 15: Quantization Noise, SNR and D/A ConverterDownload
To be verified
16Lecture 16: Arduino UnoDownload
To be verified
17Lecture 17: Arduino Uno (Contd.), Serial Communication and TimerDownload
To be verified
18Lecture 18: Controller Design using ArduinoDownload
To be verified
19Lecture 19: Tutorial - VDownload
To be verified
20Lecture 20:Power Aware Embedded System - I Download
To be verified
21Lecture 21: Power Aware Embedded System - IIDownload
To be verified
22Lecture 22: SD and DD AlgorithmDownload
To be verified
23Lecture 23: Parallel Operations and VLIWDownload
To be verified
24Lecture 24: Code EfficiencyDownload
To be verified
25Lecture 25: DSP Application and Address Generation UnitDownload
To be verified
26Lecture 26: Real Time O.S - IDownload
To be verified
27Lecture 27: Real Time O.S - IIDownload
To be verified
28Lecture 28: RMS AlgorithmDownload
To be verified
29Lecture 29 : EDF Algorithm and Resource Constraint IssueDownload
To be verified
30Lecture 30 : Priority Inversion and Priority Inheritance ProtocolDownload
To be verified
31Lecture 31 : Modeling and Specification - IDownload
To be verified
32Lecture 32 : Modeling and Specification - IIDownload
To be verified
33Lecture 33 : FSM and StatechartDownload
To be verified
34Lecture 34 : Statechart and Statemate SemanticsDownload
To be verified
35Lecture 35 : Statecharts (Contd.)Download
To be verified
36Lecture 36 : Program State MachinesDownload
To be verified
37Lecture 37 : SDLDownload
To be verified
38Lecture 38 : Data Flow Model - IDownload
To be verified
39Lecture 39 : Data Flow Model - IIDownload
To be verified
40Lecture 40 : Hardware Synthesis - IDownload
To be verified
41Lecture 41 : Hardware Synthesis - IIDownload
To be verified
42Lecture 42 : SchedulingDownload
To be verified
43Lecture 43 : Digital Camera DesignDownload
To be verified
44Lecture 44 : Digital Camera - Iterative DesignDownload
To be verified
45Lecture 45 : HW-SW PartitioningDownload
To be verified
46Lecture 46 : Optimization - IDownload
To be verified
47Lecture 47 : Optimization - IIDownload
To be verified
48Lecture 48 : SimulationDownload
To be verified
49Lecture 49 : Formal VerificationDownload
To be verified


Sl.No Language Book link
1EnglishNot Available
2BengaliNot Available
3GujaratiNot Available
4HindiNot Available
5KannadaNot Available
6MalayalamNot Available
7MarathiNot Available
8TamilNot Available
9TeluguNot Available