Modules / Lectures
Module NameDownloadDescriptionDownload Size
Module 1: Multi-core: The Ultimate Dose of MooreLecture 1Evolution of Processor Architecture146 kb
Module 1: Multi-core: The Ultimate Dose of MooreLecture 2Moore's Law and Multi-cores211 kb
Module 2: Parallel Computer Architecture: Today and TomorrowLecture 3Evaluating Performance86 kb
Module 2: Parallel Computer Architecture: Today and TomorrowLecture 4Shared Memory Multiprocessors50 kb
Module 3: Recap: Single-threaded ExecutionLecture 5Pipelining and Hazards103 kb
Module 3: Recap: Single-threaded ExecutionLecture 6Instruction Issue Algorithms230 kb
Module 4: Recap: Virtual Memory and CachesLecture 7Virtual Memory, TLB, and Caches64 kb
Module 4: Recap: Virtual Memory and CachesLecture 8Cache Hierarchy and Memory-level Parallelism61 kb
Module 5: MIPS R10000: A Case StudyLecture 9MIPS R10000: A Case Study66 kb
Module 6: Fundamentals of Parallel ComputersLecture 10Communication Architecture50 kb
Module 6: Fundamentals of Parallel ComputersLecture 11Design Issues in Parallel Computers71 kb
Module 7: Parallel ProgrammingLecture 12Steps in Writing a Parallel Program46 kb
Module 7: Parallel ProgrammingLecture 13Parallelizing a Sequential Program110 kb
Module 8: Performance IssuesLecture 14Load Balancing and Domain Decomposition49 kb
Module 8: Performance IssuesLecture 15Locality and Communication Optimizations98 kb
Module 9: Introduction to Shared Memory MultiprocessorsLecture 16Multiprocessor Organizations and Cache Coherence98 kb
Module 9: Introduction to Shared Memory MultiprocessorsLecture 17Introduction to Cache Coherence Protocols105 kb
Module 10: Design of Shared Memory MultiprocessorsLecture 18Introduction to Cache Coherence108 kb
Module 10: Design of Shared Memory MultiprocessorsLecture 19Sequential Consistency and Cache Coherence Protocols119 kb
Module 10: Design of Shared Memory MultiprocessorsLecture 20Performance of Coherence Protocols90 kb
Module 11: SynchronizationLecture 21Introduction to Synchronization44 kb
Module 11: SynchronizationLecture 22Scalable Locking Primitives49 kb
Module 11: SynchronizationLecture 23Barriers and Speculative Synchronization52 kb
Module 12: Multiprocessors on a Snoopy BusLecture 24Write Serialization in a Simple Design90 kb
Module 12: Multiprocessors on a Snoopy BusLecture 25Protocols for Split-transaction Buses124 kb
Module 12: Multiprocessors on a Snoopy BusLecture 26Case Studies185 kb
Module 12: Multiprocessors on a Snoopy BusLecture 27Scalable Snooping and AMD Hammer Protocol166 kb
Module 13: Scalable MultiprocessorsLecture 28Scalable Multiprocessors200 kb
Module 14: Directory-based Cache CoherenceLecture 29Basics of Directory47 kb
Module 14: Directory-based Cache CoherenceLecture 30SGI Origin 2000276 kb
Module 14: Directory-based Cache CoherenceLecture 31Managing Directory Overhead50 kb
Module 14: Directory-based Cache CoherenceLecture 32Protocol Occupancy and Directory Controllers41 kb
Module 14: Directory-based Cache CoherenceLecture 33SCI Protocol46 kb
Module 15: Memory Consistency ModelsLecture 34Sequential Consistency and Relaxed Models63 kb
Module 15: Memory Consistency ModelsLecture 35Release Consistency and Delayed Consistency87 kb
Module 16: Software Distributed Shared Memory MultiprocessorsLecture 36Software Distributed Shared Memory Multiprocessors122 kb
Module 17: Interconnection NetworksLecture 37Introduction to Routers181 kb
Module 17: Interconnection NetworksLecture 38Routing Algorithms144 kb
Module 18: TLP on Chip: HT/SMT and CMPLecture 39Simultaneous Multithreading and Chip-multiprocessing131 kb
Module 18: TLP on Chip: HT/SMT and CMPLecture 40Case Studies: IBM Power4 and IBM Power5778 kb
Module 18: TLP on Chip: HT/SMT and CMPLecture 41Case Studies: Intel Montecito and Sun Niagara528 kb