Sl.No Chapter Name MP4 Download
1Lec 1: Introduction to C-Based VLSI DesignDownload
2Lec 2: C-based VLSI Design: An OverviewDownload
3Lec 3: C-based VLSI Design: Problem FormulationDownload
4Lec 4: C-based VLSI Design: Course PlanDownload
5Lec 5: Introduction to SchedulingDownload
6Lec 6: ILP formulation of SchedulingDownload
7Lec 7: ILP formulation of MRLC and MLRC SchedulingDownload
8Lec 8: Multiprocessor SchedulingDownload
9Lec 9: Hu’s algorithm for Multiprocessor SchedulingDownload
10Lec 10: List based Scheduling of MLRCDownload
11Lec 11: List based Scheduling of MRLCDownload
12Lec 12: Forced Directed SchedulingDownload
13Lec 13: Forced Directed MLRC and MRLC Scheduling AlgorithmDownload
14Lec 14: Path Based SchedulingDownload
15Lec 15: Path Based SchedulingDownload
16Lec 16: Allocation and Binding Problem FormulationDownload
17Lec 17: Left Edge AlgorithmDownload
18Lec 18: ILP Formulation of Allocation and BindingDownload
19Lec 19: Allocation and Binding for Hierarchical GraphDownload
20Lec 20: Register Allocation and BindingDownload
21Lec 21: Multi-port Binding ProblemDownload
22Lec 22: Datapath and Controller SynthesisDownload
23Lec 23: HLS for ArraysDownload
24Lec 24: HLS for LoopsDownload
25Lec 25: HLS for Loop - pipelineDownload
26Lec 26: Hardware Efficient C CodingDownload
27Lec 27: Hardware Efficient C Coding – part IIDownload
28Lec 28: Dataflow Optimization in HLSDownload

Sl.No Chapter Name English
1Lec 1: Introduction to C-Based VLSI DesignPDF unavailable
2Lec 2: C-based VLSI Design: An OverviewPDF unavailable
3Lec 3: C-based VLSI Design: Problem FormulationPDF unavailable
4Lec 4: C-based VLSI Design: Course PlanPDF unavailable
5Lec 5: Introduction to SchedulingPDF unavailable
6Lec 6: ILP formulation of SchedulingPDF unavailable
7Lec 7: ILP formulation of MRLC and MLRC SchedulingPDF unavailable
8Lec 8: Multiprocessor SchedulingPDF unavailable
9Lec 9: Hu’s algorithm for Multiprocessor SchedulingPDF unavailable
10Lec 10: List based Scheduling of MLRCPDF unavailable
11Lec 11: List based Scheduling of MRLCPDF unavailable
12Lec 12: Forced Directed SchedulingPDF unavailable
13Lec 13: Forced Directed MLRC and MRLC Scheduling AlgorithmPDF unavailable
14Lec 14: Path Based SchedulingPDF unavailable
15Lec 15: Path Based SchedulingPDF unavailable
16Lec 16: Allocation and Binding Problem FormulationPDF unavailable
17Lec 17: Left Edge AlgorithmPDF unavailable
18Lec 18: ILP Formulation of Allocation and BindingPDF unavailable
19Lec 19: Allocation and Binding for Hierarchical GraphPDF unavailable
20Lec 20: Register Allocation and BindingPDF unavailable
21Lec 21: Multi-port Binding ProblemPDF unavailable
22Lec 22: Datapath and Controller SynthesisPDF unavailable
23Lec 23: HLS for ArraysPDF unavailable
24Lec 24: HLS for LoopsPDF unavailable
25Lec 25: HLS for Loop - pipelinePDF unavailable
26Lec 26: Hardware Efficient C CodingPDF unavailable
27Lec 27: Hardware Efficient C Coding – part IIPDF unavailable
28Lec 28: Dataflow Optimization in HLSPDF unavailable


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