Modules / Lectures
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noc21_cs96_assignment_Week_10noc21_cs96_assignment_Week_10
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noc21_cs96_assignment_Week_9noc21_cs96_assignment_Week_9
noc21_cs96assignment_Week12noc21_cs96assignment_Week12


Sl.No Chapter Name MP4 Download
1Lec 1: Introduction to C-Based VLSI DesignDownload
2Lec 2: C-based VLSI Design: An OverviewDownload
3Lec 3: C-based VLSI Design: Problem FormulationDownload
4Lec 4: C-based VLSI Design: Course PlanDownload
5Lec 5: Introduction to SchedulingDownload
6Lec 6: ILP formulation of SchedulingDownload
7Lec 7: ILP formulation of MRLC and MLRC SchedulingDownload
8Lec 8: Multiprocessor SchedulingDownload
9Lec 9: Hu’s algorithm for Multiprocessor SchedulingDownload
10Lec 10: List based Scheduling of MLRCDownload
11Lec 11: List based Scheduling of MRLCDownload
12Lec 12: Forced Directed SchedulingDownload
13Lec 13: Forced Directed MLRC and MRLC Scheduling AlgorithmDownload
14Lec 14: Path Based SchedulingDownload
15Lec 15: Path Based SchedulingDownload
16Lec 16: Allocation and Binding Problem FormulationDownload
17Lec 17: Left Edge AlgorithmDownload
18Lec 18: ILP Formulation of Allocation and BindingDownload
19Lec 19: Allocation and Binding for Hierarchical GraphDownload
20Lec 20: Register Allocation and BindingDownload
21Lec 21: Multi-port Binding ProblemDownload
22Lec 22: Datapath and Controller SynthesisDownload
23Lec 23: HLS for ArraysDownload
24Lec 24: HLS for LoopsDownload
25Lec 25: HLS for Loop - pipelineDownload
26Lec 26: Hardware Efficient C CodingDownload
27Lec 27: Hardware Efficient C Coding – part IIDownload
28Lec 28: Dataflow Optimization in HLSDownload
29Lec 29: Frontend Optimizations in CDownload
30Lec 30: HLS Optimizations: Case Study 1Download
31Lec 31: HLS Optimizations: Case Study 1Download
32Lec 32: Simulation based VerificationDownload
33Lec 33: RTL to C Reverse EngineeringDownload
34Lec 34: Phase-wise Verification of HLSDownload
35Lec 35: Equivalence between C and RTLDownload
36Lec 37: HLS for SecurityDownload
37Lec 36: Introduction to Hardware SecurityDownload
38Lec 38: Attacks on RTL Logic lockingDownload
39Lec 39: Introduction to Logic SynthesisDownload
40Lec 40: FPGA Technology MappingDownload
41Lec 41: Introduction to Physical SynthesisDownload
42Lec 42: Introduction to Circuit optimizationsDownload
43Lec 43: Recent Advances in C-Based VLSI DesignDownload

Sl.No Chapter Name English
1Lec 1: Introduction to C-Based VLSI DesignDownload
Verified
2Lec 2: C-based VLSI Design: An OverviewPDF unavailable
3Lec 3: C-based VLSI Design: Problem FormulationPDF unavailable
4Lec 4: C-based VLSI Design: Course PlanPDF unavailable
5Lec 5: Introduction to SchedulingDownload
Verified
6Lec 6: ILP formulation of SchedulingDownload
Verified
7Lec 7: ILP formulation of MRLC and MLRC SchedulingDownload
Verified
8Lec 8: Multiprocessor SchedulingDownload
Verified
9Lec 9: Hu’s algorithm for Multiprocessor SchedulingDownload
Verified
10Lec 10: List based Scheduling of MLRCDownload
Verified
11Lec 11: List based Scheduling of MRLCDownload
Verified
12Lec 12: Forced Directed SchedulingDownload
Verified
13Lec 13: Forced Directed MLRC and MRLC Scheduling AlgorithmDownload
Verified
14Lec 14: Path Based SchedulingDownload
Verified
15Lec 15: Path Based SchedulingDownload
Verified
16Lec 16: Allocation and Binding Problem FormulationPDF unavailable
17Lec 17: Left Edge AlgorithmPDF unavailable
18Lec 18: ILP Formulation of Allocation and BindingPDF unavailable
19Lec 19: Allocation and Binding for Hierarchical GraphPDF unavailable
20Lec 20: Register Allocation and BindingPDF unavailable
21Lec 21: Multi-port Binding ProblemPDF unavailable
22Lec 22: Datapath and Controller SynthesisPDF unavailable
23Lec 23: HLS for ArraysPDF unavailable
24Lec 24: HLS for LoopsPDF unavailable
25Lec 25: HLS for Loop - pipelinePDF unavailable
26Lec 26: Hardware Efficient C CodingPDF unavailable
27Lec 27: Hardware Efficient C Coding – part IIPDF unavailable
28Lec 28: Dataflow Optimization in HLSPDF unavailable
29Lec 29: Frontend Optimizations in CPDF unavailable
30Lec 30: HLS Optimizations: Case Study 1PDF unavailable
31Lec 31: HLS Optimizations: Case Study 1PDF unavailable
32Lec 32: Simulation based VerificationPDF unavailable
33Lec 33: RTL to C Reverse EngineeringPDF unavailable
34Lec 34: Phase-wise Verification of HLSPDF unavailable
35Lec 35: Equivalence between C and RTLPDF unavailable
36Lec 37: HLS for SecurityDownload
Verified
37Lec 36: Introduction to Hardware SecurityDownload
Verified
38Lec 38: Attacks on RTL Logic lockingDownload
Verified
39Lec 39: Introduction to Logic SynthesisDownload
Verified
40Lec 40: FPGA Technology MappingPDF unavailable
41Lec 41: Introduction to Physical SynthesisPDF unavailable
42Lec 42: Introduction to Circuit optimizationsDownload
Verified
43Lec 43: Recent Advances in C-Based VLSI DesignDownload
Verified


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3GujaratiNot Available
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7MarathiNot Available
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