Modules / Lectures
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Sl.No Chapter Name MP4 Download
1Review of Basic Computer Organization Download
2Perfomance Evaluation Methods Download
3Introduction to RISC Instruction PipelineDownload
4Instruction Pipeline & PerformanceDownload
5Lec 4: Pipeline HazardsDownload
6Lec 5 : Control Hazards & Branch PredictionDownload
7Lec 6 : MIPS Pipeline for Multi-Cycle OperationsDownload
8Tutorial 2 : Pipeline Hazard AnalysisDownload
9Lec 7: Compiler Techniques to Explore ILPDownload
10Lec 8: Dynamic Scheduling to Explore ILPDownload
11Lec 9: Dynamic Scheduling with Tomasulo’s AlgorithmDownload
12Lec 10: Dynamic Scheduling with Speculative ExecutionDownload
13Tutorial 3: Static and Dynamic SchedulingDownload
14Lec 11: Advanced Pipelining & Superscalar ProcessorsDownload
15Lec 12: Exploiting DLP: Vector & GPU ArchitecturesDownload
16Tutorial 4: Architectural Simulation using gem5Download
17Tutorial 5: Core Optimization in gem5Download
18Lec 13: Introduction to Cache MemoryDownload
19Lec 14: Block Replacement Techniques & Write StrategyDownload
20Tutorial 6: Design Concepts in Cache MemoryDownload
21Lec 15: Optimization Techniques in Cache MemoryDownload
22Lec 16: Advanced Cache Optimization TechniquesDownload
23 Tutorial 7: Optimization Techniques in Cache MemoryDownload
24Tutorial 8: Cache Optimization in gem5Download
25Lec 17: Introduction to DRAM SystemDownload
26Lec 18: DRAM Controllers & Address MappingDownload
27Lec 19: Secondary Storage SystemsDownload
28Tutorial 9: Design Concepts in DRAM and HarddiskDownload
29Lec 20: Tiled Chip Multicore ProcessorsDownload
30Lec 21: Routing Techniques in Network on ChipDownload
31Lec 22: NoC Router MicroarchitectureDownload
32Lec 23: How to Explore Computer Architecture?Download
33Tutorial 10: TCMP and NoC Design PrinciplesDownload

Sl.No Chapter Name English
1Review of Basic Computer Organization Download
Verified
2Perfomance Evaluation Methods Download
Verified
3Introduction to RISC Instruction PipelineDownload
Verified
4Instruction Pipeline & PerformanceDownload
Verified
5Lec 4: Pipeline HazardsDownload
Verified
6Lec 5 : Control Hazards & Branch PredictionDownload
Verified
7Lec 6 : MIPS Pipeline for Multi-Cycle OperationsDownload
Verified
8Tutorial 2 : Pipeline Hazard AnalysisDownload
Verified
9Lec 7: Compiler Techniques to Explore ILPDownload
Verified
10Lec 8: Dynamic Scheduling to Explore ILPDownload
Verified
11Lec 9: Dynamic Scheduling with Tomasulo’s AlgorithmDownload
Verified
12Lec 10: Dynamic Scheduling with Speculative ExecutionDownload
Verified
13Tutorial 3: Static and Dynamic SchedulingDownload
Verified
14Lec 11: Advanced Pipelining & Superscalar ProcessorsDownload
Verified
15Lec 12: Exploiting DLP: Vector & GPU ArchitecturesDownload
Verified
16Tutorial 4: Architectural Simulation using gem5Download
Verified
17Tutorial 5: Core Optimization in gem5Download
Verified
18Lec 13: Introduction to Cache MemoryDownload
Verified
19Lec 14: Block Replacement Techniques & Write StrategyDownload
Verified
20Tutorial 6: Design Concepts in Cache MemoryDownload
Verified
21Lec 15: Optimization Techniques in Cache MemoryDownload
Verified
22Lec 16: Advanced Cache Optimization TechniquesDownload
Verified
23 Tutorial 7: Optimization Techniques in Cache MemoryDownload
Verified
24Tutorial 8: Cache Optimization in gem5Download
Verified
25Lec 17: Introduction to DRAM SystemDownload
Verified
26Lec 18: DRAM Controllers & Address MappingDownload
Verified
27Lec 19: Secondary Storage SystemsDownload
Verified
28Tutorial 9: Design Concepts in DRAM and HarddiskDownload
Verified
29Lec 20: Tiled Chip Multicore ProcessorsDownload
Verified
30Lec 21: Routing Techniques in Network on ChipDownload
Verified
31Lec 22: NoC Router MicroarchitectureDownload
Verified
32Lec 23: How to Explore Computer Architecture?Download
Verified
33Tutorial 10: TCMP and NoC Design PrinciplesDownload
Verified


Sl.No Language Book link
1EnglishNot Available
2BengaliNot Available
3GujaratiNot Available
4HindiNot Available
5KannadaNot Available
6MalayalamNot Available
7MarathiNot Available
8TamilNot Available
9TeluguNot Available