Module NameDownload
Assignment-1_noc18_cs50_8Assignment-1_noc18_cs50_8
Assignment-2_noc18_cs50_16Assignment-2_noc18_cs50_16
Assignment-3_noc18_cs50_22Assignment-3_noc18_cs50_22
Assignment-4_noc18_cs50_34Assignment-4_noc18_cs50_34
Assignment-5_noc18_cs50_40Assignment-5_noc18_cs50_40
Assignment-6_noc18_cs50_46Assignment-6_noc18_cs50_46
Assignment-7_noc18_cs50_53Assignment-7_noc18_cs50_53
Assignment-8_noc18_cs50_61Assignment-8_noc18_cs50_61
Assignment-9_noc18_cs50_68Assignment-9_noc18_cs50_68


Sl.No Chapter Name MP4 Download
1Introduction and Overview of the CourseDownload
2Instruction Execution PrinciplesDownload
3Introduction to Instruction PipelineDownload
4Introduction to Superscalar PipelinesDownload
5Instruction Pipeline & Performance - IDownload
6Instruction Pipeline & Performance - IIDownload
7Introduction to Cache MemoryDownload
8Block Replacement Techniques & Write StrategyDownload
9gem5 Simulator - An OverviewDownload
10Cache MemoryDownload
11Basic Cache Optimization TechniquesDownload
12gem5 Simulator - Cache OptimisationDownload
13Advanced Cache Optimization Techniques-IDownload
14Advanced Cache Optimization Techniques-IIDownload
15Cache Memory OptimizationsDownload
16Introduction to DRAM SystemDownload
17DRAM Controllers & Address MappingDownload
18Address Translation MechanismsDownload
19Main Memory ConceptsDownload
20Introduction to Tiled Chip Multicore ProcessorsDownload
21Routing Techniques in Network On ChipDownload
22Network On Chip Router Micro-ArchitectureDownload
23gem5 Simulator - NoC OptimisationDownload
24Energy Efficient Bufferless NoC RoutersDownload
25Sidebuffered Deflection RoutersDownload
26Concepts in Network on ChipDownload
27QoS of NoC and Caches in TCMP SystemsDownload
28Emerging Trends in Network On ChipsDownload
29Concepts in TCMP SystemsDownload

Sl.No Chapter Name English
1Introduction and Overview of the CourseDownload
Verified
2Instruction Execution PrinciplesDownload
Verified
3Introduction to Instruction PipelineDownload
Verified
4Introduction to Superscalar PipelinesDownload
Verified
5Instruction Pipeline & Performance - IDownload
Verified
6Instruction Pipeline & Performance - IIDownload
Verified
7Introduction to Cache MemoryDownload
Verified
8Block Replacement Techniques & Write StrategyDownload
Verified
9gem5 Simulator - An OverviewDownload
Verified
10Cache MemoryDownload
Verified
11Basic Cache Optimization TechniquesDownload
Verified
12gem5 Simulator - Cache OptimisationDownload
Verified
13Advanced Cache Optimization Techniques-IDownload
Verified
14Advanced Cache Optimization Techniques-IIDownload
Verified
15Cache Memory OptimizationsDownload
Verified
16Introduction to DRAM SystemDownload
Verified
17DRAM Controllers & Address MappingDownload
Verified
18Address Translation MechanismsDownload
Verified
19Main Memory ConceptsDownload
Verified
20Introduction to Tiled Chip Multicore ProcessorsDownload
Verified
21Routing Techniques in Network On ChipDownload
Verified
22Network On Chip Router Micro-ArchitectureDownload
Verified
23gem5 Simulator - NoC OptimisationDownload
Verified
24Energy Efficient Bufferless NoC RoutersDownload
Verified
25Sidebuffered Deflection RoutersDownload
Verified
26Concepts in Network on ChipDownload
Verified
27QoS of NoC and Caches in TCMP SystemsDownload
Verified
28Emerging Trends in Network On ChipsDownload
Verified
29Concepts in TCMP SystemsDownload
Verified


Sl.No Language Book link
1EnglishNot Available
2BengaliNot Available
3GujaratiNot Available
4HindiNot Available
5KannadaNot Available
6MalayalamNot Available
7MarathiNot Available
8TamilNot Available
9TeluguNot Available