Modules / Lectures
Module NameDownloadDescriptionDownload Size
IntroductionModule 1module1891 kb
Scheduling, Allocation and BindingModule 2module21136 kb
Logic Optimization and SynthesisModule3module31210 kb
Temporal LogicModule4module4625 kb
Verification TechniquesModule5module51026 kb
Binary Decision DiagramModule6module6583 kb
Introduction to Digital TestingModule7module71275 kb
Fault Simulation and Testability MeasuresModule8module81372 kb
Combinational Circuit Test Pattern GenerationModule9module9794 kb
Sequential Circuit Testing and Scan ChainsModule10module10931 kb
Built in Self test (BIST)Module11module11725 kb
Module NameDownloadDescriptionDownload Size
IntroductionAssignment IAssignment I64 kb
Scheduling, Allocation and BindingAssignment IIAssignment II9 kb
Logic Optimization and SynthesisAssignment IIIAssignment III63 kb
Temporal LogicAssignment IVAssignment IV34 kb
Verification TechniquesAssignment VAssignment V22 kb
Binary Decision DiagramAssignment VIAssignment VI42 kb
Introduction to Digital TestingAssignment VIIAssignment VII64 kb
Fault Simulation and Testability MeasuresAssignment VIIIAssignment VIII69 kb
Combinational Circuit Test Pattern GenerationAssignment IXAssignment IX64 kb
Sequential Circuit Testing and Scan ChainsAssignment XAssignment X68 kb
Built in Self test (BIST)Assignment XIAssignment XI15 kb


New Assignments
Module NameDownload

Sl.No Chapter Name English
1Introduction to Digital VLSI Design FlowPDF unavailable
2High Level Design RepresentationPDF unavailable
3Transformations for High Level SynthesisPDF unavailable
4Introduction to HLS: Scheduling, Allocation and Binding ProblemPDF unavailable
5Scheduling Algorithms-1 PDF unavailable
6Scheduling Algorithms-2 PDF unavailable
7Binding and Allocation AlgorithmsPDF unavailable
8Two level Boolean Logic Synthesis-1PDF unavailable
9Two level Boolean Logic Synthesis-2PDF unavailable
10Two level Boolean Logic Synthesis-3PDF unavailable
11Heuristic Minimization of Two-Level CircuitsPDF unavailable
12Finite State Machine SynthesisPDF unavailable
13Multilevel ImplementationPDF unavailable
14Introduction to formal methods for design verification PDF unavailable
15Temporal Logic: Introduction and Basic OperatorsPDF unavailable
16Syntax and Semantics of CTLPDF unavailable
17Syntax and Semantics of CTL Continued PDF unavailable
18Equivalence between CTL FormulasPDF unavailable
19Introduction to Model Checking PDF unavailable
20Model Checking Algorithms IPDF unavailable
21Model Checking Algorithms IIPDF unavailable
22Model Checking with FairnessPDF unavailable
23Binary Decision Diagram: Introduction and constructionPDF unavailable
24Ordered Binary Decision DiagramPDF unavailable
25Operation on Ordered Binary Decision DiagramPDF unavailable
26Ordered Binary Decision Diagram for State Transition SystemsPDF unavailable
27Symbolic Model CheckingPDF unavailable
28Introduction to Digital VLSI TestingPDF unavailable
29Functional and Structural TestingPDF unavailable
30Fault EquivalencePDF unavailable
31Fault Simulation-1PDF unavailable
32Fault Simulation-2PDF unavailable
33Fault Simulation-3PDF unavailable
34Testability Measures (SCOAP)PDF unavailable
35Introduction to Automatic Test Pattern Generation (ATPG) and ATPG AlgebrasPDF unavailable
36D-Algorithm-1PDF unavailable
37D-Algorithm-2PDF unavailable
38ATPG for Synchronous Sequential CircuitsPDF unavailable
39Scan Chain based Sequential Circuit Testing-1PDF unavailable
40Scan Chain based Sequential Circuit Testing-2PDF unavailable
41Built in Self Test-1 PDF unavailable
42Built in Self Test-2 PDF unavailable
43Memory Testing-1PDF unavailable
44Memory Testing-2PDF unavailable


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2BengaliNot Available
3GujaratiNot Available
4HindiNot Available
5KannadaNot Available
6MalayalamNot Available
7MarathiNot Available
8TamilNot Available
9TeluguNot Available