**Self Assessment Quiz**

1. Assume that a silicon transistor with β =50, V_{BEactive}=0.7 V, V_{CC} =15V and R_{C}=10K is used in the Fig.1.It is desired to establish a Q-point at V_{C}_{E}=7.5 V and I_{C}=5mA and stability factor S≤5.Find Re,R_{1}and R_{2}.

Fig.1

2. In the Darlington stage shown in Fig.2 , V_{CC}=15V , β_{1}=50, β_{2}=75,V_{BE}=0.7,R_{C}=750 Ω and R_{E}=100 Ω. If at the quiescent point V_{CE2}=6V determine the value of R.

Fig.2

3. For the amplifier shown in Fig.3 using a transistor whose parameters are h_{ie}=1100,h_{re}=2.5×10^{-4,}h_{fe}=50,h_{oe}=24µA/V.Find A_{I}, A_{V}, A_{VS} and R_{i}.

Fig.3

4. Find the voltage gain A_{V }, A_{VS}of the amplifier shown. Assume h_{ie} =1100 ,h_{re}=2.5×10^{-4}, h_{fe}=50, h_{oe}=24µA/V. Also find Ri and Ro.

Fig.4

5. Given the following transistor measurements made at I_{C}=10mA , V_{CE}=7.5V and at room temperature h_{fe}=100 , h_{ie} =1100 , A_{ie}=40 at 1MHz and Cc=3 pf. Find f_{β} , f_{T }, Ce , r_{bꞌe} and r_{bbꞌ}.

This problem is to be attempted similar to the problem 5 of the tutorial, i.e., by closing the cap and subtracting the contribution due to the cap. The divergence being 3, the flux from the closed cone is 3 times the volume of the cone which gives The contribution from the top face (which is a disk of radius 2 ) is . Thus the net flux is zero. (You can also try to get this result directly as done in problem 4, where we showed that the flux from the curved surface is zero).

6. Determine the voltage gain for the following circuits given in Fig.6.

Fig.6

7. Design the circuit given in Fig.7 for a voltage gain of 30 and a power budget of 15mW. Assume voltage drop across R_{s} is equal to the overdrive voltage of the transistor and R_{D}=400 Ω.

Fig.7

8. In the following amplifier circuit shown in Fig.8 small signal output resistance R_{out}=R_{outa}//R_{outb}, where Routais the resistance seen from the drain of M_{2} and R_{outb} is the resistance seen from drain of M_{3}.

If I_{D1}=2I_{D2}

- Show that only depends on the ratio of gate overdrive voltage of M
_{2} & M_{3}.
- Determine the bias currents and size of all transistors if the following constraints are considered.Bias all the transistors in the saturation region. I
_{D2}=100µA ,V_{GST3}=3V_{GS2}, .Minimum voltage gain of 5000.
- Determine

Fig.8

9. The current mirror shown in the Fig.9 should satisfy the following conditions.

for all transistors . Iref =1µA,Iout=10µA.Gate overdrive V_{GST}=200mV for M_{1}and M_{2}.

- Find Vbias and size of all transistors such that V
_{outmin} can reach to its minimum possible value if V_{GSTmin}=150mV for M_{3 }& M_{4}.Determine minimum possible value of V_{outmin}.
- Find output resistance of current mirror.

Fig.9

10. Design the commongate stage of the given circuit in Fig.10 which employs the current source M_{3} as the load to achieve a voltage gain .Neglect λ of M_{1} . Assuming M_{3}= 400/1 , λn=0.1V^{-1} , λp = 0.2 V^{-1},design the circuit for a voltage gain of 100 an input impedance of 200 Ω and a power budget of 30mW.

Fig.10

11. Due to manufacturing error,a parasitic resistance R_{P} has appeared in series with the source of M_{1} as shown in figure . Assume λ =0.Detremine the input and output poles of the circuit and plot the bode diagram.

Fig.11

12. Construct the bodeplot of and find the poles and zeroes.

Fig.12

13. Design a PMOS differential amplifier for the following specifications. =100 , I_{REF}=I=500µA . The dc voltage at the gates of M_{6} and M_{7} is 2.5V. The DC voltage at the gate of M_{7 }, M_{4 }and M_{5} is -2.5 V . The µ_{nCox}= 3µ_{pCox}=120µA/ V^{2}, Vtn=|Vtp|= 0.7V ,= ||=30V.

- Find the value of R & W/L ratios of all transistors. Find A
_{d} and A_{c}.
- Find the input commonmode range.
- Find the allowable range of the output voltage.

Fig.13

14. For the given circuit in Fig.14 draw the half circuit for both differential and common mode and compute both differential and common mode gain.

Fig.14

15. For the given circuit in Fig.15 draw the half circuit for both differential and commonmode and compute both differential and common mode gain.

Fig.15

16. A typical differential Amplifier shown in Fig.16 has interesting combination of loads which is parallel combination of current source load and diode connected load. Evaluate V_{out} =V_{01} - V_{02} and differential gain A_{vdm}.Given λn =0.04/V,λp=0.06/V , M_{1}= M_{2}=50/0.5 ,Iss=5mA, βnꞌ=50uA/V^{2} βpꞌ=16µA/V^{2},M_{3}=M_{4}=10/0.5,M_{5}=M_{6}=40/0.5.What would have been A_{vdm} value if the loads are only diode connected load instead of M_{3 }& M_{5} combination.

Fig.16

17. Design all of the W/L values of every transistor of this opamp to meet the following specifications :

Find differential gain, power dissipation and V_{Bp} & V_{Bn}.
SR= ±20V/µs , =3V , =0.8V, =1.2V , =3V and
GB=40MHz.

Fig.17

18. . In the two stage feedback amplifier shown in Fig.18 , the transistors are identical and have h_{fe}=100 and h_{re}=10K Ω, h_{re}=0and h_{oe} =0.Calculate

i)A_{if}=Io/Is

ii)R_{if}=Vi/Is

iii)Aꞌ_{if}=Io/Iiꞌ,

iv)A_{vf}=Vo/Vs where Vs=IsRs

Fig.18

19. For the given circuit shown in Fig.19 ,assume λ =0

- Find the type of feedback.
- Assume R
_{F} is very large and breaking the loop at the gate of M_{2} , Calculate the loop gain and prove what type of feedback it is .
- If Io is replaced by R
_{L}, find the closed loop input and output impedances of the circuit.

Fig.19

20. Consider the feedback circuit shown in Fig.20, assume V_{A}=α

- Suppose the output quantity of interest is the collector current of Q
_{2},I_{out}.Assuming R_{M} is very small and R_{F} is very large determine the closed loop gain and input and output impedances of the circuit.
- Now suppose the output quantity of interest is Vout. Assume R
_{F} is very large, compute the closed loop gain, input and output impedances of the circuit .

Fig.20

21. For the given circuits

- Calculate the loopgain.
- Find the closed loop gain.Assume the opamp exhibits an open loop gain of A
_{1}.

Fig.21

22. . Design an opamp circuit to provide an outputVo = -(6V1+ + . Choose relatively low values of resistances but ones for which the input current (from each input signal source) does not exceed 0.1mAfor 1V input signal.

23. For the given circuit in Fig.23 find .

Fig.23

24. For the given opamp circuit in Fig.24

- Find the input impedance.
- Design the resistance values for a gain of 1000 with Ri=α.

Fig.24

25. Design a bandpass filter with f_{o}=1MHz and Q=10 and unity resonance gain.
Find H_{OBP},ω_{O} and Q for C_{1}=C_{2}=Cand R_{1}=R_{2}=R.

Fig.25