mantle[81]:> fix wire $m $l

################### Starting Standard fix wire ####################

MSG-10 While running 'check model /work/aes_cipher_top/aes_cipher_top -level start_wiring':
CK-5 Collecting data on model aes_cipher_top .....
CK-7 Report for model /work/aes_cipher_top/aes_cipher_top
CK-6 Model /work/aes_cipher_top/aes_cipher_top passed fix route-level sanity check
CK-15 Use 'report model /work/aes_cipher_top/aes_cipher_top' to view model statistics.
MSG-10 While running 'run route stub /work/aes_cipher_top/aes_cipher_top':
STUB-301 #stdcells analyzed = 11988 (47679 pins)
STUB-302 41.08% pins are left stub-routable
STUB-302 45.03% pins are right stub-routable
STUB-302 0.00% pins are bottom stub-routable
STUB-302 0.00% pins are top stub-routable
STUB-304 13.10% models can be routed through horizontally
STUB-304 0.00% models can be routed through vertically
STUB-303 horizontal stub routing will be performed (based on analysis)
STUB-20 Magma Design Flow -- Stub Routing ...
STUB-10 2223 nets to be stub-routed
STUB-12 518 out of 2223 candidate nets have been stub-routed ( 4 seconds)
STUB-13 1141 out of 2223 candidate nets have non-first-layer-stubroutable pins
STUB-25 (post-stub-routing) 518 nets (4.23% of total) are stub-routed
HGR-97 Using high global routing effort
HGR-98 user specified topmost routing layer METAL8, botmost METAL1
HGR-55 Fine Grid Dim: 97 col * 108 row * 8 layer, Area: 400 * 400 um2
HGR-71 Design aes_cipher_top has 11988 cells (0 macro, 0 fixed, 0 off-row)
HGR-71 Analyzed geometries in 11988 real, 0 super cells
HGR-55
HGR-55 ------Pre Global Routing Obstruction Estimation----------------------
HGR-55 LAYER METAL1(H) METAL2(V) METAL3(H) METAL4(V) METAL5(H) METAL6(V) METAL7(H) METAL8(V)
HGR-55 Obstruction 91.7% 12.1% 7.0% 15.4% 29.0% 28.0% 0.3% 1.0%
HGR-55 ----------------------------------------------------------------------
HGR-96 11732 nets, MinSpanTree wire len = 0.480326m
HGR-92 518 stub-routed nets, 2 power nets, 0 clock nets, 0 dont-route nets are ignored
HGR-99 19 nets have layer assignment.
HGR-160 ------------------ Routing Cost Schedule 0 ---------------------
HGR-111 G>100%%:# overflow grids; Trk>100%%(A/P): average/peak # overflow track
HGR-111 --LAYER--| --G>85%-- | --G>100%--|-Trk>100%(A/P)|--WireLen(m)-|
HGR-111 METAL1(H)| 9401(89.7%)| 0( 0.0%)| 0.0/0 | 0.000045 |
HGR-111 METAL2(V)| 6107(58.2%)| 95( 0.9%)| 1.0/1 | 0.085974 |
HGR-111 METAL3(H)| 3925(37.4%)| 641( 6.1%)| 1.1/3 | 0.138379 |
HGR-111 METAL4(V)| 1148(10.9%)| 0( 0.0%)| 0.0/0 | 0.060672 |
HGR-111 METAL5(H)| 3270(31.2%)| 7( 0.0%)| 1.0/1 | 0.073865 |
HGR-111 METAL6(V)| 3271(31.2%)| 0( 0.0%)| 0.0/0 | 0.078804 |
HGR-111 METAL7(H)| 1( 0.0%)| 0( 0.0%)| 0.0/0 | 0.023074 |
HGR-111 METAL8(V)| 2( 0.0%)| 0( 0.0%)| 0.0/0 | 0.017046 |
HGR-111 SUM | 27125(32.3%)| 743( 0.8%)| 1.1/3 | 0.477863 |
HGR-160 ------------------ Routing Cost Schedule 1 ---------------------
HGR-111 G>100%%:# overflow grids; Trk>100%%(A/P): average/peak # overflow track
HGR-111 --LAYER--| --G>85%-- | --G>100%--|-Trk>100%(A/P)|--WireLen(m)-|
HGR-111 METAL1(H)| 9401(89.7%)| 0( 0.0%)| 0.0/0 | 0.000053 |
HGR-111 METAL2(V)| 6004(57.3%)| 52( 0.4%)| 1.0/1 | 0.085253 |
HGR-111 METAL3(H)| 3978(37.9%)| 118( 1.1%)| 1.0/2 | 0.136160 |
HGR-111 METAL4(V)| 1175(11.2%)| 0( 0.0%)| 0.0/0 | 0.062934 |
HGR-111 METAL5(H)| 3350(31.9%)| 0( 0.0%)| 0.0/0 | 0.075972 |
HGR-111 METAL6(V)| 3275(31.2%)| 0( 0.0%)| 0.0/0 | 0.079048 |
HGR-111 METAL7(H)| 1( 0.0%)| 0( 0.0%)| 0.0/0 | 0.023268 |
HGR-111 METAL8(V)| 2( 0.0%)| 0( 0.0%)| 0.0/0 | 0.017069 |
HGR-111 SUM | 27186(32.4%)| 170( 0.2%)| 1.0/2 | 0.479760 |
HGR-160 ------------------ Routing Cost Schedule 2 ---------------------
HGR-111 G>100%%:# overflow grids; Trk>100%%(A/P): average/peak # overflow track
HGR-111 --LAYER--| --G>85%-- | --G>100%--|-Trk>100%(A/P)|--WireLen(m)-|
HGR-111 METAL1(H)| 9401(89.7%)| 0( 0.0%)| 0.0/0 | 0.000057 |
HGR-111 METAL2(V)| 5969(56.9%)| 16( 0.1%)| 1.0/1 | 0.084957 |
HGR-111 METAL3(H)| 3937(37.5%)| 75( 0.7%)| 1.0/2 | 0.135377 |
HGR-111 METAL4(V)| 1188(11.3%)| 0( 0.0%)| 0.0/0 | 0.063642 |
HGR-111 METAL5(H)| 3359(32.0%)| 0( 0.0%)| 0.0/0 | 0.076809 |
HGR-111 METAL6(V)| 3274(31.2%)| 0( 0.0%)| 0.0/0 | 0.079118 |
HGR-111 METAL7(H)| 1( 0.0%)| 0( 0.0%)| 0.0/0 | 0.023426 |
HGR-111 METAL8(V)| 2( 0.0%)| 0( 0.0%)| 0.0/0 | 0.017069 |
HGR-111 SUM | 27131(32.3%)| 91( 0.1%)| 1.0/2 | 0.480458 |
HGR-160 ------------------ Routing Cost Schedule 3 ---------------------
HGR-111 G>100%%:# overflow grids; Trk>100%%(A/P): average/peak # overflow track
HGR-111 --LAYER--| --G>85%-- | --G>100%--|-Trk>100%(A/P)|--WireLen(m)-|
HGR-111 METAL1(H)| 9401(89.7%)| 0( 0.0%)| 0.0/0 | 0.000062 |
HGR-111 METAL2(V)| 5966(56.9%)| 11( 0.1%)| 1.0/1 | 0.084924 |
HGR-111 METAL3(H)| 3931(37.5%)| 42( 0.4%)| 1.0/1 | 0.135104 |
HGR-111 METAL4(V)| 1197(11.4%)| 0( 0.0%)| 0.0/0 | 0.063974 |
HGR-111 METAL5(H)| 3375(32.2%)| 0( 0.0%)| 0.0/0 | 0.077161 |
HGR-111 METAL6(V)| 3280(31.3%)| 0( 0.0%)| 0.0/0 | 0.079266 |
HGR-111 METAL7(H)| 1( 0.0%)| 0( 0.0%)| 0.0/0 | 0.023513 |
HGR-111 METAL8(V)| 2( 0.0%)| 0( 0.0%)| 0.0/0 | 0.017069 |
HGR-111 SUM | 27153(32.3%)| 53( 0.0%)| 1.0/1 | 0.481075 |
HGR-111 G>100%%:# overflow grids; Trk>100%%(A/P): average/peak # overflow track
HGR-111 --LAYER--| --G>85%-- | --G>100%--|-Trk>100%(A/P)|--WireLen(m)-|
HGR-111 METAL1(H)| 9401(89.7%)| 0( 0.0%)| 0.0/0 | 0.000062 |
HGR-111 METAL2(V)| 5820(55.5%)| 11( 0.1%)| 1.0/1 | 0.084924 |
HGR-111 METAL3(H)| 3931(37.5%)| 42( 0.4%)| 1.0/1 | 0.135104 |
HGR-111 METAL4(V)| 1197(11.4%)| 0( 0.0%)| 0.0/0 | 0.063974 |
HGR-111 METAL5(H)| 3375(32.2%)| 0( 0.0%)| 0.0/0 | 0.077161 |
HGR-111 METAL6(V)| 3280(31.3%)| 0( 0.0%)| 0.0/0 | 0.079266 |
HGR-111 METAL7(H)| 1( 0.0%)| 0( 0.0%)| 0.0/0 | 0.023513 |
HGR-111 METAL8(V)| 2( 0.0%)| 0( 0.0%)| 0.0/0 | 0.017069 |
HGR-111 SUM | 27007(32.2%)| 53( 0.0%)| 1.0/1 | 0.481075 |
HGR-203 Finish collecting timing slack: CPU= 3.7s, PMem= 233.2MB
HGR-97 Using high global routing effort
HGR-98 user specified topmost routing layer METAL8, botmost METAL1
HGR-55 Fine Grid Dim: 97 col * 108 row * 8 layer, Area: 400 * 400 um2
HGR-71 Design aes_cipher_top has 11988 cells (0 macro, 0 fixed, 0 off-row)
HGR-71 Analyzed geometries in 11988 real, 0 super cells
HGR-55
HGR-55 ------Pre Global Routing Obstruction Estimation----------------------
HGR-55 LAYER METAL1(H) METAL2(V) METAL3(H) METAL4(V) METAL5(H) METAL6(V) METAL7(H) METAL8(V)
HGR-55 Obstruction 91.7% 12.1% 7.0% 15.4% 29.0% 28.0% 0.3% 1.0%
HGR-55 ----------------------------------------------------------------------
HGR-96 11732 nets, MinSpanTree wire len = 0.480326m
HGR-92 518 stub-routed nets, 2 power nets, 0 clock nets, 0 dont-route nets are ignored
HGR-99 19 nets have layer assignment.
HGR-160 ------------------ Routing Cost Schedule 0 ---------------------
HGR-111 G>100%%:# overflow grids; Trk>100%%(A/P): average/peak # overflow track
HGR-111 --LAYER--| --G>85%-- | --G>100%--|-Trk>100%(A/P)|--WireLen(m)-|
HGR-111 METAL1(H)| 9401(89.7%)| 0( 0.0%)| 0.0/0 | 0.000057 |
HGR-111 METAL2(V)| 5990(57.1%)| 13( 0.1%)| 1.0/1 | 0.085039 |
HGR-111 METAL3(H)| 3916(37.3%)| 90( 0.8%)| 1.0/1 | 0.134930 |
HGR-111 METAL4(V)| 1193(11.3%)| 0( 0.0%)| 0.0/0 | 0.063583 |
HGR-111 METAL5(H)| 3349(31.9%)| 1( 0.0%)| 1.0/1 | 0.076971 |
HGR-111 METAL6(V)| 3282(31.3%)| 0( 0.0%)| 0.0/0 | 0.079262 |
HGR-111 METAL7(H)| 1( 0.0%)| 0( 0.0%)| 0.0/0 | 0.023699 |
HGR-111 METAL8(V)| 2( 0.0%)| 0( 0.0%)| 0.0/0 | 0.017113 |
HGR-111 SUM | 27134(32.3%)| 104( 0.1%)| 1.0/1 | 0.480657 |
HGR-191 .
HGR-191 ----------------------- Collecting Timing Slack ---------------------
HGR-191 Detected 0 nets that have detours as well as negative slack (the worst slack was 0p, average negative slack was 0p)
HGR-191 0 Nets with negative slack will be rerouted to minimize their wirelength.
HGR-191 1 clock net with detours be rerouted to minimize their wirelength.
HGR-111 G>100%%:# overflow grids; Trk>100%%(A/P): average/peak # overflow track
HGR-111 --LAYER--| --G>85%-- | --G>100%--|-Trk>100%(A/P)|--WireLen(m)-|
HGR-111 METAL1(H)| 9401(89.7%)| 0( 0.0%)| 0.0/0 | 0.000057 |
HGR-111 METAL2(V)| 5990(57.1%)| 13( 0.1%)| 1.0/1 | 0.085039 |
HGR-111 METAL3(H)| 3916(37.3%)| 90( 0.8%)| 1.0/1 | 0.134930 |
HGR-111 METAL4(V)| 1193(11.3%)| 0( 0.0%)| 0.0/0 | 0.063583 |
HGR-111 METAL5(H)| 3349(31.9%)| 1( 0.0%)| 1.0/1 | 0.076971 |
HGR-111 METAL6(V)| 3282(31.3%)| 0( 0.0%)| 0.0/0 | 0.079262 |
HGR-111 METAL7(H)| 1( 0.0%)| 0( 0.0%)| 0.0/0 | 0.023699 |
HGR-111 METAL8(V)| 2( 0.0%)| 0( 0.0%)| 0.0/0 | 0.017113 |
HGR-111 SUM | 27134(32.3%)| 104( 0.1%)| 1.0/1 | 0.480657 |
CMD-8 cputime 0.2 minutes, walltime 0.2 minutes, process memory 234.3 MB, peak memory 245.6 MB, command "run route global /work/aes_cipher_top/aes_cipher_top"
MSG-10 While running 'run wire space /work/aes_cipher_top/aes_cipher_top':
WIRE-707 Total 0 nets are changed to use double spacing rule
WIRE-706 Initial slack = 368.4ps Final slack = 368.4ps
MSG-10 While running 'run route track /work/aes_cipher_top/aes_cipher_top -optimize':
TR-1 ############ Starting Track Routing ############
TR-1 Routing model aes_cipher_top with 97 columns, 108 rows and 8 routing layers
TR-26 Track router will center tracks on horizontal fine grid 1 and vertical fine grid 2.
TR-26 You can override these selections with model integer attributes: track_hor_main_grid and track_ver_main_grid
TR-8 Track routing layer METAL1
TR-8 Track routing layer METAL3
TR-9 Track overflow on layer METAL3 is 0.04% buckets overflowed, average/peak overflow is 1.0/1 tracks per bucket
TR-8 Track routing layer METAL5
TR-9 Track overflow on layer METAL5 is 0.55% buckets overflowed, average/peak overflow is 1.0/2 tracks per bucket
TR-8 Track routing layer METAL7
TR-8 Track routing layer METAL2
TR-9 Track overflow on layer METAL2 is 0.04% buckets overflowed, average/peak overflow is 1.0/1 tracks per bucket
TR-8 Track routing layer METAL4
TR-9 Track overflow on layer METAL4 is 0.09% buckets overflowed, average/peak overflow is 1.0/1 tracks per bucket
TR-8 Track routing layer METAL6
TR-9 Track overflow on layer METAL6 is 0.07% buckets overflowed, average/peak overflow is 1.0/1 tracks per bucket
TR-8 Track routing layer METAL8
TR-10 Overall track overflow is 0.1% buckets overflowed, average/peak overflow is 1.0/2 tracks per bucket
TR-12 Track routing elapsed time 13.00 seconds, cpu time 12.79 seconds
MISC-311 detected 0 nontrivial short (93254 segments)
MISC-312 total nontrivial short is 0u long, worst-case is 1261281056u long
MISC-311 detected 0 nontrivial spacing (93254 segments)
MISC-312 total nontrivial spacing is 0u long, worst-case is 1264853344u long
CMD-8 cputime 0.2 minutes, walltime 0.2 minutes, process memory 234.3 MB, peak memory 245.6 MB, command "run route track /work/aes_cipher_top/aes_cipher_top -optimize"
MSG-10 While running 'run route power2 pin /work/aes_cipher_top/aes_cipher_top -cell_type standard_cell':
PWR-258 Updated 0 eco standard cells power connections; If necessary, please update new Pad/Macro cells by force plan net
PWR-127 If power via violations exist, please use 'run route power2 post_route_refine' to resolve them.
MSG-10 While running 'check route spacing_short -power_only /work/aes_cipher_top/aes_cipher_top':
POST-986 detected a total of 20 non-trivial fat geometries
POST-803 Detected 0 different-net preroute violations:
POST-805 #short = 0, #spacing = 0
POST-804 Detected 0 different-net non-preroute violations:
POST-805 #short = 0, #spacing = 0
MSG-10 While running 'run route final /work/aes_cipher_top/aes_cipher_top -singlepass':
CK-7 Report for model /work/aes_cipher_top/aes_cipher_top
CK-568 WARNING: THE MODEL /work/aes_cipher_top/aes_cipher_top contains 24 cells which are off the placement grid. Use the '-print off_placement_grid_cells' option to print these cells)
POST-30 performing spectral analysis...
POST-31 layer METAL1 has spectral frequency/offset = 2/0 (86.15% confidence)
POST-31 layer METAL2 has spectral frequency/offset = 4/2 (100.00% confidence)
POST-31 layer METAL3 has spectral frequency/offset = 2/1 (100.00% confidence)
POST-31 layer METAL4 has spectral frequency/offset = 4/2 (100.00% confidence)
POST-31 layer METAL5 has spectral frequency/offset = 2/1 (100.00% confidence)
POST-31 layer METAL6 has spectral frequency/offset = 4/2 (100.00% confidence)
POST-31 layer METAL7 has spectral frequency/offset = 2/1 (100.00% confidence)
POST-31 layer METAL8 has spectral frequency/offset = 12/2 (100.00% confidence)
TY-100 >>>>> Full detailed routing of model /work/aes_cipher_top/aes_cipher_top <<<<
DR-987 initial connectivity analysis on /work/aes_cipher_top/aes_cipher_top...
DR-988 12012 cells (11988 of which are nonsplitcells), 12276 nets...
DR-963 {lowest, highest} layers = {METAL1, METAL8}
DR-964 signal-specific = {METAL1, METAL8} (same as default)
DR-964 clock-specific = {METAL1, METAL8} (same as default)
DR-964 power-specific = {METAL1, METAL8} (same as default)
DR-961 detected 0 nondefault rules:
DR-985 2% empty, 1% simple, 6% complex segments, and 91% complex pins
DR-989 initial connectivity analysis on /work/aes_cipher_top/aes_cipher_top... done
TY-10 >>> Routing 2640 maze routing regions (48 rows by 55 columns)
-- --
---------- D E T A I L E D R O U T I N G S T A T I S T I C S ----------
Generated for user temp on host vlsi2 on Thu Mar 1 15:34:46 2007
Model: /work/aes_cipher_top/aes_cipher_top

Cell Statistics s - legend -

Split cells:


Dimensions
Chip Width,Height: 0.400mm x 0.400mm= 0.160mm2 (a)
Chip Aspect ratio (w/h): 1.00
Core Width,Height: 0.395mm x 0.391mm= 0.154mm2
Cell rows & area mm2
Usable cell row area mm2 (r)
Buckets: 97 x 108 = 10476

Utilizations
Cell row utilization: 0.0% ((c)/r)
Total utilization: 70.7% ((c)/a)

Floorplans

Name : /work/aes_cipher_top/aes_cipher_top/floorplan:aes_cipher_top (primary)

 

 

Total utilization : 70 % ( (m + s + p) / (A - f) )
Cell row utilization : 73 % ( s / (a - m) )


Wire statistics
Layer | -- Segment Statistics -- | -- Wire Statistics --
METAL1: 0.000 ( 0.0%) in 13 | 0.006 ( 1.2%) in 9167
METAL2: 0.099 (19.8%) in 41563 | 0.111 (21.3%) in 59348
METAL3: 0.138 (27.5%) in 28506 | 0.140 (26.9%) in 30163
METAL4: 0.067 (13.3%) in 12991 | 0.067 (12.8%) in 12556
METAL5: 0.077 (15.4%) in 5937 | 0.077 (14.8%) in 5421
METAL6: 0.080 (15.9%) in 2944 | 0.079 (15.1%) in 2646
METAL7: 0.023 ( 4.7%) in 932 | 0.023 ( 4.5%) in 914
METAL8: 0.017 ( 3.3%) in 368 | 0.017 ( 3.3%) in 418
Total : 0.50170 meter in 93254 | 0.52034 meter in 120633 wires

Signal wire length: 0.520 meter in 120633 wires

Prerouted wires (pwr/clk): 0.074meter in 3888 wires (14.3%)
Prerouted segments (pwr/clk): 0.000meter in 0 segs (0.0%)
Average net wire length: 42um in 9.8 wires
Average net segment length: 41um in 7.6 legs

Via statistics
Total via count: 128825 of which:
in layer 12: 48833 (= 37.91% in VIA12)
in layer 13: 44704 (= 34.70% in VIA23)
in layer 14: 20911 (= 16.23% in VIA34)
in layer 15: 7761 (= 6.02% in VIA45)
in layer 16: 4812 (= 3.74% in VIA56)
in layer 17: 1115 (= 0.87% in VIA67)
in layer 18: 689 (= 0.53% in VIA78)

Routing statistics
Total violation count: 577 (3789 spot violations)
Spacing violations (spots): 2002
Shorts (spots): 1787 (causing short circuits)
Nets with >= 1 violation: 885 (either short or spacing)
Buckets with >= 1 violation: 5.43%

-> Please note that the violation checker does not necessarily capture
all mask errors.
-> The above statistics report the result of the latest violation check.
It is possible that this is not consistent anymore with the current
state of the design. When in doubt, re-run the checker using
'check route spacing_short' or 'check route drc'.
CMD-8 cputime 2.0 minutes, walltime 2.0 minutes, process memory 240.7 MB, peak memory 245.6 MB, command "run route final /work/aes_cipher_top/aes_cipher_top -singlepass"
MSG-10 While running 'run route refine -type open /work/aes_cipher_top/aes_cipher_top':
POST-1 Detected 1 regular nets with opens (out of 12276 nets)
POST-7 of the 1 nets with opens, 0 are clock and 0 are power
POST-2 #nets with 2 components = 1
POST-3 #nets with 3 components = 0
POST-4 #nets with 4 to 20 components = 0
POST-8 #nets with 21 or more components = 0
POST-6 maximum #components = 2 (us32.N1189)
POST-5 maximum brute-force patchup is 5.98 microns long (us32.N1189)
MSG-10 While running 'check route spacing_short /work/aes_cipher_top/aes_cipher_top':
POST-986 detected a total of 135 non-trivial fat geometries
POST-803 Detected 0 different-net preroute violations:
POST-805 #short = 0, #spacing = 0
POST-804 Detected 5302 different-net non-preroute violations:
POST-805 #short = 2637, #spacing = 2665
MSG-10 While running 'run route final -incremental -regular /work/aes_cipher_top/aes_cipher_top':
TY-101 >>>>> Incremental detailed routing of model /work/aes_cipher_top/aes_cipher_top <<<<
TY-16 R&R regular scheme, 14 by 14 tracks (2.42 buckets), 5302 DRC spots
TY-6 R&R: 221 spots, rerouted 389 tiles, cleaned 5081 spots in 8s
TY-16 R&R autofocus scheme, 7 by 7 tracks (0.61 buckets), 221 DRC spots
TY-6 R&R: 159 spots, rerouted 71 tiles, cleaned 62 spots in 1s
TY-2 >> Autofocus terminated: no candidates left <<<<<<<<
TY-16 R&R autofocus scheme, 22 by 22 tracks (5.98 buckets), 159 DRC spots
TY-6 R&R: 79 spots, rerouted 27 tiles, cleaned 80 spots in 1s
TY-2 >> Autofocus terminated: no candidates left <<<<<<<<
TY-16 R&R autofocus scheme, 9 by 9 tracks (1.00 buckets), 79 DRC spots
TY-6 R&R: 79 spots, rerouted 23 tiles, cleaned 0 spots in 0s
TY-2 >> Autofocus terminated: no candidates left <<<<<<<<
CMD-8 cputime 0.2 minutes, walltime 0.2 minutes, process memory 241.2 MB, peak memory 245.6 MB, command "run route final -incremental -regular /work/aes_cipher_top/aes_cipher_top"
MSG-10 While running 'run route final -incremental -regular -reroute_tile_width 30 /work/aes_cipher_top/aes_cipher_top':
TY-101 >>>>> Incremental detailed routing of model /work/aes_cipher_top/aes_cipher_top <<<<
TY-16 R&R regular scheme, 30 by 30 tracks (11.11 buckets), 79 DRC spots
TY-6 R&R: 62 spots, rerouted 13 tiles, cleaned 17 spots in 1s
TY-16 R&R autofocus scheme, 15 by 15 tracks (2.78 buckets), 62 DRC spots
TY-6 R&R: 54 spots, rerouted 11 tiles, cleaned 8 spots in 0s
TY-2 >> Autofocus terminated because there were 6 failures in a row <<<<<<<<
TY-16 R&R autofocus scheme, 48 by 48 tracks (28.45 buckets), 54 DRC spots
TY-6 R&R: 48 spots, rerouted 9 tiles, cleaned 6 spots in 2s
TY-2 >> Autofocus terminated: no candidates left <<<<<<<<
TY-16 R&R autofocus scheme, 21 by 21 tracks (5.45 buckets), 48 DRC spots
TY-6 R&R: 48 spots, rerouted 5 tiles, cleaned 0 spots in 0s
TY-2 >> Autofocus terminated because there were 5 failures in a row <<<<<<<<
MSG-10 While running 'run route final -incremental -reroute_tile_width 60 -ratio 2.0 /work/aes_cipher_top/aes_cipher_top':
TY-101 >>>>> Incremental detailed routing of model /work/aes_cipher_top/aes_cipher_top <<<<
TY-16 R&R autofocus scheme, 60 by 30 tracks (22.23 buckets), 48 DRC spots
TY-6 R&R: 48 spots, rerouted 12 tiles, cleaned 0 spots in 2s
TY-2 >> Autofocus terminated: no candidates left <<<<<<<<
TY-16 R&R autofocus scheme, 30 by 15 tracks (5.56 buckets), 48 DRC spots
TY-6 R&R: 48 spots, rerouted 6 tiles, cleaned 0 spots in 0s
TY-2 >> Autofocus terminated because there were 6 failures in a row <<<<<<<<
TY-16 R&R autofocus scheme, 96 by 48 tracks (56.90 buckets), 48 DRC spots
TY-6 R&R: 48 spots, rerouted 7 tiles, cleaned 0 spots in 2s
TY-2 >> Autofocus terminated: no candidates left <<<<<<<<
TY-16 R&R autofocus scheme, 42 by 21 tracks (10.89 buckets), 48 DRC spots
TY-6 R&R: 48 spots, rerouted 5 tiles, cleaned 0 spots in 0s
TY-2 >> Autofocus terminated because there were 5 failures in a row <<<<<<<<
MSG-10 While running 'run route final -incremental -reroute_tile_width 60 -ratio 0.5 /work/aes_cipher_top/aes_cipher_top':
TY-101 >>>>> Incremental detailed routing of model /work/aes_cipher_top/aes_cipher_top <<<<
TY-16 R&R autofocus scheme, 30 by 60 tracks (22.23 buckets), 48 DRC spots
TY-6 R&R: 34 spots, rerouted 7 tiles, cleaned 14 spots in 1s
TY-2 >> Autofocus terminated: no candidates left <<<<<<<<
TY-16 R&R autofocus scheme, 15 by 30 tracks (5.56 buckets), 34 DRC spots
TY-6 R&R: 34 spots, rerouted 6 tiles, cleaned 0 spots in 0s
TY-2 >> Autofocus terminated because there were 6 failures in a row <<<<<<<<
TY-16 R&R autofocus scheme, 48 by 96 tracks (56.90 buckets), 34 DRC spots
TY-6 R&R: 34 spots, rerouted 6 tiles, cleaned 0 spots in 3s
TY-2 >> Autofocus terminated: no candidates left <<<<<<<<
TY-16 R&R autofocus scheme, 21 by 42 tracks (10.89 buckets), 34 DRC spots
TY-6 R&R: 34 spots, rerouted 5 tiles, cleaned 0 spots in 0s
TY-2 >> Autofocus terminated because there were 5 failures in a row <<<<<<<<
MSG-10 While running 'run route final -incremental -reroute_tile_width 30 /work/aes_cipher_top/aes_cipher_top -effort maximum':
TY-101 >>>>> Incremental detailed routing of model /work/aes_cipher_top/aes_cipher_top <<<<
TY-16 R&R autofocus scheme, 30 by 30 tracks (11.11 buckets), 34 DRC spots
TY-6 R&R: 0 spots, rerouted 6 tiles, cleaned 34 spots in 1s
TY-2 >> Autofocus terminated: no candidates left <<<<<<<<
MSG-10 While running 'run route final -incremental -reroute_tile_width 60 /work/aes_cipher_top/aes_cipher_top -effort maximum':
TY-101 >>>>> Incremental detailed routing of model /work/aes_cipher_top/aes_cipher_top <<<<
MSG-10 While running 'run route refine -route -incremental /work/aes_cipher_top/aes_cipher_top':
POST-217 Detected 0 maximum-width violations (polygon-based analysis)
POST-219 Detected 0 wires (0 regular, 0 preroute) with min-width violation
POST-119 Detected 0 wires (0 regular, 0 preroute) with off-grid violation
POST-166 Detected a total of 7 duplicate geometries
POST-747 There are some duplicated wires/vias
POST-1 Detected 0 regular nets with opens (out of 12276 nets)
POST-253 Detected a total of 0 multiport violations
POST-575 Incremental mode: skipping multiport correction on 12250 nets.
POST-253 Detected a total of 0 multiport violations
POST-575 Incremental mode: skipping multiport correction on 12250 nets.
POST-253 Detected a total of 0 multiport violations
POST-575 Incremental mode: skipping multiport detection on 12250 nets.
POST-253 Detected a total of 0 multiport violations
POST-359 Skipping via overhang checks because there are no non-trivial via overhang rules.
POST-53 Removed 67 loops
POST-1 Detected 0 regular nets with opens (out of 12276 nets)
POST-55 Removed 668 redundant hanging rectangles.
POST-56 Removed 4015 appendices.
POST-342 Detected 0 via-to-via violations (out of 0 vias total)
POST-343 there are 0 non-linear violations.
POST-344 there are 0 non-touching violations
POST-225 Detected 0 via-reliability violation(s)
POST-226 fixed 0 via-reliability violation(s) (0 DRCs)
POST-71 filled 2310 regular and 0 diagonal notches (0 DRC violations)
POST-921 detected 0 short-edge sequences (0 notches)
POST-21 fixed 5 diagonal width violations (0 DRCs)
POST-61 fixed 2 (0 with DRC violation) out of 2 island-rule violations
POST-222 fixed 0 holes violations (0 DRC)
POST-891 removed 507 microns of overlapping rectangles
POST-575 Incremental mode: skipping nontrivial fatwires detection on 8358 nets.
POST-986 detected a total of 145 non-trivial fat geometries
POST-803 Detected 0 different-net preroute violations:
POST-805 #short = 0, #spacing = 0
POST-804 Detected 0 different-net non-preroute violations:
POST-805 #short = 0, #spacing = 0
CMD-8 cputime 0.2 minutes, walltime 0.2 minutes, process memory 242.9 MB, peak memory 247.6 MB, command "run route refine -route -incremental /work/aes_cipher_top/aes_cipher_top"
MSG-10 While running 'run route final -incremental -reroute_tile_width 30 /work/aes_cipher_top/aes_cipher_top':
TY-101 >>>>> Incremental detailed routing of model /work/aes_cipher_top/aes_cipher_top <<<<
MSG-10 While running 'run route final -incremental -reroute_tile_width 40 /work/aes_cipher_top/aes_cipher_top -effort maximum':
TY-101 >>>>> Incremental detailed routing of model /work/aes_cipher_top/aes_cipher_top <<<<
MSG-10 While running 'run route refine /work/aes_cipher_top/aes_cipher_top':
POST-217 Detected 0 maximum-width violations (polygon-based analysis)
POST-219 Detected 0 wires (0 regular, 0 preroute) with min-width violation
POST-119 Detected 0 wires (0 regular, 0 preroute) with off-grid violation
POST-166 Detected a total of 7 duplicate geometries
POST-747 There are some duplicated wires/vias
POST-1 Detected 0 regular nets with opens (out of 12276 nets)
POST-253 Detected a total of 0 multiport violations
POST-253 Detected a total of 0 multiport violations
POST-253 Detected a total of 0 multiport violations
POST-253 Detected a total of 0 multiport violations
POST-359 Skipping via overhang checks because there are no non-trivial via overhang rules.
POST-53 Removed 12 loops
POST-1 Detected 0 regular nets with opens (out of 12276 nets)
POST-55 Removed 6 redundant hanging rectangles.
POST-56 Removed 20 appendices.
POST-342 Detected 0 via-to-via violations (out of 0 vias total)
POST-343 there are 0 non-linear violations.
POST-344 there are 0 non-touching violations
POST-225 Detected 0 via-reliability violation(s)
POST-226 fixed 0 via-reliability violation(s) (0 DRCs)
POST-986 detected a total of 160 non-trivial fat geometries
POST-71 filled 1 regular and 0 diagonal notches (0 DRC violations)
POST-921 detected 0 short-edge sequences (0 notches)
POST-21 fixed 0 diagonal width violations (0 DRCs)
POST-61 fixed 0 (0 with DRC violation) out of 0 island-rule violations
POST-222 fixed 0 holes violations (0 DRC)
POST-891 removed 123 microns of overlapping rectangles
POST-575 Incremental mode: skipping nontrivial fatwires detection on 12241 nets.
POST-986 detected a total of 1 non-trivial fat geometries
POST-803 Detected 0 different-net preroute violations:
POST-805 #short = 0, #spacing = 0
POST-804 Detected 5 different-net non-preroute violations:
POST-805 #short = 0, #spacing = 5
CMD-8 cputime 0.3 minutes, walltime 0.3 minutes, process memory 242.9 MB, peak memory 247.6 MB, command "run route refine /work/aes_cipher_top/aes_cipher_top"
MSG-10 While running 'check route antenna /work/aes_cipher_top/aes_cipher_top':
ANT-15 net key[4] has antenna rule violation...
ANT-14 pin u0.w_reg[3][4]/pin:D (SDFFQX1/mpin:D) at (5u, 163u) is 15% over on METAL6
ANT-15 net key[94] has antenna rule violation...
ANT-14 pin u0.w_reg[1][30]/pin:D (SDFFQX1/mpin:D) at (100u, 274u) is 2% over on METAL6
ANT-16 there are 2 antenna violations (2 nets)
ANT-91 of which 2 net(s) have model pins
ANT-91 of which 2 net(s) have zero-gate/diffusion output model pins
ANT-30 ------------------------------------------------------------------
ANT-31 Summary of violations (>1.0 means a violation)
ANT-32 layer <0.95 <1.0 | <1.2 <1.5 <2.0 <3.0 >=3.0 | max ratio
ANT-30 ------------------------------------------------------------------
ANT-34 METAL1 71058 - | - - - - - | 0.03
ANT-34 VIA12 70024 - | - - - - - | 0.06
ANT-34 METAL2 70024 - | - - - - - | 0.21
ANT-34 VIA23 63234 - | - - - - - | 0.12
ANT-34 METAL3 63234 - | - - - - - | 0.21
ANT-34 VIA34 49704 - | - - - - - | 0.09
ANT-34 METAL4 49704 - | - - - - - | 0.14
ANT-34 VIA45 36628 - | - - - - - | 0.06
ANT-34 METAL5 36628 - | - - - - - | 0.92
ANT-34 VIA56 26346 - | - - - - - | 0.05
ANT-34 METAL6 26344 1 | 1 - - - - | 1.10
ANT-34 VIA67 13236 - | - - - - - | 0.04
ANT-34 METAL7 13236 - | - - - - - | 0.78
ANT-34 VIA78 8846 - | - - - - - | 0.18
ANT-34 METAL8 8846 - | - - - - - | 0.05
Elapsed cpu time: 1.83 minutes (cpu usage 100.00%)
Effective routing speed: 0.009 seconds/net
------------------------------ E N D ------------------------------------

POST-121 -------------------------------------------------------------------
POST-121 Summary of short and spacing violations:
POST-121 statistics on shorts and spacing violations:
POST-121
POST-121 * different-net
POST-121 * short and spacing violation
POST-121 * involving at least one regular wire or via
POST-121
POST-121 * This report is based on previous, possibly outdated, checks.
POST-121 Please run "check route spacing_short" or "check route drc"
POST-121 for accurate reports.
POST-121 -------------------------------------------------------------------

statistics -- violation per layer...
layer short spacing total
------ ----- ------- -----
METAL1 - - -
VIA12 - - -
METAL2 - - -
VIA23 - - -
METAL3 - 5 5
VIA34 - - -
METAL4 - - -
VIA45 - - -
METAL5 - - -
VIA56 - - -
METAL6 - - -
VIA67 - - -
METAL7 - - -
VIA78 - - -
METAL8 - - -

statistics -- violation per net type...
net type short spacing
---------------------- ----- -------
clock nets - -
power and ground nets - -
wires and vias - 8
obstacles, cells, etc. - 2

violation per location (down model)...
model name score #instances #violations extra
--------------------------- ----- ---------- ----------- -----
/cl013lv/OAI2BB2X/OAI2BB2XL 0.04 142 5

statistics -- violation per error type...
error type #violations
---------- -----------
short -
spacing 5
total 5

POST-975 -------------------------------------------------------------------
POST-975 Summary of violations (DRC/attention rectangles)
POST-975
POST-975 SPCE: preroute spacing SHRT: preroute short offg: off grid
POST-975 spce: regular spacing shrt: regular short wdth: width
POST-975 ntch: notch open: open ilnd: island
POST-975 dgnl: diagonal width hole: hole mprt: multiport
POST-975 pwro: power open viar: via reliability viav: via-to-via
POST-975 dupl: duplicate shed: short-edge prot: protrusion
POST-975 viso: insufficient via overhang
POST-975
POST-975 * the following categories are not shown (no violations):
POST-975 {SPCE SHRT offg shrt wdth ntch open ilnd dgnl hole mprt pwro viar viav dupl shed prot viso}
POST-975
POST-975 * the following categories are shown (with violations):
POST-975 {spce}
POST-975
POST-975 * This report is based on previous, possibly outdated, checks.
POST-975 Please run "check route drc" for accurate reports.
POST-975 -------------------------------------------------------------------

DRC categories with violations:
layer spce
------ ----
METAL3 5
------ ----
layer spce
all 5

MSG-10 While running 'run route antenna -incremental /work/aes_cipher_top/aes_cipher_top':
ANT-17 Antenna Rule Sign-in Check Summary:
ANT-17 0 pins have unacceptable gate strength (#): <= 12.3u
ANT-17 0 pins have marginal gate strength (+): <= 24.6u
ANT-17 340 pins have acceptable gate strength (.): > 24.6u
ANT-17 0 pins have unacceptable diffusion strength (#): <= 5.5X
ANT-17 0 pins have marginal diffusion strength (+): <= 20.0X
ANT-17 252 pins have acceptable diffusion strength (.): > 20.0X
ANT-17 88 pins have waived diffusion strength criteria (w)
ANT-16 there are 2 antenna violations (2 nets)
ANT-26 12248 nets were not checked in incremental mode
POST-575 Incremental mode: skipping antenna correction on 12248 nets.
TY-16 R&R autofocus scheme, 30 by 30 tracks (11.11 buckets), 5 DRC spots
TY-6 R&R: 5 spots, rerouted 0 tiles, cleaned 0 spots in 0s
TY-2 >> Autofocus terminated: no candidates left <<<<<<<<
TY-16 R&R autofocus scheme, 15 by 15 tracks (2.78 buckets), 5 DRC spots
TY-6 R&R: 5 spots, rerouted 0 tiles, cleaned 0 spots in 0s
TY-2 >> Autofocus terminated: no candidates left <<<<<<<<
TY-16 R&R autofocus scheme, 48 by 48 tracks (28.45 buckets), 5 DRC spots
TY-6 R&R: 5 spots, rerouted 0 tiles, cleaned 0 spots in 0s
TY-2 >> Autofocus terminated: no candidates left <<<<<<<<
TY-16 R&R autofocus scheme, 21 by 21 tracks (5.45 buckets), 5 DRC spots
TY-6 R&R: 5 spots, rerouted 0 tiles, cleaned 0 spots in 0s
TY-2 >> Autofocus terminated: no candidates left <<<<<<<<
POST-951 #antenna violations got reduced by 2 (approximately)
ANT-16 there are 0 antenna violations (0 nets)
ANT-26 12250 nets were not checked in incremental mode
POST-575 Incremental mode: skipping antenna correction on 12250 nets.
TY-16 R&R autofocus scheme, 30 by 30 tracks (11.11 buckets), 5 DRC spots
TY-6 R&R: 5 spots, rerouted 0 tiles, cleaned 0 spots in 0s
TY-2 >> Autofocus terminated: no candidates left <<<<<<<<
TY-16 R&R autofocus scheme, 15 by 15 tracks (2.78 buckets), 5 DRC spots
TY-6 R&R: 5 spots, rerouted 0 tiles, cleaned 0 spots in 0s
TY-2 >> Autofocus terminated: no candidates left <<<<<<<<
TY-16 R&R autofocus scheme, 48 by 48 tracks (28.45 buckets), 5 DRC spots
TY-6 R&R: 5 spots, rerouted 0 tiles, cleaned 0 spots in 0s
TY-2 >> Autofocus terminated: no candidates left <<<<<<<<
TY-16 R&R autofocus scheme, 21 by 21 tracks (5.45 buckets), 5 DRC spots
TY-6 R&R: 5 spots, rerouted 0 tiles, cleaned 0 spots in 0s
TY-2 >> Autofocus terminated: no candidates left <<<<<<<<
POST-951 #antenna violations got reduced by 0 (approximately)
ANT-16 there are 0 antenna violations (0 nets)
ANT-26 12250 nets were not checked in incremental mode
ANT-30 ------------------------------------------------------------------
ANT-31 Summary of violations (>1.0 means a violation)
ANT-32 layer <0.95 <1.0 | <1.2 <1.5 <2.0 <3.0 >=3.0 | max ratio
ANT-30 ------------------------------------------------------------------
ANT-34 METAL1 - - | - - - - - | 0.00
ANT-34 VIA12 - - | - - - - - | 0.00
ANT-34 METAL2 - - | - - - - - | 0.00
ANT-34 VIA23 - - | - - - - - | 0.00
ANT-34 METAL3 - - | - - - - - | 0.00
ANT-34 VIA34 - - | - - - - - | 0.00
ANT-34 METAL4 - - | - - - - - | 0.00
ANT-34 VIA45 - - | - - - - - | 0.00
ANT-34 METAL5 - - | - - - - - | 0.00
ANT-34 VIA56 - - | - - - - - | 0.00
ANT-34 METAL6 - - | - - - - - | 0.00
ANT-34 VIA67 - - | - - - - - | 0.00
ANT-34 METAL7 - - | - - - - - | 0.00
ANT-34 VIA78 - - | - - - - - | 0.00
ANT-34 METAL8 - - | - - - - - | 0.00
MSG-10 While running 'run route final -incremental -regular /work/aes_cipher_top/aes_cipher_top':
TY-101 >>>>> Incremental detailed routing of model /work/aes_cipher_top/aes_cipher_top <<<<
TY-16 R&R regular scheme, 14 by 14 tracks (2.42 buckets), 5 DRC spots
TY-6 R&R: 0 spots, rerouted 1 tiles, cleaned 5 spots in 0s
MSG-10 While running 'check route antenna -incremental /work/aes_cipher_top/aes_cipher_top':
ANT-16 there are 0 antenna violations (0 nets)
ANT-26 12247 nets were not checked in incremental mode
ANT-30 ------------------------------------------------------------------
ANT-31 Summary of violations (>1.0 means a violation)
ANT-32 layer <0.95 <1.0 | <1.2 <1.5 <2.0 <3.0 >=3.0 | max ratio
ANT-30 ------------------------------------------------------------------
ANT-34 METAL1 172 - | - - - - - | 0.01
ANT-34 VIA12 172 - | - - - - - | 0.03
ANT-34 METAL2 172 - | - - - - - | 0.03
ANT-34 VIA23 170 - | - - - - - | 0.06
ANT-34 METAL3 170 - | - - - - - | 0.12
ANT-34 VIA34 170 - | - - - - - | 0.05
ANT-34 METAL4 170 - | - - - - - | 0.01
ANT-34 VIA45 78 - | - - - - - | 0.02
ANT-34 METAL5 78 - | - - - - - | 0.00
ANT-34 VIA56 - - | - - - - - | 0.00
ANT-34 METAL6 - - | - - - - - | 0.00
ANT-34 VIA67 - - | - - - - - | 0.00
ANT-34 METAL7 - - | - - - - - | 0.00
ANT-34 VIA78 - - | - - - - - | 0.00
ANT-34 METAL8 - - | - - - - - | 0.00

POST-121 -------------------------------------------------------------------
POST-121 Summary of short and spacing violations:
POST-121 statistics on shorts and spacing violations:
POST-121
POST-121 * different-net
POST-121 * short and spacing violation
POST-121 * involving at least one regular wire or via
POST-121
POST-121 * This report is based on previous, possibly outdated, checks.
POST-121 Please run "check route spacing_short" or "check route drc"
POST-121 for accurate reports.
POST-121 -------------------------------------------------------------------

POST-126 no violation is reported
POST-975 -------------------------------------------------------------------
POST-975 Summary of violations (DRC/attention rectangles)
POST-975
POST-975 SPCE: preroute spacing SHRT: preroute short offg: off grid
POST-975 spce: regular spacing shrt: regular short wdth: width
POST-975 ntch: notch open: open ilnd: island
POST-975 dgnl: diagonal width hole: hole mprt: multiport
POST-975 pwro: power open viar: via reliability viav: via-to-via
POST-975 dupl: duplicate shed: short-edge prot: protrusion
POST-975 viso: insufficient via overhang
POST-975
POST-975 * the following categories are not shown (no violations):
POST-975 {SPCE SHRT offg spce shrt wdth ntch open ilnd dgnl hole mprt pwro viar viav dupl shed prot viso}
POST-975
POST-975 * the following categories are shown (with violations):
POST-975 {}
POST-975
POST-975 * This report is based on previous, possibly outdated, checks.
POST-975 Please run "check route drc" for accurate reports.
POST-975 -------------------------------------------------------------------
MSG-10 While running 'run route final -incremental -regular /work/aes_cipher_top/aes_cipher_top':
TY-101 >>>>> Incremental detailed routing of model /work/aes_cipher_top/aes_cipher_top <<<<
MSG-10 While running 'run route antenna -incremental /work/aes_cipher_top/aes_cipher_top':
ANT-17 Antenna Rule Sign-in Check Summary:
ANT-17 0 pins have unacceptable gate strength (#): <= 12.3u
ANT-17 0 pins have marginal gate strength (+): <= 24.6u
ANT-17 340 pins have acceptable gate strength (.): > 24.6u
ANT-17 0 pins have unacceptable diffusion strength (#): <= 5.5X
ANT-17 0 pins have marginal diffusion strength (+): <= 20.0X
ANT-17 252 pins have acceptable diffusion strength (.): > 20.0X
ANT-17 88 pins have waived diffusion strength criteria (w)
ANT-16 there are 0 antenna violations (0 nets)
ANT-26 12250 nets were not checked in incremental mode
POST-575 Incremental mode: skipping antenna correction on 12250 nets.
POST-951 #antenna violations got reduced by 0 (approximately)
ANT-16 there are 0 antenna violations (0 nets)
ANT-26 12250 nets were not checked in incremental mode
ANT-30 ------------------------------------------------------------------
ANT-31 Summary of violations (>1.0 means a violation)
ANT-32 layer <0.95 <1.0 | <1.2 <1.5 <2.0 <3.0 >=3.0 | max ratio
ANT-30 ------------------------------------------------------------------
ANT-34 METAL1 - - | - - - - - | 0.00
ANT-34 VIA12 - - | - - - - - | 0.00
ANT-34 METAL2 - - | - - - - - | 0.00
ANT-34 VIA23 - - | - - - - - | 0.00
ANT-34 METAL3 - - | - - - - - | 0.00
ANT-34 VIA34 - - | - - - - - | 0.00
ANT-34 METAL4 - - | - - - - - | 0.00
ANT-34 VIA45 - - | - - - - - | 0.00
ANT-34 METAL5 - - | - - - - - | 0.00
ANT-34 VIA56 - - | - - - - - | 0.00
ANT-34 METAL6 - - | - - - - - | 0.00
ANT-34 VIA67 - - | - - - - - | 0.00
ANT-34 METAL7 - - | - - - - - | 0.00
ANT-34 VIA78 - - | - - - - - | 0.00
ANT-34 METAL8 - - | - - - - - | 0.00
MSG-10 While running 'run route final -incremental -regular /work/aes_cipher_top/aes_cipher_top':
TY-101 >>>>> Incremental detailed routing of model /work/aes_cipher_top/aes_cipher_top <<<<
MSG-10 While running 'run route refine -incremental /work/aes_cipher_top/aes_cipher_top':
POST-217 Detected 0 maximum-width violations (polygon-based analysis)
POST-219 Detected 0 wires (0 regular, 0 preroute) with min-width violation
POST-119 Detected 0 wires (0 regular, 0 preroute) with off-grid violation
POST-575 Incremental mode: skipping duplicate correction on 12236 nets.
POST-166 Detected a total of 7 duplicate geometries
POST-747 There are some duplicated wires/vias
POST-1 Detected 0 regular nets with opens (out of 12276 nets)
POST-575 Incremental mode: skipping multiport correction on 12212 nets.
POST-253 Detected a total of 0 multiport violations
POST-575 Incremental mode: skipping multiport correction on 12250 nets.
POST-253 Detected a total of 0 multiport violations
POST-575 Incremental mode: skipping multiport correction on 12250 nets.
POST-253 Detected a total of 0 multiport violations
POST-575 Incremental mode: skipping multiport detection on 12250 nets.
POST-253 Detected a total of 0 multiport violations
POST-359 Skipping via overhang checks because there are no non-trivial via overhang rules.
POST-575 Incremental mode: skipping loop correction on 12242 nets.
POST-53 Removed 0 loops
POST-1 Detected 0 regular nets with opens (out of 12276 nets)
POST-575 Incremental mode: skipping appendix correction on 12248 nets.
POST-55 Removed 0 redundant hanging rectangles.
POST-56 Removed 0 appendices.
POST-342 Detected 0 via-to-via violations (out of 0 vias total)
POST-343 there are 0 non-linear violations.
POST-344 there are 0 non-touching violations
POST-575 Incremental mode: skipping via reliability correction on 12236 nets.
POST-225 Detected 0 via-reliability violation(s)
POST-226 fixed 0 via-reliability violation(s) (0 DRCs)
POST-575 Incremental mode: skipping notch correction on 9875 nets.
POST-71 filled 0 regular and 0 diagonal notches (0 DRC violations)
POST-921 detected 0 short-edge sequences (0 notches)
POST-575 Incremental mode: skipping diagonal correction on 12258 nets.
POST-21 fixed 0 diagonal width violations (0 DRCs)
POST-61 fixed 0 (0 with DRC violation) out of 0 island-rule violations
POST-575 Incremental mode: skipping hole correction on 12236 nets.
POST-222 fixed 0 holes violations (0 DRC)
POST-575 Incremental mode: skipping overlap correction on 43 nets.
POST-891 removed 0 microns of overlapping rectangles
POST-575 Incremental mode: skipping nontrivial fatwires detection on 12247 nets.
POST-986 detected a total of 0 non-trivial fat geometries
POST-803 Detected 0 different-net preroute violations:
POST-805 #short = 0, #spacing = 0
POST-804 Detected 0 different-net non-preroute violations:
POST-805 #short = 0, #spacing = 0
MSG-10 While running 'run route final -incremental -regular /work/aes_cipher_top/aes_cipher_top':
TY-101 >>>>> Incremental detailed routing of model /work/aes_cipher_top/aes_cipher_top <<<<
MSG-10 While running 'check route antenna -incremental /work/aes_cipher_top/aes_cipher_top':
ANT-16 there are 0 antenna violations (0 nets)
ANT-26 12250 nets were not checked in incremental mode
ANT-30 ------------------------------------------------------------------
ANT-31 Summary of violations (>1.0 means a violation)
ANT-32 layer <0.95 <1.0 | <1.2 <1.5 <2.0 <3.0 >=3.0 | max ratio
ANT-30 ------------------------------------------------------------------
ANT-34 METAL1 - - | - - - - - | 0.00
ANT-34 VIA12 - - | - - - - - | 0.00
ANT-34 METAL2 - - | - - - - - | 0.00
ANT-34 VIA23 - - | - - - - - | 0.00
ANT-34 METAL3 - - | - - - - - | 0.00
ANT-34 VIA34 - - | - - - - - | 0.00
ANT-34 METAL4 - - | - - - - - | 0.00
ANT-34 VIA45 - - | - - - - - | 0.00
ANT-34 METAL5 - - | - - - - - | 0.00
ANT-34 VIA56 - - | - - - - - | 0.00
ANT-34 METAL6 - - | - - - - - | 0.00
ANT-34 VIA67 - - | - - - - - | 0.00
ANT-34 METAL7 - - | - - - - - | 0.00
ANT-34 VIA78 - - | - - - - - | 0.00
ANT-34 METAL8 - - | - - - - - | 0.00
MSG-10 While running 'force wire model final /work/aes_cipher_top/aes_cipher_top':
WIRE-21 Wire delay/capacitance mode for /work/aes_cipher_top/aes_cipher_top reset from global to final.
MSG-10 While running 'run route shielding /work/aes_cipher_top/aes_cipher_top -supply either -final':
POST-500 Inserting shields in model /work/aes_cipher_top/aes_cipher_top.
POST-599 Creating shield wires. cputime: 0.00 mt. total cputime: 15.30 mt. memory: 242.89 MB. peak memory: 247.63 MB.
POST-504 No shielding was required.
MSG-10 While running 'check route drc /work/aes_cipher_top/aes_cipher_top':
POST-166 Detected a total of 7 duplicate geometries
POST-747 There are some duplicated wires/vias/segments
POST-217 Detected 0 maximum-width violations (polygon-based analysis)
POST-219 Detected 0 wires (0 regular, 0 preroute) with min-width violation
POST-119 Detected 0 wires (0 regular, 0 preroute) with off-grid violation
POST-986 detected a total of 159 non-trivial fat geometries
POST-74 Detected 0 regular and 0 diagonal notches
POST-359 Skipping via overhang checks because there are no non-trivial via overhang rules.
POST-342 Detected 0 via-to-via violations (out of 0 vias total)
POST-343 there are 0 non-linear violations.
POST-344 there are 0 non-touching violations
POST-225 Detected 0 via-reliability violation(s)
POST-921 detected 0 short-edge sequences (0 notches)
POST-25 Detected 0 diagonal width violations
POST-62 detected 0 island-rule violations (0 at model pins)
POST-221 Detected 0 holes violations
POST-9 Detected 0 power/ground nets with opens (out of 26 nets)
POST-1 Detected 0 regular nets with opens (out of 12276 nets)
POST-253 Detected a total of 0 multiport violations
POST-575 Incremental mode: skipping nontrivial fatwires detection on 12252 nets.
POST-576 Incremental mode: skipping nontrivial fatwires detection on model.
POST-986 detected a total of 0 non-trivial fat geometries
POST-803 Detected 0 different-net preroute violations:
POST-805 #short = 0, #spacing = 0
POST-804 Detected 0 different-net non-preroute violations:
POST-805 #short = 0, #spacing = 0
POST-364 VIA layers : Number of Violations
POST-366 Total violation of VIA to VIA interlayer spacing: 0
POST-369 Total violation of Contact/VIA to Metal interlayer spacing: 0

POST-121 -------------------------------------------------------------------
POST-121 Summary of short and spacing violations:
POST-121 statistics on shorts and spacing violations:
POST-121
POST-121 * different-net
POST-121 * short and spacing violation
POST-121 * involving at least one regular wire or via
POST-121 -------------------------------------------------------------------

POST-126 no violation is reported
POST-975 -------------------------------------------------------------------
POST-975 Summary of violations (DRC/attention rectangles)
POST-975
POST-975 SPCE: preroute spacing SHRT: preroute short offg: off grid
POST-975 spce: regular spacing shrt: regular short wdth: width
POST-975 ntch: notch open: open ilnd: island
POST-975 dgnl: diagonal width hole: hole mprt: multiport
POST-975 pwro: power open viar: via reliability viav: via-to-via
POST-975 dupl: duplicate shed: short-edge prot: protrusion
POST-975 viso: insufficient via overhang
POST-975
POST-975 * the following categories are not shown (no violations):
POST-975 {SPCE SHRT offg spce shrt wdth ntch open ilnd dgnl hole mprt pwro viar viav dupl shed prot viso}
POST-975
POST-975 * the following categories are shown (with violations):
POST-975 {}
POST-975 -------------------------------------------------------------------
CMD-8 cputime 0.3 minutes, walltime 0.3 minutes, process memory 242.9 MB, peak memory 247.6 MB, command "check route drc /work/aes_cipher_top/aes_cipher_top"
MSG-10 While running 'export volcano snap/aes_cipher_top%fix-wire-final.volcano':
LAVA-26 Writing library /macro_lib
LAVA-26 Writing library /cl013lv
LAVA-26 Writing library /work
LAVA-26 Writing library /magma
LAVA-900 Successfully froze lava into volcano snap/aes_cipher_top%fix-wire-final.volcano: 3 seconds, 2 on cpu.
LAVA-248 Volcano file size: 58.2 MByte, data compression was not used.
LAVA-251 Data throughput 15.920 MB/s (3.66 s elapsed)
MSG-10 While running 'report timing path /work/aes_cipher_top/aes_cipher_top -number 100 -file snap/aes_cipher_top%fix-wire-final%timing.rpt':
EXTR-60 Setting the min_segment_resistance to 1.12 Ohm.
CMD-8 cputime 0.6 minutes, walltime 0.6 minutes, process memory 249.9 MB, peak memory 250.0 MB, command "report timing path /work/aes_cipher_top/aes_cipher_top -number 100 -file snap/aes_cipher_top%fix-wire-final%timing.rpt"

################### Finished Standard fix wire ####################

CMD-8 cputime 4.7 minutes, walltime 4.8 minutes, process memory 249.9 MB, peak memory 250.0 MB, command "fix wire /work/aes_cipher_top/aes_cipher_top /cl013lv"