mantle[74]:>report timing path $m
######################################################################
# Mantle analysis report
# Command:
#          report timing path \
#               /work/aes_cipher_top/aes_cipher_top 
# Date:    Thu Mar  1 15:24:14 2007
# Version: mantle version 4.1.57-linux24_x86_64 
# Delay Configuration:
#          config condition case worst
#          config condition parasitics max worst
#          force timing clockdelay /work/aes_cipher_top/aes_cipher_top computed
#          config timing borrow automatic on
#          config timing borrow method balance
#          config timing propagate constants combinational
#          config timing threshold delay  50.00  50.00  50.00  50.00
#          config timing threshold slew  10.00  90.00  10.00  90.00
#          config condition on_chip_variation off
#          config timing clockgating off
#          config timing propagate clockgating off
#          config timing crosstalk delay off
#          force wire model global /work/aes_cipher_top/aes_cipher_top
#          config capacitance congestion false
#          Library: cl013lv
#          Operating condition: slow/slow( P= 1.00, V= 0.90, T=125.00 )
#          lib_group: slow nominal: ( P= 1.00, V= 0.90, T=125.00 )
#          layer: METAL1 nominal: ( P=default_pro
cess, V=default_voltage, T=25.00 )
#          layer: METAL2 nominal: ( P=default_process, V=default_voltage, T=25.00 )
#          layer: METAL3 nominal: ( P=default_process, V=default_voltage, T=25.00 )
#          layer: METAL4 nominal: ( P=default_process, V=default_voltage, T=25.00 )
#          layer: METAL5 nominal: ( P=default_process, V=default_voltage, T=25.00 )
#          layer: METAL6 nominal: ( P=default_process, V=default_voltage, T=25.00 )
#          layer: METAL7 nominal: ( P=default_process, V=default_voltage, T=25.00 )
#          layer: METAL8 nominal: ( P=default_process, V=default_voltage, T=25.00 )
#          config cell process off -case both
#          config cell voltage off -case both
#          config cell temperature off -case both
######################################################################


#### Path 1 ##########################################################

Start       ld                    
End         text_in_r_reg[77]/E   
Reference   text_in_r_reg[77]/CK  
Path slack  372p                  

Reference arrival time                                1246  
+ Cycle adjust(source phase DEFAULT has zero period)     0  
- Setup time                                          -534  
----------------------------------------------------  ----  
End-of-path required time (ps)                         713  
                                                            
Starting arrival time                                    0  
+ Data path delay                                      341  
----------------------------------------------------  ----  
End-of-path arrival time (ps)                          341  

Data path
pin name                model name    delay    AT  slew  pin cap  pin load  wire load  total load  fanout arcs  length  edge  
----------------------  ------------  -----  ----  ----  -------  --------  ---------  ----------  -----------  ------  ----  
ld                      #_cipher_top            0     0        0        98        106         204           20          RISE  
BW1_BUF4/A              BUFX20            1     1     2       16        98        106         204                   74  RISE  
BW1_BUF4/Y              BUFX20          133   134   184        0       197        119         317           70          RISE  
BW2_INV31658/A          INVX6            13   147   187       12       197        119         317                  185  RISE  
BW2_INV31658/Y          INVX6            69   217    73        0        32          5          37            1          FALL  
BW2_INV31658_1/A        INVX16            0   217    73       32        32          5          37   
                23  FALL  
BW2_INV31658_1/Y        INVX16          116   333   176        0       139        105         244           51          RISE  
text_in_r_reg[77]/E     EDFFX1            7   341   177        3       139        105         244                  114  RISE  

Reference clock path
pin name                model name    delay    AT  slew  pin cap  pin load  wire load  total load  fanout arcs  length  edge  
----------------------  ------------  -----  ----  ----  -------  --------  ---------  ----------  -----------  ------  ----  
clock:clk               #_cipher_top         1000     0                                                      1          RISE  
clk                     #_cipher_top      0  1000     0        0        39         53          92            1          RISE  
clk_S0/A                INVX20            4  1004     8       39        39         53          92                  217  RISE  
clk_S0/Y                INVX20           35  1039    51       
 0        78         78         156            2          FALL  
clk_L0_1/A              INVX20            7  1046    54       39        78         78         156                  308  FALL  
clk_L0_1/Y              INVX20           61  1106    81        0        78         46         124            2          RISE  
clk_L1_3/A              INVX20            2  1108    81       39        78         46         124                  106  RISE  
clk_L1_3/Y              INVX20           47  1155    47        0        78         33         111            2          FALL  
clk_L2_10/A             INVX20            1  1157    47       39        78         33         111                   76  FALL  
clk_L2_10/Y             INVX20           87  1243   133        0       116        105         221           58          RISE  
text_in_r_reg[77]/CK    EDFFX1            3  1246   133        2       116        105         221                   55  RISE