mantle[62]:>report model $m
MSG-10   While running 'report model /work/aes_cipher_top/aes_cipher_top':
CK-5 Collecting data on model aes_cipher_top .....
------------------- M O D E L  S T A T I S T I C S ------------------
Generated for user temp on host vlsi2                          on Thu Mar  1 15:13:01 2007 
Model: /work/aes_cipher_top/aes_cipher_top
 
Cell Statistics                - count -    - area -         - legend -
  Standard cell total:              11970      0.113mm2         (c)
  Hard Macros:                          0      0.000mm2         (m)
  Total cells:                      11970      0.113mm2
 
Dimensions
  Chip Width,Height:  0.400mm x  0.400mm=   0.160mm2         (a)
  Chip Aspect ratio (w/h):        1.00
  Core Width,Height:  0.395mm x  0.391mm=   0.154mm2
  Cell rows & area                    106      0.154mm2   
  Usable cell row area                      0.154mm2         (r)
  Buckets:         97 x  108 =   10476       
 
Utilizations
  Cell row utilization:           73.0%                       ((c)/r)
  Total utilization:              70.4%                       ((c)/a)

Floorplans

  Name : /work/aes_cipher_top/aes_cipher_top/floorplan:aes_cipher_top (primary)
  Outer shape area       :                                   0.160 mm2 (A)
  Sub-floorplans         :           0 Total area     :    0.000 mm2 (f)
  Cell rows              :         106 Available area :    0.154 mm2 (a)
  Attached macros        :           0 Total area     :    0.000 mm2 (m)
  Attached pads          :           0 Total area     :    0.000 mm2 (p)
  Attached standard cells:       11970 Total 
area     :    0.113 mm2 (s)
  Total utilization        :       70 % ( (m + s + p) / (A - f) )
  Cell row utilization     :       72 % ( s / (a - m) )


 
Net Statistics
  Number of signal nets:         12232
  Number of power/clock nets:        2
  Number of cell pins:           47643
  Average nets per standard cell: 1.02
  Average pins per standard cell: 4.00
  Average pins per signal net:    3.91       (maximum = 555)
 
Dangling Pin Statistics
  Dangling cell pins:              270       (0 dangling input pins)
 
Wire statistics
  Layer  | -- Segment Statistics --  |   -- Wire Statistics --
   METAL1:   0.000 ( 0.0%) in     17 |   0.000 ( 0.0%) in      0
   METAL2:   0.109 (23.8%) in  40687 |   0.000 ( 0.0%) in      0
   METAL3:   0.136 (29.6%) in  25434 |   0.000 ( 0.0%) in      0
   METAL4:   0.031 ( 6.8%) in   8272 |   0.000 ( 0.0%) in      0
   METAL5:   0.067 (14.7%) in   4860 |   0.000 ( 0.0%) in      0
   METAL6:   0.077 (16.8%) in   2593 |   0.000 ( 0.0%) in      0
   METAL7:   0.021 ( 4.6%) in    784 |   0.000 ( 0.0%) in      0
   METAL8:   0.017 ( 3.8%) in    337 |   0.000 ( 0.0%) in      0
  Total  :   0.45929 meter in  
82984 |   0.00000 meter in      0 wires
  
  Signal nets:                   0.459      meter in 82984 segments
  
  Estimated signal wire length:  0.490       meter
  
  Prerouted wires (pwr/clk):     0.077meter in 3894 wires (100.0%)
  Prerouted segments (pwr/clk):  0.000meter in 0 segs  (0.0%)
  Average net segment length:       38um    in  6.8 legs

 
Routing statistics
  Total violation count:             0 
 
  -> Please note that the violation checker does not necessarily capture
     all mask errors.
  -> The above statistics report the result of the latest violation check. 
     It is possible that this is not consistent anymore with the current
     state of the design.  When in doubt, re-run the checker using
     'check route spacing_short' or 'check route drc'.
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