Magma ASIC Design Flow - Stage 2
Magma For You in Three Hours (MYTH) - Hour II
MYTH is not a myth
V. Kamakoti and Shankar Balachandran
Reconfigurable Intelligent Systems Engineering Lab

Stage 2: Logic Optimization, Floor Planning and Power Planning

 Logic Optimization

The logical optimization step performs logical synthesis and timing optimization using the fix time command.

Step - 20: "fix time" will Converts a design to Super Cell models, and restructures logic. The man pages list the primitive commands included in this command script. Note the cell count, the worst late slack, and the number of failing endpoints.

 mantle[38]:> fix time \$m \$l

Step - 21: "report timing summary" will generates a timing analysis summary report for the design model.

 mantle[38]:> report timing summary \$m

Step - 22: "report model" Checks the model for basic netlist and floorplan integrity (for example, cell overlap and dangling input pins, timing information, etc.,).

 mantle[45]:> report model \$m

Step - 23: "run bind logical" will bind the unbound cells to the target library.

 mantle[45]:> run bind logical \$m \$l

 Floor Planning

In the floor planning step of the design flow, you define the core size, pin and macro placement, and power routing.

Step - 24: "run bind physical" will binds the design to the physical rule library.

 mantle[45]:> run bind physical \$m \$l

Step - 25: "run prepare lib" will prepare the physical design library.

 mantle[45]:> run prepare lib \$l

Step - 26: To over come the error that displayed at this moment in the mantle, use the following command.

Step - 27: "power plan net" will defines the power and ground nets. Let us assign the power net to VDD using the following command.

 mantle[52]:> force plan net VDD \$m -port VDD -usage power

Step - 28: "power plan net" will defines the power and ground nets. Let us assign the power net to VSS using the following command.

 mantle[53]:> force plan net VSS \$m -port VSS -usage ground

Step - 29: "force plan chip" will bind the design chip size. The total area of the layout can be found by seeing "report model \$m". Specify the area size little greater than the original size given in the report for the purpose of power rails. The chip dimensions can be specified using microns (use letter "u" to represent the microns). The dimension for AES design is given below.

 mantle[53]:> force plan chip \$m -width 400u -height 400u -left_clearance 2.6u -right_clearance 2.6u -top_clearance 2.6u -bottom_clearance 2.6u

Step - 30: "run plan create chip" will create the chip for the specified constraints.

 mantle[53]:> run plan create chip \$m

Step - 31: "run floor plan apply" will apply floor plan to the design and verifies with the design rule checker (DRC).

 mantle[53]:> run floorplan apply \$m

Step - 32: "run plan create pin" will create a pin plan for the chip.

 mantle[53]:> run plan create pin \$m

Step - 33: "run place global" will do the global placement on the chip.

 mantle[53]:> run place global \$m

Step - 34: "export volcano" to Saves the data model information to disk. Save the design so far what we have designed use the following export command with the filename.volcano.

 mantle[53]:> export volcano aes_floorplan.volcano

At this point you can view your design using "Open Layout Editor" in the "viewers" tab of the main menu. It will ask design model name, Specify the design model name in this example as "/work/aes_cipher_top/aes_cipher_top/". The AES design example layout is shown in here.

 Power Planning using the GUI.

You can create the power plan either manually using the GUI or by using a prescripted Tcl file. This section describes using the GUI to manually create the power plan. At this point you can view your design using "Open Layout Editor" in the "viewers" tab of the main menu. It will ask design model name, Specify the design model name in this example as "/work/aes_cipher_top/aes_cipher_top/". The AES design example layout is shown in here.

Now select the go to the "Power" tab in the main menu of the Layout Editor. This is workspace for the power plan. Now follow the following steps:

The GUI provides dialog boxes for creating the power rings and mesh. To begin, you open the layout with the Power plan theme.

1. In the layout window, choose Power > Add Power Rings, It will open the power ring editor as shown in Figure 5.2, and complete the dialog box as follows.

Click the "Add Net" button in the upper left corner. It will open the "Choose multiple nets" dialoge window. Enter information in the dialog box that appears, as described in Figure 5.3. Enter Net information for power net VDD. In the same line enter the information for power net VSS.

Now specify the power ring specification in "Spec" combo box as a "power_ring" as show in the Figure 5.4.

In the Create Power Ring dialog box, select the VDD net and click Add Wire. And enter the following information in the table.

 Wire Layer Width Offset Side Extend VDD/wire0 METAL2 2.000u 2.000u vertical none VDD/wire1 METAL3 2.000u 2.000u horizontal none VSS/wire0 METAL2 2.000u 4.600u vertical none VSS/wire1 METAL3 2.000u 4.600u horizontal none

When you are done, the create power ring editor will look as shown in Figure 5.5. Select the No Via check box. Now Save the spec as a "power_ring" by clicking on the "save specs" button in the right corner of the create power editor. Click on the "Apply" button that is show in the bottom of the create power editor to apply specs. At the bottom of the page, click OK to add the rings.

Now in the layout it will show the power rings as shown in the Figure 5.6.

In the following steps, you add the mesh on three layers. To open the power mesh editor, select the "Power Mesh" tab in the "power" tab of the "Layout" editor as shown in the Figure 5.7.

1. Create vertical stripes as follows:

In the layout window, choose Power > Add Power Mesh, and complete the dialog box as shown in Figure 5.8. It will open the power mesh editor that is shown in the Figure 5.9.

Click the "Add Net" button in the upper left corner. It will open the "Choose multiple nets" dialoge window. Enter information in the dialog box that appears, as described in Figure 5.10 . Enter Net information for power net VDD. In the same line enter the information for power net VSS.

In the Create Power Mesh dialog box, select the VDD net and click Add Wire. And enter the following information in the table.

 Wire Layer Width Offset Extend VDD/wire0 METAL6 10.000u 25.000u both VSS/wire1 METAL6 10.000u 45.000u both

Set the following settings:

 Spec v6 Direction vertical Group Spacing 80u

Keep rest of the settings as a default. In the Spec entry field at the top of the page, enter the name "v6" as shown in Figure 5.11 , and click Save Spec. Click OK to add the stripes, and wait for the stripes to appear in the layout as shown in Figure 5.12 .

On the same line create a vertical strip V4 as follows:

In the layout window, choose Power > Add Power Mesh, and complete the dialog box as shown in Figure 5.13 . It will open the power mesh editor that is shown in the Figure 5.14 .

Click the "Add Net" button in the upper left corner. It will open the "Choose multiple nets" dialoge window. Enter information in the dialog box that appears, as described in Figure 5.15 . Enter Net information for power net VDD. In the same line enter the information for power net VSS.

In the Create Power Mesh dialog box, select the VDD net and click Add Wire. And enter the following information in the table.

 Wire Layer Width Offset Extend VDD/wire0 METAL4 1.000u 10.000u both VSS/wire1 METAL4 1.000u 13.000u both

Set the following settings:

 Spec v4 Direction vertical Group Spacing 20u

Keep rest of the settings as a default. In the Spec entry field at the top of the page, enter the name "v4" as shown in Figure 5.16, and click Save Spec. Click OK to add the stripes, and wait for the stripes to appear in the layout as shown in Figure 5.17.

2. Create Horizontal stripes as follows:

In the layout window, choose Power > Add Power Mesh, and complete the dialog box as shown in Figure 5.18. It will open the power mesh editor that is shown in the Figure 5.19 .

Click the "Add Net" button in the upper left corner. It will open the "Choose multiple nets" dialog window. Enter information in the dialog box that appears, as described in Figure 5.20 . Enter Net information for power net VDD. In the same line enter the information for power net VSS.

In the Create Power Mesh dialog box, select the VDD net and click Add Wire. And enter the following information in the table.

 Wire Layer Width Offset Extend VDD/wire0 METAL5 10.000u 25.000u both VSS/wire1 METAL5 10.000u 45.000u both

Set the following settings:

 Spec h5 Direction horizantal Group Spacing 80u

Keep rest of the settings as a default. In the Spec entry field at the top of the page, enter the name "h5" as shown in Figure 5.21 , and click Save Spec. Click OK to add the stripes, and wait for the stripes to appear in the layout as shown in Figure 5.22.

At the end of Power Mesh design layout is as shown in Figure 5.23 .

Create Power Rails

In the layout window, choose Power > Create Rails, and complete the dialog box as shown in Figure 5.24 . It will open the power rail editor that is shown in the Figure 5.25 .

 Macro clip range 100u Stack via 4

Keep thes rest of the settings as a default setting. At the end of create rail the desin layout will look as shown in Figure 5.25. The power plan of the layout is shown in Figure 5.26 . The Power plan is shown in Figure 5.27 .

 Power Plan Ends Here

Step - 35: "check route drc" will check for routing DRC for power plan.

 mantle[53]:> check route drc \$m -power_only

To See the mantle Report click here. The design layout is shown in Figure 5.28. The elaborated view of the layout is shown in Figure 5.29, Figure 5.30.

Note: If you came across any power related DRC errors in the design then run the following command to fix the problem. (Run the following command in case of DRC errors in power plan).

 mantle[53]:> run route power2 post_route_refine \$m

Step - 36: "check route drc" will do the DRC check for routing.

 mantle[53]:> check route drc \$m