Lectures in this course:35
1 - Introduction (54:03)
2 - Verilog: Part - I (49:00)
3 - Verilog: Part - II (55:50)
4 - Verilog: Part - III (55:27)
5 - Verilog: Part - IV (49:53)
6 - Verilog: Part - V (50:35)
7 - Verilog: Part - VI (56:24)
8 - Synthesis: Part - I (56:19)
9 - Synthesis: Part - II (51:54)
10 - Synthesis: Part - III (51:48)
11 - Synthesis: Part - IV (52:39)
12 - Synthesis: Part - V (48:37)
13 - Synthesis: Part - VI (52:26)
14 - Synthesis: Part - VII (52:46)
15 - Backend Design: Part - I (47:44)
16 - Backend Design: Part - II (56:57)
17 - Backend Design: Part - III (56:36)
18 - Backend Design: Part - IV (52:17)
19 - Backend Design Part - V (56:38)
20 - Backend Design Part - VI (55:13)
21 - Backend Design Part - VII (54:31)
22 - Backend Design Part - VIII (53:24)
23 - Backend Design Part - IX (55:41)
24 - Backend Design Part - X (52:34)
25 - Backend Design Part - XI (56:04)
26 - Backend Design Part - XII (56:49)
27 - Backend Design Part - XIII (52:17)
28 - Backend Design Part - XIV (56:23)
29 - Backend Design Part - XV (57:46)
30 - Testing Part - I (54:38)
31 - Testing Part - II (56:34)
32 - Testing Part - III (52:06)
33 - Testing Part - IV (55:27)
34 - Testing Part - V (53:32)
35 - Testing Part - VI (56:02)

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