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Course Co-ordinated by IIT Bombay
Coordinators
 

 
Prof. D.K. Sharma
IIT Bombay

 
Prof. Sachin Patkar
IIT Bombay

 

 

Download Syllabus in PDF format



Untitled Document
 

Historical Perspective of VLSICMOS VLSI Design for Power and Speed consideration, Logical Efforts: Designing Fast CMOS Circuits; Datapath Design, Interconnect aware   design, Hardware Description Languages for VLSI Design, FSM Controller/Datapath and Processor Design, VLSI Design Automation, and VLSI Design Test and Verification.

 
 

Module

Lecture Topics

1: CMOS VLSI Design for Power and Speed consideration (Prof. A.N.Chandorkar)

 

  1. Historical Perspective and Future Trends in CMOS VLSI Circuit and System Design- Part-I
  2. Historical Perspective and Future Trends in CMOS VLSI Circuit   and System Design - Part II
  3. Logical Effort - A way of Designing Fast CMOS Circuits
  4. Logical Effort - A way of Designing Fast CMOS Circuits -Part II
  5. Logical Effort - A way of Designing Fast CMOS Circuits -Part III
  6. Power Estimation and Control in CMOS VLSI circuits
  7. Power Estimation and Control in CMOS VLSI circuits -Part II
  8. Low Power Design Techniques- Part-I
  9. Low Power Design Techniques -Part II

2:  Datapath Design (Prof. A.N.Chandorkar)

  1. Arithmetic Implementation Strategies for VLSI – Part I
  2. Arithmetic Implementation Strategies for VLSI -Part II
  3. Arithmetic Implementation Strategies for VLSI -Part III
  4. Arithmetic Implementation Strategies for VLSI -Part IV

3: Interconnect aware design (Prof. Dinesh Sharma)

  1. Interconnect aware design: Impact of scaling, buffer insertion and
    Inductive peaking
  2. Interconnect aware design: Low swing and Current mode signaling
  3. Interconnect aware design: Capacitively coupled interconnects

4: Hardware Description Languages for VLSI Design (Prof. Dinesh Sharma)

 

  1. Managing concurrency and time in Hardware Description Languages
  2. Introduction to VHDL
  3. Basic Components in VHDL
  4. Structural Description in VHDL
  5. Behavioral Description in VHDL
  6. Introduction to Verilog

5:  FSM Controller/Datapath and Processor Design (Prof. Sachin Patkar)

 

  1. FSM + datapath (GCD example)
  2. FSM + datapath (continued)
  3. Single Cycle MMIPS
  4. Multicycle MMIPS
  5. Multicycle MMIPS – FSM

6: VLSI Design Automation (Prof. Sachin Patkar)

  1. Brief Overview of Basic VLSI Design Automation Concepts
  2. Netlist and System Partitioning
  3. Timing Analysis in the context of Physical Design Automation
  4. Placement algorithm

7: VLSI Design Test and Verification (Prof. Virendra Singh)

  1. Introduction to VLSI Testing
  2. VLSI Test Basics - I
  3. VLSI Test Basics - II
  4. VLSI Testing: Automatic Test Pattern Generation
  5. VLSI Testing: Design for Test (DFT)
  6. VLSI Testing: Built-In Self-Test (BIST)
  7. VLSI Design Verification: An Introduction
  8. VLSI Design Verification: Equivalence Checking
  9. VLSI Design Verification: Equivalence/Model Checking
  10. VLSI Design Verification: Model Checking

  • Basic course on VLSI Design


  • Module 1 and 2: “Principles of CMOS VLSI Design” by Weste and Eshranghian, Second Edition, Pearson Education, India; “CMOS VLSI Design ” by Neil H. E. Weste, David F. Harris ,Pearson/Addison Wesley ; “Digital Integrated Circuits” , Jan M.Rabaey, Anant Chandrakasan, and Borivoje Nikoli?, Prentice Hall (India); “Logical Efforts: Designing Fast CMOS Circuits”, Ivan Suderland, Bob Sproull and D. Harris, Morgan Kaufmann, India. “Low Power CMOS VLSI Circuit Design”, Kaushik Roy, Wiley- Interscience.
  • Module 3: “Modern VLSI Design”, Wayne Wolf, Third Edition, Pearson Education
  • Module 4: “The designer's guide to VHDL”, Peter J. Ashenden, Second Edition, Morgan and Kaufmann/Harcourt India. “Verilog HDL” by Samir Palnitkar, Low Price Edition, Pearson Education, Asia
  • Module 5: “CMOS VLSI Design” by Neil H. E. Weste, David F. Harris ,Pearson/Addison Wesley,“Computer Organization and Design, Fourth Edition: The Hardware/Software Interface” , David A. Patterson, John L. Hennessy,Morgan Kaufmann, 2008
  • Module 6: “VLSI Physical Design: From Graph Partitioning to Timing Closure”, Kahng and Lienig,Springer, 2011
  • Module 7: “Essential of Electronic Testing for Digital, Memory, and Mixed Signal VLSI Circuits”, M.L. Bushnell and V.D Agrawal, Springer 2005 “VLSI Test Principles and Architectures”, L.W. Wang, C.W. Wu, W. Xioqing, Academic Press, 2006 . “Hardware Design Verification”, William Lam, Prentice Hall, “Logics in Computer Science”, M. Huth and M. Ryan, Cambridge University Press, 2006


  • Technical Papers in following Journals:
    IEEE’s Journal of Solid State Circuits, IEEE Trans. on CAD of ICs, IEEE Trans. on VLSI, IEEE Trans. on Circuits and Systems, Embedded System Letters(IEEE), IEEE Trans. On Computers



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