﻿1 00:01:01,410 --> 00:01:08,410 We have started discussion on designing of a simple CPU and the CPU architecture that 2 00:01:08,440 --> 00:01:15,440 we have considered is like this, having only two registers R1 and R2. In addition to accumulator 3 00:01:16,020 --> 00:01:22,110 and data register, it is having an ALU, program counter, instruction register, instruction 4 00:01:22,110 --> 00:01:29,110 decoder, timing and control unit and a memory address register. For designing the CPU, we 5 00:01:29,520 --> 00:01:36,520 have considered few instructions around which the CPU will be designed and the instructions 6 00:01:37,880 --> 00:01:40,110 that we have said is like this. 7 00:01:40,110 --> 00:01:47,110 It is having an add instruction add R1 then complement and logical instruction and R1, 8 00:01:47,750 --> 00:01:54,750 one jump instruction and few MOV instructions. Then we have seen that the block diagram of 9 00:01:56,960 --> 00:02:03,960 the timing and control unit of this particular CPU will be something like this. 10 00:02:06,520 --> 00:02:10,940 From the instruction register, the instruction opcode will go to the instruction decoder. 11 00:02:10,940 --> 00:02:17,690 Similarly we have a sequence counter to generate different time states of the CPU. The counter 12 00:02:17,690 --> 00:02:23,450 output is again going to a decoder. All the decoder outputs that is sequence counter decoder 13 00:02:23,450 --> 00:02:28,190 output and the instruction decoder output they are going to the timing and control unit 14 00:02:28,190 --> 00:02:35,190 and the timing and control circuit will generate the timing clock in the sequence that is required. 15 00:02:39,360 --> 00:02:44,790 So for that instead of taking the entire instruction set that we are considering, we have tried 16 00:02:44,790 --> 00:02:51,790 to see that how the timing and control circuit can be designed with respects to these three 17 00:02:53,459 --> 00:03:00,459 instructions that is add R1, MOV R1, R2 and MOV accumulator, memory. 18 00:03:03,750 --> 00:03:09,190 So till last class we have considered only the first instruction that is the add instruction 19 00:03:09,190 --> 00:03:15,930 and we have said that for execution of any of the instructions, few operations like opcode 20 00:03:15,930 --> 00:03:22,690 fetch that is common and the opcode fetch and the decoding that takes place during the 21 00:03:22,690 --> 00:03:29,690 time states machine states T0, T1 and T2. So for execution of any instruction, the operation 22 00:03:30,080 --> 00:03:36,710 during T0, T1 and T2 will remain the same. So those are the common micro operations which 23 00:03:36,710 --> 00:03:43,710 are to be there for execution of any of the instructions. After that T3 onwards the operations, 24 00:03:44,450 --> 00:03:51,450 the micro operations are different for instructions. So for add R1 during T3 the operations that 25 00:03:52,030 --> 00:03:58,550 are to be performed is transferring the content of R1 to data register because as per our 26 00:03:58,550 --> 00:04:05,100 architecture, CPU architecture addition directly on R1 is not possible because R1 does not 27 00:04:05,100 --> 00:04:07,240 provide any input to the ALU. 28 00:04:07,240 --> 00:04:13,580 ALU gets input from the data register. So for addition operation add R1, the data from 29 00:04:13,580 --> 00:04:20,580 R1 has to be transferred to the data register after that the content of data register can 30 00:04:21,750 --> 00:04:28,139 be added with the accumulator and after additional operation is complete, the accumulator output 31 00:04:28,139 --> 00:04:33,750 has to be loaded back into the accumulator. So this is the operation that will be performed 32 00:04:33,750 --> 00:04:40,750 while execution of add R1 instruction. We were trying to develop the control logic for 33 00:04:44,970 --> 00:04:47,440 performing these operations. 34 00:04:47,440 --> 00:04:53,150 So the control logic we are developing or something like this. We have said that during 35 00:04:53,150 --> 00:05:00,150 T0, T1 and T2, the operations for all the instructions are common. So during T0 the 36 00:05:01,900 --> 00:05:06,780 operation was content of the program counter has to go to the memory address register. 37 00:05:06,780 --> 00:05:12,509 So output enable of the program counter, it has to be activated during machines state 38 00:05:12,509 --> 00:05:19,509 T0. Then memory address register that has to get the input during T0 and also during 39 00:05:20,690 --> 00:05:27,690 T2, when the operand address part of the instruction that is IR0-11 the lower 12 bits will be transferred 40 00:05:28,690 --> 00:05:34,440 from the instruction register to memory address register. So during T2 again the data has 41 00:05:34,440 --> 00:05:39,630 to be loaded into memory address register, so the load control signal till now gets the 42 00:05:39,630 --> 00:05:46,630 logic of T0 plus T2. Instruction register that instruction code is loaded into instruction 43 00:05:49,250 --> 00:05:52,260 register during T1. 44 00:05:52,260 --> 00:05:57,990 So the instruction register load input has to be active during T1 and the instruction 45 00:05:57,990 --> 00:06:04,250 register output enable also has to be active during machine state T2 because during that 46 00:06:04,250 --> 00:06:10,570 time, the operand address part of the instruction will be loaded into the memory address register. 47 00:06:10,570 --> 00:06:15,990 So you find that load input of the memory address register that is active during T2. 48 00:06:15,990 --> 00:06:22,010 Similarly the output enable of the instruction register that is also enabled during T2. So 49 00:06:22,010 --> 00:06:27,460 because these two are activated simultaneously, the output from the instruction register the 50 00:06:27,460 --> 00:06:31,320 lower 12 bits will be loaded into memory address register. 51 00:06:31,320 --> 00:06:38,320 Then for performing the add operation add R1, we have said that because this is a register 52 00:06:39,510 --> 00:06:46,330 reference instructions so the decoder output, instruction decoder output D7 will be high. 53 00:06:46,330 --> 00:06:53,330 So if D7 is high then during time interval T3, what you have to do is we have to transfer 54 00:06:53,330 --> 00:07:00,330 the data from the register R1 to the data register. So that is why if D7 is high, referring 55 00:07:04,740 --> 00:07:11,680 that it is a register reference instruction and I0 that is the least significant bit of 56 00:07:11,680 --> 00:07:16,669 the instruction register, we have said that for register reference instructions the operand 57 00:07:16,669 --> 00:07:23,240 fields identify that what register reference instruction it is. We have said that if I0 58 00:07:23,240 --> 00:07:30,240 is high then it is add R1 operation. So during T3, if D7 is high and I0 is high then data 59 00:07:33,610 --> 00:07:40,610 will be transferred from register R1 to data register. So the output enable of R1 must 60 00:07:41,180 --> 00:07:47,970 be active, if this condition is true. Similarly the load input of the data register also must 61 00:07:47,970 --> 00:07:54,870 be active if the same condition is true. So the same logic goes to the load input of the 62 00:07:54,870 --> 00:08:01,729 data register. It also goes to the output enable of the register R1. 63 00:08:01,729 --> 00:08:08,710 Now in addition to this for performing the addition operation, you find that during time 64 00:08:08,710 --> 00:08:15,710 interval T4, accumulator will get the output of the ALU and because this is add operation, 65 00:08:18,520 --> 00:08:25,479 so ALU has to perform the addition operation. Among the arithmetical logical operation, 66 00:08:25,479 --> 00:08:32,479 we have assumed that we have only two operations. One is ADD, other one is AND. The other operation 67 00:08:35,630 --> 00:08:39,550 that has to be performed on the accumulator is the complementation of the accumulator 68 00:08:39,550 --> 00:08:44,649 for which we will assume that ALU will not be needed, q bar output of the accumulator 69 00:08:44,649 --> 00:08:50,500 can be fed back to the d input of the accumulator. So by using a single clock pulse, within the 70 00:08:50,500 --> 00:08:55,880 same machine state, the accumulator complementation can be performed. 71 00:08:55,880 --> 00:09:01,050 So ALU will be involved for performing only two operations, one is ADD operation and the 72 00:09:01,050 --> 00:09:08,019 another one is AND operation. So in the simplest case, we will assume that ALU will also have 73 00:09:08,019 --> 00:09:14,790 two mode select inputs. One corresponding to ADD, the other one corresponding to AND. 74 00:09:14,790 --> 00:09:20,509 So whenever the ALU has to perform the add operation, the add mode select input of the 75 00:09:20,509 --> 00:09:26,269 ALU will be active. When it performs AND operation, the AND mode select input of the ALU will 76 00:09:26,269 --> 00:09:33,269 be active. So accordingly, for performing this ADD operation coming to the control signal 77 00:09:33,999 --> 00:09:40,999 needed for the accumulator, what we need is accumulator has to have a load input. So for 78 00:09:44,939 --> 00:09:51,939 the accumulator will have a load input because the result after addition will be loaded into 79 00:09:53,529 --> 00:10:00,529 the accumulator and that is to be performed during the time state T4. So this load input 80 00:10:01,269 --> 00:10:08,269 of the accumulator will be active during T4 when D7 is active because this is register 81 00:10:14,759 --> 00:10:21,759 reference operation and I0 is high. So that is an add operation. ALU load input may be 82 00:10:24,160 --> 00:10:31,160 active in other cases as well. So I will put it as OR logic. Similarly for ALU I have to 83 00:10:33,550 --> 00:10:40,550 have the mode select inputs. I assume that for add operation I have the mode selection 84 00:10:45,929 --> 00:10:52,929 input called add. This also has to be active during T4 if D7 is high and I0 is high. So 85 00:11:07,660 --> 00:11:14,239 with the help of these control signals I can perform the add operation. 86 00:11:14,239 --> 00:11:21,239 Now there is one more operation that is quite obvious that is at the end of each of these 87 00:11:23,110 --> 00:11:30,110 time periods machine states, the sequence counter has to be incremented by one. So for 88 00:11:30,629 --> 00:11:37,629 that we have an increment input of the sequence counter. So the other unit that is involved 89 00:11:37,889 --> 00:11:44,889 in the timing and control is sequence counter. sequence counter is having an increment output. 90 00:11:56,350 --> 00:12:02,879 When this increment output will be active, it has to be active during T0 because after 91 00:12:02,879 --> 00:12:09,879 T0 the machine state has to go to T1. It also has to be active during T1 because after T2, 92 00:12:12,699 --> 00:12:19,699 the machine will go to T2. It also has to be active during T2 because after T2, the 93 00:12:19,980 --> 00:12:26,980 machine has to go to T3. It also has to be active during T3 because after T3 it will 94 00:12:32,249 --> 00:12:35,149 go to T4. 95 00:12:35,149 --> 00:12:42,149 Now let me do one thing. Let me not put T3 right now. We will come to that later, for 96 00:12:44,699 --> 00:12:51,699 the time being let it be here. The sequence counter also has a control input called clear. 97 00:12:56,720 --> 00:13:01,279 So after completion of the execution of any instruction, the machine has to go back to 98 00:13:01,279 --> 00:13:07,769 time state T0 when it will be ready for fetching the next instruction. So for that the clear 99 00:13:07,769 --> 00:13:14,769 input has to be active. Now with respect to this add operation, you find that at the end 100 00:13:16,019 --> 00:13:23,019 of machine state T4, we have to bring back the machine state to T0. So this clear input 101 00:13:26,589 --> 00:13:33,589 has to be active, if during T4 if D7 is high and I0 is also high. It will be cleared in 102 00:13:41,439 --> 00:13:48,139 other situations also, so we will put this as OR logic. So with the help of this, whatever 103 00:13:48,139 --> 00:13:52,730 is the control signal required for performing add operation that control logic has been 104 00:13:52,730 --> 00:13:59,730 done. After doing this let us take the next instruction that is MOV R1, R2. When R1, content 105 00:14:08,489 --> 00:14:14,679 of R2 has to be transferred to register R1 and you have seen that this operation can 106 00:14:14,679 --> 00:14:21,679 be performed in only one machine state that is during time state T3 and the control signals 107 00:14:23,199 --> 00:14:30,199 that is required for performing this operation is output enable of R2 and load input of R1. 108 00:14:32,540 --> 00:14:39,540 So we take register R2. We take the output enable of register R2 and for MOV R1, R2 what 109 00:14:53,839 --> 00:15:00,839 is the code? Let us see. 110 00:15:08,619 --> 00:15:14,839 This is what we have assumed for MOV R1, R2. That means it is also a register reference 111 00:15:14,839 --> 00:15:21,839 instruction. All the operations had been performed within the register and the I3 bit of the 112 00:15:22,410 --> 00:15:27,489 instruction register has to be high. That means for this instruction, we have to have 113 00:15:27,489 --> 00:15:34,489 the opcode as 1 1 1 that means D7 output will be high and the bit I3 will also be high. 114 00:15:37,879 --> 00:15:44,879 So for output enable for register R2, we must have this condition to be true. During T3, 115 00:15:48,809 --> 00:15:55,809 D7 is high and I3 is also high. During the same interval, the load input of register 116 00:16:07,910 --> 00:16:14,319 R1 also has to be active because the data has to go from register R2 to register R1. 117 00:16:14,319 --> 00:16:21,319 So for that what we need is the load input of register R1. R1 have we considered till 118 00:16:24,339 --> 00:16:31,339 now? No. So for register R1, we have to consider the load input. So load input also be has 119 00:16:35,730 --> 00:16:42,730 to be active, if this condition is true; load of register R1. So we have to have T3 D7 and 120 00:16:48,269 --> 00:16:52,899 I3. 121 00:16:52,899 --> 00:16:59,059 So if we set this conditions true then the data will be transferred from register R2 122 00:16:59,059 --> 00:17:06,059 to register R1. Now in addition to this, what are the other things that we have to consider? 123 00:17:06,520 --> 00:17:12,620 For the sequence counter, the clear input also has to be active. If this condition is 124 00:17:12,620 --> 00:17:19,549 true because after T3, the sequence counter has to generate machine state T0. So for the 125 00:17:19,549 --> 00:17:26,549 clear input, we must have T3 D7 and I3. So clear becomes T4 D7 I0 or T3 D7 I3. Now here 126 00:17:40,190 --> 00:17:45,880 you find that for sequence counter, I put a question mark that whether we should put 127 00:17:45,880 --> 00:17:52,600 T3 also here or not? In this case after T3 the sequence counter has to be cleared, it 128 00:17:52,600 --> 00:17:59,600 is not to be incremented to T4. So I have to set what will be the increment logic for 129 00:18:03,770 --> 00:18:10,770 the sequence counter. So the sequence counter will be incremented after T3 for an add operation. 130 00:18:13,210 --> 00:18:20,210 So for that the was the logic? T3, D7 and I0, so I will put it as T3 D7 and I0. Again 131 00:18:34,270 --> 00:18:41,270 the situation may arise in other cases. So I will put all of them are OR logic. So with 132 00:18:44,490 --> 00:18:51,420 this I can complete the execution of MOV R1, R2 statement. 133 00:18:51,420 --> 00:18:58,420 Coming to the next statement that we are considering, that is MOV accumulator, M that is reading 134 00:19:03,580 --> 00:19:10,580 the data from a location in memory and loading that data into accumulator. So for that we 135 00:19:10,980 --> 00:19:16,520 need memory address from which location in the memory that data has to be read and you 136 00:19:16,520 --> 00:19:23,520 see that during time interval T2, we have already put the operand address into memory 137 00:19:24,600 --> 00:19:29,610 address register and this operand address has come from the instruction register. So 138 00:19:29,610 --> 00:19:33,480 whatever location that has to be read and the data has to be put into the accumulator, 139 00:19:33,480 --> 00:19:40,120 the address of that location is already available in the memory address register. So we don’t 140 00:19:40,120 --> 00:19:45,210 have to perform any extra operation for that purpose. 141 00:19:45,210 --> 00:19:51,060 So what we have to do is we have to simply generate the memory read control signal and 142 00:19:51,060 --> 00:19:58,060 we have to generate the accumulator load control signal during time interval T3, if it is a 143 00:19:59,070 --> 00:20:05,410 memory read operation. Whether it is memory read operation or not that will load from 144 00:20:05,410 --> 00:20:12,030 the decoder output, from the instruction decoder output. So for this our instruction decoder 145 00:20:12,030 --> 00:20:19,030 output was 0 0 1 which is the instruction for MOV accumulator, memory. So our logic 146 00:20:25,280 --> 00:20:32,280 will be that during machine state T3, if the decoder output one is active then what operations 147 00:20:34,320 --> 00:20:41,040 we have to perform? We have to generate the memory read control signal, we have to generate 148 00:20:41,040 --> 00:20:48,040 or activate the load control signal of the accumulator. So I will consider this. I will 149 00:20:50,030 --> 00:20:57,030 put, it is a memory M. For m I need the control signal memory read, I will put it as a MR. 150 00:21:01,600 --> 00:21:08,600 So MR will be active, if during time state T3 if D1 is high. 151 00:21:17,860 --> 00:21:23,050 Similarly for the accumulator, the load input will be active, the load control signal will 152 00:21:23,050 --> 00:21:30,050 be active during T3 if D1 is high. I can also have other conditions so let us put this as 153 00:21:36,200 --> 00:21:43,200 OR logic. So this completes our memory read operation. Now again in memory read operation, 154 00:21:47,070 --> 00:21:54,070 after time state T3 the sequence counter has to be cleared. So for clearing sequence counter, 155 00:21:54,860 --> 00:22:01,860 here I have to have the same logic that is T3 D1. I can have other condition as well, 156 00:22:16,170 --> 00:22:23,170 so I put this as OR logic. So with this I can transfer the content of the addressed 157 00:22:24,330 --> 00:22:29,540 memory location to accumulator and after that transfer is complete, the sequence counter 158 00:22:29,540 --> 00:22:35,010 will be cleared to zero, generating the next machine state as T0, when it is ready for 159 00:22:35,010 --> 00:22:42,010 fetching the next instruction. Now this memory read also has to be active 160 00:22:43,120 --> 00:22:50,120 for instruction fetch and that has to be done when we have put the instruction opcode into 161 00:22:54,010 --> 00:23:01,010 the instruction register during time state T1. So irrespective of the instruction during 162 00:23:01,530 --> 00:23:08,530 time state T1, we have to generate the memory read control signal because this is also reading 163 00:23:09,490 --> 00:23:15,600 a location of the memory and loading the content into the instruction register. So memory read 164 00:23:15,600 --> 00:23:22,600 also has to be active during time state T1 and there may be other conditions as well. 165 00:23:25,800 --> 00:23:31,460 So you find that following this kind of logic after analyzing each and every instruction 166 00:23:31,460 --> 00:23:36,900 that what are the micro operations that are involved in the instruction and in which sequence 167 00:23:36,900 --> 00:23:43,900 the micro operations are to be performed, I can generate the control signals accordingly. 168 00:23:46,860 --> 00:23:53,860 So once I get the logic for each of this control signals, I simply put this logic design a 169 00:23:54,530 --> 00:24:01,530 combinational circuit to replace this block with the combinational logic circuit and that 170 00:24:04,120 --> 00:24:11,120 combinational logic circuit comes from this logical expressions. So with that I can complete 171 00:24:13,610 --> 00:24:20,610 this timing and control circuit design. Sequence counter increment has to be done, why? After 172 00:24:28,080 --> 00:24:35,080 T3 D1, you are resetting the sequence counter so that comes in clear input. You cannot put 173 00:24:40,100 --> 00:24:47,100 both clear and increment active simultaneously because this transfer of data from the memory 174 00:24:48,450 --> 00:24:54,780 to the accumulator is complete during T3. So following T3 the machine should be ready 175 00:24:54,780 --> 00:24:59,060 to get the next instruction from the memory. So for that I have to generate the machine 176 00:24:59,060 --> 00:25:06,060 states T0. So that is what has been done by this clear. Is that okay? 177 00:25:08,140 --> 00:25:15,140 Now we will see that in this instruction register, one bit we had left in our last class. Instead 178 00:25:18,280 --> 00:25:23,940 of having opcode as four bit opcode, we have said that our opcodes are 3 bit up codes, 179 00:25:23,940 --> 00:25:30,940 one bit I had left. So what I can do is these bit I can use to indicate whether the memory 180 00:25:33,440 --> 00:25:40,440 reference that is being performed is direct memory access or indirect memory access. 181 00:25:41,140 --> 00:25:47,030 Now what is meant by direct memory access? In case of direct memory access, we have said 182 00:25:47,030 --> 00:25:54,030 that whatever is there as the operand address, the bits 0 to 11 in the instruction register, 183 00:26:08,990 --> 00:26:14,240 this gives you the operand address and for direct memory access we have said that this 184 00:26:14,240 --> 00:26:21,240 operand address directly specifies the location in the memory that contains the operand. So 185 00:26:25,900 --> 00:26:32,900 this points to a location in the memory that contains the data and for this, the most significant 186 00:26:42,730 --> 00:26:49,730 bit in the instruction register will have a value zero. Now for indirect address, what 187 00:26:52,280 --> 00:26:59,280 we will assume is for any memory reference operation, these bits from 0 to 11 which otherwise 188 00:27:04,520 --> 00:27:11,520 gives you the address of the operand in memory, now this is pointing to a memory location 189 00:27:15,830 --> 00:27:22,830 something like this. This is pointing to a memory location, this memory location gives 190 00:27:27,670 --> 00:27:34,670 you the address of the data. This is what contains the data. 191 00:27:44,140 --> 00:27:49,870 So in case of direct address, what we have said is for a memory reference instruction, 192 00:27:49,870 --> 00:27:56,870 we have to have three bit opcode that is bit number 12, 13 and 14. This 3 bit opcode and 193 00:28:03,420 --> 00:28:10,420 the last bit indicates whether it is direct addressing or it is indirect addressing. So 194 00:28:11,030 --> 00:28:17,770 if the most significant bit is 0, we say that it is a direct addressing mode. In case of 195 00:28:17,770 --> 00:28:24,770 direct addressing mode, whatever you have in the bit numbers 0 to 11 that is this lower 196 00:28:25,500 --> 00:28:31,260 12 bits of the instruction that gives you the address of the operand. That means this 197 00:28:31,260 --> 00:28:37,059 is pointing to a particular memory location and content of that memory location is the 198 00:28:37,059 --> 00:28:39,360 data. 199 00:28:39,360 --> 00:28:46,360 That is what we have done for this example when we have moved, executed the instruction 200 00:28:47,380 --> 00:28:54,380 MOV accumulator, memory here. So in this we have assumed that whatever is the content 201 00:28:58,460 --> 00:29:04,750 of those lower 12 bits, that is the address of the data and that is why we have during 202 00:29:04,750 --> 00:29:11,340 T3 we have transferred the content of memory pointed to the memory address register to 203 00:29:11,340 --> 00:29:18,340 the accumulator because this is the data. Here our assumption is the most significant 204 00:29:19,510 --> 00:29:26,510 bit is 0. So the control logic that we have performed, in the control logic we have to 205 00:29:27,440 --> 00:29:34,440 put one more component that is the MSB of the instruction register has to be 0. So instruction 206 00:29:35,930 --> 00:29:42,930 register I15 complement has to come in to that. 207 00:29:43,309 --> 00:29:50,309 Now in case of indirect addressing again this bit numbers 12, 13 and 14, they give you the 208 00:29:54,370 --> 00:30:01,370 opcode of the instruction. Bit number 15 is one. So if bit number 15 is one and this is 209 00:30:06,950 --> 00:30:13,950 a memory reference instruction then the addressing mode that is being used is an indirect addressing, 210 00:30:14,070 --> 00:30:21,070 not a direct addressing. So for indirect addressing whatever you have in this bits that is bit 211 00:30:22,200 --> 00:30:27,510 number 0 to 11, they point to a particular memory location. Now this memory location 212 00:30:27,510 --> 00:30:34,510 is not a data but this is a pointer 213 00:30:40,090 --> 00:30:46,690 that means it is another address. So whatever the content of this memory location, this 214 00:30:46,690 --> 00:30:53,690 is the address of a memory location that contains the data. So what should our control logic 215 00:30:55,240 --> 00:30:57,430 do now? 216 00:30:57,430 --> 00:31:01,790 Control logic has to find out that if this is the memory reference instruction then it 217 00:31:01,790 --> 00:31:08,430 has to check whether this most significant bit is 0 or not. If the most significant bit 218 00:31:08,430 --> 00:31:15,430 is 0 then whatever control logic we have developed till now that is valid. If this is 1 then 219 00:31:17,700 --> 00:31:24,140 what we have developed is no more valid because we have to take care of this indirection. 220 00:31:24,140 --> 00:31:31,140 If this bit is 1, MSB is 1 and it’s a memory reference instruction then I have to get the 221 00:31:31,970 --> 00:31:38,970 data from this location and address of this comes from this location. So during time interval 222 00:31:40,430 --> 00:31:47,430 T3, during the machine state T3 which otherwise in case of machine state T3, what we have 223 00:31:48,980 --> 00:31:54,080 done is we have transferred the content of the memory addressed by the memory address 224 00:31:54,080 --> 00:32:01,080 register to the accumulator. If this bit is one then what we have to do is we have to 225 00:32:02,110 --> 00:32:07,650 read the same content but this cannot be put into the accumulator because this is not the 226 00:32:07,650 --> 00:32:14,650 data. The content of this we have to put to the memory address register. After putting 227 00:32:15,290 --> 00:32:21,450 this to memory address register, we have to perform one more memory read operation and 228 00:32:21,450 --> 00:32:28,450 for this next memory read operation, whatever you get from the memory that can be put into 229 00:32:29,130 --> 00:32:30,460 the accumulator. 230 00:32:30,460 --> 00:32:37,460 So for this indirect memory transfer, let me put it as MOVI. The operands remains the 231 00:32:52,220 --> 00:32:59,220 same accumulator, M. So what is the additional operation that we have to perform? During 232 00:33:01,179 --> 00:33:08,179 machine state T3, previously we have read the memory and put the data into the accumulator. 233 00:33:10,210 --> 00:33:17,210 Now what we have to do is again you read the memory, address coming from the memory address 234 00:33:19,710 --> 00:33:26,710 register instead of putting this into accumulator, we have to put this into memory address register 235 00:33:33,190 --> 00:33:40,190 itself. So I assume that I have that corresponding bit mapping. So during T3, this is the operation 236 00:33:47,640 --> 00:33:54,640 that have to perform. During T4, I have to perform another memory read operation and 237 00:34:00,130 --> 00:34:07,130 now the data will come to the accumulator. It will not go to the memory address register 238 00:34:12,780 --> 00:34:19,780 any more. What is the content of memory address register now? Memory address register, that 239 00:34:20,929 --> 00:34:27,929 is the pointer that is the address that has been set during T3. So for this our control 240 00:34:28,929 --> 00:34:35,929 logic has to be suitably modified. 241 00:34:36,450 --> 00:34:43,450 So in earlier case for memory read, we have assumed that during T3 if D1 is high then 242 00:34:44,889 --> 00:34:49,639 we to perform, we have to enable the memory read control signal. Memory read control signal 243 00:34:49,639 --> 00:34:56,159 will, in any case be activated during T1 because that is an opcode fetch operation. So it is 244 00:34:56,159 --> 00:35:02,890 respective of the instruction that we are going to execute. So now again similarly for 245 00:35:02,890 --> 00:35:09,890 memory read, for the memory how do you activate the memory read control signal? Now memory 246 00:35:15,829 --> 00:35:22,829 read control signal will be during T1, we have already activated this memory read plus 247 00:35:28,519 --> 00:35:35,519 during T3 if D1 is high then we have to perform memory read. 248 00:35:40,140 --> 00:35:47,140 Now we find that during T3 whether it is direct or indirect, in both the cases we have to 249 00:35:47,220 --> 00:35:54,220 read the content of the memory, only the destination will be different. So I simply put as T3 D1. 250 00:35:55,480 --> 00:36:02,200 I don’t check what is the content of the most significant bit in the instruction register. 251 00:36:02,200 --> 00:36:08,829 I have to perform an additional memory read operation during T4, if the most significant 252 00:36:08,829 --> 00:36:15,829 bit of the instruction register is one. So I will put it as T4 and if the opcode is D1, 253 00:36:19,599 --> 00:36:26,599 not only that if I15 the most significant bit of the instruction register is one then 254 00:36:27,099 --> 00:36:31,769 also I have to perform memory read operation. So this is the additional memory read operation 255 00:36:31,769 --> 00:36:33,989 that is required because of introduction. 256 00:36:33,989 --> 00:36:40,989 I may have other logics as well, so put this as OR logic. For memory address register, 257 00:36:48,769 --> 00:36:55,769 I have to modify the control logic. The earlier control logic was this. During T0 and T2, 258 00:37:00,670 --> 00:37:07,670 so they will remain as it is. So for memory address register the load input, the earlier 259 00:37:12,119 --> 00:37:19,119 conditions remains valid during T0 and also during T2. We have to activate the load input 260 00:37:19,920 --> 00:37:26,920 of the memory address register. Now additional thing comes here. So during T3 I again have 261 00:37:28,529 --> 00:37:35,410 to activate the load input of the memory address register if it is an indirect memory address 262 00:37:35,410 --> 00:37:42,410 operation. So my condition will be during T3, if D1 is high and I15 is high. Again I 263 00:37:50,799 --> 00:37:57,369 put this as a OR logic because there may be other conditions as well during which this 264 00:37:57,369 --> 00:38:00,039 memory address register has to be active. 265 00:38:00,039 --> 00:38:07,039 Coming back to accumulator, for accumulator the load input earlier was during T4 if D7 266 00:38:12,190 --> 00:38:19,190 is high and I0 is high. Now this is the one that will be modified now. So these conditions 267 00:38:21,019 --> 00:38:26,430 remains as it is because it’s a register reference instruction and the operation was 268 00:38:26,430 --> 00:38:33,430 moving the data from R2 to R1. Sorry this was the operation for adding the content of 269 00:38:36,529 --> 00:38:41,079 R1 with accumulator and loading the data back into accumulator. So that will remain as it 270 00:38:41,079 --> 00:38:48,079 is. So for accumulator control, the load input will be modified as, the first condition we 271 00:38:53,710 --> 00:39:00,710 have to retain that is T4 D7 and I0. This will remain as it is. 272 00:39:05,890 --> 00:39:12,890 The second condition that we had put is T3 D1. Now T3 D1 will be replaced by T3 D1 I15 273 00:39:17,069 --> 00:39:22,230 complement because here the load input will be active only if it is an direct memory read 274 00:39:22,230 --> 00:39:27,660 operation. If it is indirect memory read operation, the data will not come to accumulator. So 275 00:39:27,660 --> 00:39:34,660 I will put it as T three D one and I fifteen complement. What is the additional condition? 276 00:39:46,420 --> 00:39:53,420 That is during T4, the data will be loaded into accumulator if it is D1 and I15 is high. 277 00:40:04,680 --> 00:40:09,970 I can have additional conditions, situations when the load input of the accumulator also 278 00:40:09,970 --> 00:40:16,970 has to be active. So you put all of them as OR logic. So this is for getting a data from 279 00:40:17,210 --> 00:40:24,210 a memory location, loading the data into accumulator that is the memory read operation. 280 00:40:24,369 --> 00:40:29,029 Similarly for a memory write operation, when the transferring the data from the accumulator 281 00:40:29,029 --> 00:40:36,029 to a particular memory location I can also have direct memory write operation. I can 282 00:40:36,599 --> 00:40:43,369 also have indirect memory write operation. In such case the control signals that will 283 00:40:43,369 --> 00:40:49,799 be generated is not memory read, I have to have another control signal which is memory 284 00:40:49,799 --> 00:40:56,799 write. So memory write control signal also has to be activated accordingly. Similarly 285 00:41:00,420 --> 00:41:04,680 this accumulator, whenever you transfer the data it’s a memory write operation, you 286 00:41:04,680 --> 00:41:10,289 have to transfer the data from the accumulator to a location in the memory. So we have to 287 00:41:10,289 --> 00:41:17,289 accurate the output enable of the accumulators accordingly. So this is how by analyzing the 288 00:41:19,900 --> 00:41:26,900 micro operations that will be performed while execution of every instruction. To that analysis 289 00:41:28,150 --> 00:41:34,160 I have to find out that what will be the logic for each and every control signal and I have 290 00:41:34,160 --> 00:41:39,400 to design the circuit for generating these logics and that has to be replaced in the 291 00:41:39,400 --> 00:41:44,069 timing and control circuit block. 292 00:41:44,069 --> 00:41:49,779 Now here you find that though the circuit is a combinational circuit but because of 293 00:41:49,779 --> 00:41:55,999 the sequence counter output is also going to the timing and control circuit input, the 294 00:41:55,999 --> 00:42:01,130 sequences in which the control signals will be generated that is defined, because in the 295 00:42:01,130 --> 00:42:07,099 timing and control circuit block we have these inputs either T1, T2, T3 three. So these are 296 00:42:07,099 --> 00:42:14,049 the inputs which are going to that particular block. So these input guarantee that these 297 00:42:14,049 --> 00:42:20,569 control signals will be generated during a particular machine state only. This control 298 00:42:20,569 --> 00:42:26,119 signals will not be generated arbitrarily. 299 00:42:26,119 --> 00:42:32,400 So I can design the timing and control circuit for a CPU, given the instructions and having 300 00:42:32,400 --> 00:42:39,400 the knowledge of what the instructions are supposed to do. So far we have considered 301 00:42:43,069 --> 00:42:50,069 for the internal data path that all the components are capable of loading the data from the internal 302 00:42:52,829 --> 00:42:59,539 data path. They are also capable of sending the data to internal data path from there 303 00:42:59,539 --> 00:43:06,539 they can go the destination. For that purpose, for each of the components we have an output 304 00:43:07,229 --> 00:43:14,229 enable. So our restriction is the output enable of only one component can be active at a time. 305 00:43:16,609 --> 00:43:21,279 I cannot activate the output enable of more than one component simultaneously because 306 00:43:21,279 --> 00:43:28,279 in that case there will be data clash on the parser which is called bus contention. So 307 00:43:29,509 --> 00:43:35,660 this can be guaranteed in one of the two ways. I can assume that the outputs of each and 308 00:43:35,660 --> 00:43:42,660 every component is tri stated output. So only when you give the output enable component, 309 00:43:43,859 --> 00:43:50,859 only when you activate the output enable control signal then only the data will move from that 310 00:43:51,499 --> 00:43:58,450 particular selected component to the data bus. When the output enable control signal 311 00:43:58,450 --> 00:44:05,450 is low in that case, the output of that particular component will go the tri-state, the third 312 00:44:05,509 --> 00:44:11,049 state that means high impedance state and the data from that component will not reach 313 00:44:11,049 --> 00:44:17,249 the data bus. So that way we can avoid the parse contention. 314 00:44:17,249 --> 00:44:24,249 The second approach is let there be number of components. The outputs of all these components 315 00:44:24,999 --> 00:44:31,999 goes to a multiplexer and it is the output of the multiplexer that acts as a parse. So 316 00:44:36,890 --> 00:44:43,890 now in this case I don’t need tri stated output device, I can have multiplexer. So 317 00:44:46,150 --> 00:44:53,150 this output enable signal now will be replaced by multiplexes select channel signal. So assuming 318 00:44:55,999 --> 00:45:02,999 if the accumulator is connected to multiplexer input to 0, so whenever the accumulator output 319 00:45:05,700 --> 00:45:11,549 is to be activated, instead of activating the output enable of the multiplexer I will 320 00:45:11,549 --> 00:45:18,440 properly select the select inputs instead of activating the output enable of the accumulator, 321 00:45:18,440 --> 00:45:24,210 I will properly select the select inputs of the multiplexer. So that only the accumulator 322 00:45:24,210 --> 00:45:31,210 output goes to the internal data path. So I can have one of the two ways either we can 323 00:45:33,269 --> 00:45:40,269 use a multiplexer or we can have tri stated outputs for every individual component in 324 00:45:40,299 --> 00:45:47,299 a CPU. So I hope with this discussion now you know that given any CPU and the instruction 325 00:45:52,339 --> 00:45:59,339 set of the CPU, you can design that particular CPU. So with this our low level design is 326 00:46:03,229 --> 00:46:10,229 complete. Next class onwards everything will be in block diagrams. 327 00:46:15,769 --> 00:46:22,769 Till last class the control circuit unit that we have discussed that is called harder control 328 00:46:27,309 --> 00:46:34,309 unit because all the control signals are generated by harder circuit. Now there is another way 329 00:46:34,630 --> 00:46:40,839 of generating the control signals and that is called a micro programmed control unit. 330 00:46:40,839 --> 00:46:46,299 So in case of micro programmed control unit, the control signals instead of being generated 331 00:46:46,299 --> 00:46:53,059 by a hardware circuit it is generated through software and because these control signals 332 00:46:53,059 --> 00:47:00,059 are generated through software this is more flexible. So now let us see how you can generate 333 00:47:00,599 --> 00:47:07,599 the control signals through software. So you have said during our previous discussion that 334 00:47:10,720 --> 00:47:17,289 once you design the hardware resources within the CPU, for every hardware resource you can 335 00:47:17,289 --> 00:47:21,739 determine that what are the control signals that will be required. 336 00:47:21,739 --> 00:47:26,880 So you know our hardware control unit when we have discussed, we have said that during 337 00:47:26,880 --> 00:47:33,880 time state T0 the operation that was preformed was the memory address register gets the content 338 00:47:39,559 --> 00:47:46,559 of the program counter. Then during time interval T1 or machine set T1, what we have done is 339 00:47:52,400 --> 00:47:59,400 instruction register gets the value from memory whose address is in the memory address register 340 00:48:10,569 --> 00:48:17,569 and at the same time, the program counter is incremented by one and during T2 the content of the instruction 341 00:48:28,969 --> 00:48:35,969 register is decoded. So what we do is we decode the instruction register content. 342 00:48:45,380 --> 00:48:52,380 So these of the operations that were done during the machine states T0 to T2 and we 343 00:48:53,109 --> 00:48:59,329 have also said that simultaneously what we have done is we have loaded memory address 344 00:48:59,329 --> 00:49:06,329 register with the lower 12 bits of the instruction register that is supposed to hold the operand 345 00:49:11,650 --> 00:49:18,650 address in memory, if it is memory reference instruction. So if I consider only these three 346 00:49:19,839 --> 00:49:26,839 machine states, you find that the controls that are invoked is for memory address register 347 00:49:26,880 --> 00:49:32,880 we have to have the load control input of the memory address register, output enable 348 00:49:32,880 --> 00:49:39,170 of the program counter, load instruction register, read memory, increment program counter, load 349 00:49:39,170 --> 00:49:46,170 memory address register again, these are identical then output of enable of the instruction register. 350 00:49:46,630 --> 00:49:53,630 So let us associate these control signals with some bits in the control memory. 351 00:49:57,420 --> 00:50:04,420 So let me say that load memory address register that is associated with number C0 that is the zeroth bit in the control memory. 352 00:50:17,109 --> 00:50:24,109 Output enable of the program control that is associated with bit number one in the control 353 00:50:29,769 --> 00:50:36,769 memory or C1, then load instruction register is associated with bit number C2 in the control 354 00:50:42,920 --> 00:50:49,920 memory. Then rate control single for memory is associated with C3 in the control memory. 355 00:50:57,039 --> 00:51:04,039 Then we have program counter increment that is associated with bit number C4 in the control memory. Then load memory address register 356 00:51:12,440 --> 00:51:19,440 is already considered then what we need is output enable of instruction register is associated 357 00:51:24,140 --> 00:51:31,140 with bit number C5 in the control memory. The first operation that is to be performed 358 00:51:33,819 --> 00:51:40,819 is an opcode fetch. So if I ensure that whenever the machine is powered on or whenever the 359 00:51:41,749 --> 00:51:48,420 machine is reset, the control memory address register will also be reset to zero. 360 00:51:48,420 --> 00:51:53,589 So that ensures that just after switching on the machine or just after resetting the 361 00:51:53,589 --> 00:51:59,989 machine, the micro programmed control unit will start generating control signals from 362 00:51:59,989 --> 00:52:03,739 the zeroth location in the control memory. That means the first control signals it will 363 00:52:03,739 --> 00:52:10,739 generate are C0 control signals associated with C0 and C1 which are nothing but load 364 00:52:11,430 --> 00:52:18,009 memory address register and output enable of the program counter. From the program counter 365 00:52:18,009 --> 00:52:21,960 the address goes to memory address register. 366 00:52:21,960 --> 00:52:27,069 Now in addition to this we also have said that every location in the control memory 367 00:52:27,069 --> 00:52:32,719 will have to more fields. One is the next address field or from the next control signals 368 00:52:32,719 --> 00:52:39,719 are to be read and it also have a one bit field which is the modes, the address select 369 00:52:42,170 --> 00:52:49,170 field. So I will put in along with this in the same locations, the next address fields 370 00:52:52,559 --> 00:52:59,559 within the control memory address register. So you will find that after generating this 371 00:53:00,789 --> 00:53:05,920 control signals, the next control signals are to be generate from the next memory location 372 00:53:05,920 --> 00:53:12,920 within the memory, which is memory location one. So I put the next memory location in 373 00:53:16,239 --> 00:53:23,019 few more bits, I put it as 0 1. Right now I am putting it decimal form but this has 374 00:53:23,019 --> 00:53:27,309 to be coded in to binary and the number of bits required in binary form that has to be 375 00:53:27,309 --> 00:53:34,210 used. For simplicity I am putting this as the decimal number. 376 00:53:34,210 --> 00:53:41,009 So after execution of this, the next address is one that is this particular location in 377 00:53:41,009 --> 00:53:46,450 the control memory. So after generations of this control signals, next time the control 378 00:53:46,450 --> 00:53:53,329 signals will be generate are C4, C3 and C2 and C4, C3, C2 means increment program counter, 379 00:53:53,329 --> 00:54:00,329 read memory and load instruction register. So after these control signals are generated, 380 00:54:00,339 --> 00:54:05,460 the next control signals are to be read from the third location in the control memory. 381 00:54:05,460 --> 00:54:11,930 So I again put in the next address field as 0 2, so you find that I am putting in the 382 00:54:11,930 --> 00:54:18,930 decimal form. So we find that for the simple situation MOV R1, R2 the micro program was 383 00:54:24,519 --> 00:54:30,229 a single micro instruction. So this I can call as a micro instruction, so it is a signal 384 00:54:30,229 --> 00:54:37,229 micro instruction whereas for execution of some other programs may be I need more than 385 00:54:37,390 --> 00:54:42,180 one micro instruction. I think we had taken some such example where you need more than 386 00:54:42,180 --> 00:54:42,710 one. 387 00:54:42,710 --> 00:54:49,710 The example that we had taken is add. One of the instructions that we had is add R1. 388 00:54:59,979 --> 00:55:06,979 In add R1, the micro operations that are to be done is during time machine state T3, the 389 00:55:14,489 --> 00:55:21,489 content of R1 has to be loaded to data register. Then during machine state T4, accumulator 390 00:55:32,539 --> 00:55:38,489 is to be loaded with sum of accumulator and data register. So that we had put in this 391 00:55:38,489 --> 00:55:45,489 way ALU performing add operation on accumulator and data register. So for this operation I 392 00:55:58,309 --> 00:56:05,289 need a micro instruction and the control signals that are needed are load the data register 393 00:56:05,289 --> 00:56:12,289 and output enable of R1. For this micro operation to be executed during machine state T4, the 394 00:56:26,539 --> 00:56:33,539 control signals which are required are load accumulator then we need ALU add control signal 395 00:56:40,549 --> 00:56:47,549 because when this control signal is made equal to one then only ALU will perform add operation. 396 00:56:49,119 --> 00:56:56,119 Simultaneously we also need output enable of ALU because from the ALU, output of the 397 00:56:58,509 --> 00:57:05,509 ALU is going to the common data path. So I also have to activate output enable of ALU. 398 00:57:07,289 --> 00:57:14,289 But does it have only advantage? Yeah, speed wise this will be slow because for generation 399 00:57:15,499 --> 00:57:21,289 of any control signal, I have to read the memory content. So because it is software 400 00:57:21,289 --> 00:57:27,289 in nature, it will be slower than hardware control unit but the advantage is it is more 401 00:57:27,289 --> 00:57:34,289 flexible, gives flexibly while designing and the second advantage is it is more compact 402 00:57:34,630 --> 00:57:41,630 because the full lot of hardware control circuit is now put in just the control memory. So 403 00:57:42,569 --> 00:57:49,569 it is compact and flexible but speed wise it will be slower. That accuracy does not 404 00:57:59,259 --> 00:58:04,189 matter much. So with this we will take a break. 405