﻿1 00:00:57,399 --> 00:01:04,399 Now let us see that given this instruction, set of instructions and the instruction format, 2 00:01:06,960 --> 00:01:13,960 how we can design the hardware? So here for designing the hardware, what you have to do 3 00:01:19,360 --> 00:01:26,360 is we have to study each of these instruction in detail that what these instructions are 4 00:01:28,090 --> 00:01:35,090 doing and in which sequence those operations will be done. However you will see that few 5 00:01:36,750 --> 00:01:42,140 of the operations for execution of any of these instructions are common. 6 00:01:42,140 --> 00:01:49,140 For example whenever the CPU will execute any instruction, the first one as we have 7 00:01:49,810 --> 00:01:56,810 said is an opcode fetch cycle. That is the instruction has to be read from the main memory 8 00:01:59,200 --> 00:02:05,349 and it has to be put into the instruction register. After that it will be decoded, the 9 00:02:05,349 --> 00:02:07,920 signal will be given to the control and timing circuit. 10 00:02:07,920 --> 00:02:11,440 The control and timing circuit will generate the control signals, the required control 11 00:02:11,440 --> 00:02:18,440 signals in the required signals. So the first cycle that is opcode fetch cycle, it is common 12 00:02:19,209 --> 00:02:26,209 for each and every instruction. So let us see how this opcode fetch cycle will be performed. 13 00:02:30,900 --> 00:02:37,370 For opcode fetch as we have said that this is similar to a memory read operation that 14 00:02:37,370 --> 00:02:44,159 means the memory address register has to be set with the address of the instruction that 15 00:02:44,159 --> 00:02:51,159 is going to be fetched and we know that the address of the instruction which will be executed 16 00:02:51,709 --> 00:02:58,709 resides in the program counter. So the first operation that has to be done is setting the 17 00:03:00,319 --> 00:03:06,849 data into the memory address register or address into the memory address register and this 18 00:03:06,849 --> 00:03:13,849 will come from the program counter. So the first operation will be, you have to load 19 00:03:15,239 --> 00:03:22,239 the memory address register with the content of the program counter. 20 00:03:28,689 --> 00:03:35,680 So once the content of program counter goes to the memory address register then that particular 21 00:03:35,680 --> 00:03:41,829 address, that particular location in the memory has to be read and whatever you read from 22 00:03:41,829 --> 00:03:48,689 that address has to be put into the instruction register. So next operation that will be performed 23 00:03:48,689 --> 00:03:55,689 is instruction register gets the value from memory whose address comes from memory address 24 00:04:01,079 --> 00:04:08,079 register. At the same time what I can do is because once you read an instruction, the program counter 25 00:04:16,209 --> 00:04:23,209 has to be incremented so that it points to the next instruction in the memory. Here I 26 00:04:23,490 --> 00:04:30,490 assume that each and every instruction takes just one location in the memory. So the address 27 00:04:34,000 --> 00:04:39,699 of the next instruction which will be executed is the next location in the memory. 28 00:04:39,699 --> 00:04:46,699 So I simply increment the program counter by one. This is a simplified situation where 29 00:04:47,490 --> 00:04:53,690 my assumption is every instruction occupies only one location in the memory but for a 30 00:04:53,690 --> 00:04:59,430 complicated situation where if I incorporate the provision that the instruction length 31 00:04:59,430 --> 00:05:05,520 can be varied. It need not necessarily be one location, it can be multiple locations. 32 00:05:05,520 --> 00:05:12,060 In that case I cannot simply increment the program counter here. Incrementation of the 33 00:05:12,060 --> 00:05:18,030 program counter has to be done after decoding the instruction because only when you decode 34 00:05:18,030 --> 00:05:21,870 the instruction you would know what is the length of the instruction and the program 35 00:05:21,870 --> 00:05:27,110 counter has to be incremented accordingly. But for our simple case because I am assuming 36 00:05:27,110 --> 00:05:33,620 that every instruction is loaded in only one location in memory so I can just increment 37 00:05:33,620 --> 00:05:40,620 the program counter at this point. Now after that you have to decode the instruction. 38 00:05:43,000 --> 00:05:50,000 So decode the content of instruction register. So these are the operations which are to be 39 00:05:59,439 --> 00:06:05,990 performed always. Now simultaneously when I decode the instruction, I can do one more 40 00:06:05,990 --> 00:06:12,699 additional thing because till now I do not know what is the type of instruction that 41 00:06:12,699 --> 00:06:18,419 I am going to execute because decoding is not yet complete. It is possible that it is 42 00:06:18,419 --> 00:06:25,419 a memory reference instruction. So there is no harm that from the instruction register, 43 00:06:25,539 --> 00:06:32,539 the lower 12 bits which is supposed to be the operand address for the memory reference 44 00:06:32,560 --> 00:06:39,560 instructions. Simultaneously while decoding, I can send the content from lower 12 bits 45 00:06:40,840 --> 00:06:47,840 of the instruction register to memory address register. Even if this is not needed but this 46 00:06:54,229 --> 00:07:01,229 does not harm, so what I will do is I will shift the lower 12 bits of the instruction 47 00:07:01,740 --> 00:07:08,159 register that is IR0 to IR11 to the memory address register during the same time when 48 00:07:08,159 --> 00:07:14,400 the instruction is decoded. These are the operations which are common for execution 49 00:07:14,400 --> 00:07:21,400 of any instruction and the operations are to be done in this sequence. 50 00:07:21,509 --> 00:07:28,509 So what I can do is I can define some timing intervals that during a particular time, program 51 00:07:28,979 --> 00:07:33,099 counter content will go to be memory address register. During the next interval of time 52 00:07:33,099 --> 00:07:40,099 for instruction in that case my address of the memory that is to be read is already available 53 00:08:10,379 --> 00:08:16,349 in memory address register. So I don’t have to spend any additional time to set the memory 54 00:08:16,349 --> 00:08:23,349 address register that is the advantage. Even if it is not needed, this does not harm. So 55 00:08:24,819 --> 00:08:31,819 I will define this timing intervals as T0, T1 and T2. I am referring T your 8085 microprocessor. 56 00:08:43,620 --> 00:08:50,620 You know that these timing intervals are popularly known as machine states. I hope you are aware 57 00:08:51,560 --> 00:08:58,560 of the term. So these are different machine states T0, T1 and T2. During T0 the operation 58 00:08:58,800 --> 00:09:05,240 is specific, during T1 the operation is specific, during T2 the operation is also specific. 59 00:09:05,240 --> 00:09:12,240 T3 onwards the operations will be dictated by the decoder output. 60 00:09:14,210 --> 00:09:20,380 How many such states will be needed for execution of a particular instruction that depends upon 61 00:09:20,380 --> 00:09:27,370 what is the instruction that you are going to execute. So like this. So this to decide 62 00:09:27,370 --> 00:09:34,090 the operations during these states T3 onwards, I have to analyze each and every instruction 63 00:09:34,090 --> 00:09:41,090 in details. So let us take few of the instructions. See what is to be done during T3 T4 like this, 64 00:09:46,140 --> 00:09:53,140 so this is T4. So let us take few of the instructions. Let me consider the first instruction say 65 00:09:58,980 --> 00:10:05,470 ADD R1. What we have to do for addition of R1? 66 00:10:05,470 --> 00:10:12,470 So the instruction that I am considering is the instruction ADD R1 and we know that this 67 00:10:21,470 --> 00:10:28,470 is performing a function of adding the content of the accumulator with register R1 and the 68 00:10:33,520 --> 00:10:40,520 result goes to accumulator where accumulator is the destination address. So this is the 69 00:10:43,010 --> 00:10:49,190 operation that will be performed by this instruction ADD R1. 70 00:10:49,190 --> 00:10:56,190 Now if you look at the architecture that we are considering. I have this ALU, the addition 71 00:10:58,810 --> 00:11:05,810 operation has to be performed by this ALU which needs two operands. For this instruction 72 00:11:06,130 --> 00:11:13,130 ADD R1 one of the operands is in the accumulator, the other operand is in register R1 but R1 73 00:11:14,390 --> 00:11:19,130 is not directly connected to accumulator. That means I cannot get the data from R1 to 74 00:11:19,130 --> 00:11:23,380 ADD with the content of accumulator and feed the results to accumulator which is not possible 75 00:11:23,380 --> 00:11:30,380 as far this architecture. So the ALU is getting data from accumulator and the data register 76 00:11:32,760 --> 00:11:39,680 DR. One of the operands is in the accumulator, the other operand we have to load into the 77 00:11:39,680 --> 00:11:46,680 data register. So that means from R1 that data has to be transferred to date register 78 00:11:48,830 --> 00:11:55,830 before this addition operation can be performed. So that is the first step. So for execution 79 00:11:57,500 --> 00:12:04,500 of this ADD R1 the first operation that we have to perform is load the data into data 80 00:12:09,040 --> 00:12:16,040 register from register R1 that is a first operation. Then once you have the data into 81 00:12:22,000 --> 00:12:27,820 the data register, if I assume that output of accumulator is always connected to ALU, 82 00:12:27,820 --> 00:12:34,230 output of data register is always connected to ALU. That means I don’t need any extra 83 00:12:34,230 --> 00:12:41,230 timing signal to set up this path. The accumulator to ALU, this path and data register to ALU 84 00:12:42,830 --> 00:12:47,980 this path, I don’t need any extra timing signal to activate these two. I can assume 85 00:12:47,980 --> 00:12:53,920 that those are always connected but what is the important is whether ALU output can be 86 00:12:53,920 --> 00:13:00,920 activated or not. ALU output is to be activated only when you perform either some arithmetic 87 00:13:02,640 --> 00:13:09,640 operation or some logical operation where ALU is involved. So output of the ALU will 88 00:13:10,450 --> 00:13:15,750 go to the data path only when we need the output from the ALU. 89 00:13:15,750 --> 00:13:22,750 In this case that is needed. So once I said the data into the data register from register 90 00:13:24,550 --> 00:13:31,550 R1 the next operation that will be performed is accumulator will get the output of ALU 91 00:13:35,170 --> 00:13:42,170 and in this case the function of the ALU is ADD function. So I will put it this way, ALUADD 92 00:13:48,500 --> 00:13:55,500 then accumulator and data register. I will come to that. So these are the two operations 93 00:14:12,490 --> 00:14:19,490 which are to be performed while execution of this ADD R1 instruction. These type of 94 00:14:20,930 --> 00:14:27,930 operations are called micro-operations. ADD R1 is a complete operation, you break that 95 00:14:28,110 --> 00:14:34,770 operation into a number of micro-operations in sequence. So when all those micro-operations 96 00:14:34,770 --> 00:14:41,770 in the proper sequence are complete then only the execution of the instruction is complete. 97 00:14:43,300 --> 00:14:46,130 So what are the timing signals that will be needed? 98 00:14:46,130 --> 00:14:53,130 For first operation that is loading the data from R1 to DR, I need one time interval.Why 99 00:14:54,810 --> 00:15:01,810 do we need two symbols? but as we said that both of them can be done simultaneously. You 100 00:15:03,600 --> 00:15:10,600 refer to that figure here. Both of them can be done simultaneously because output is enabled 101 00:15:14,200 --> 00:15:20,250 simultaneously, I activate the load input of data register. So one time interval is 102 00:15:20,250 --> 00:15:27,250 sufficient. So for this I need one time interval. We will see that later. 103 00:15:30,510 --> 00:15:37,510 So for this, it will take, let us assume that it will take one time interval. For this also 104 00:15:37,590 --> 00:15:44,590 it will take one time interval. So earlier we had three time intervals T0, T1 and T2. 105 00:15:48,090 --> 00:15:55,090 Now during T3, I can assume that this operation can be done. During T4 this operation can 106 00:15:57,000 --> 00:16:04,000 be done. Yeah but ALU is a combinational circuit. ALU is a computational circuit, the output 107 00:16:13,930 --> 00:16:20,930 will be available after few gate delays. So if we assume that each of this time at interval 108 00:16:21,440 --> 00:16:27,700 is long enough to take care of that gate delay, this one time clock is sufficient. That is 109 00:16:27,700 --> 00:16:33,870 the final details as I said it may so happen that if my circuit is very high frequency 110 00:16:33,870 --> 00:16:39,220 circuit. I am operating the CPU at very high frequency where each of this time intervals 111 00:16:39,220 --> 00:16:45,070 will be very small. So that a single time interval cannot take 112 00:16:45,070 --> 00:16:50,660 care of the gate delay. In that case we may have to extend it. Instead of only T4, I can 113 00:16:50,660 --> 00:16:56,630 go for, I may have to go for T4, T5, T6 and so on or also of them together to get an extended 114 00:16:56,630 --> 00:17:03,630 time interval. Load the data, output of ALU into accumulator at the end of that extended 115 00:17:03,880 --> 00:17:10,880 time interval. So those are all finer specification or finer details which has to be done at the 116 00:17:12,439 --> 00:17:18,909 time of implementation but logically this is okay. Based on my assumption that each 117 00:17:18,909 --> 00:17:25,909 of this time interval is long enough to accommodate the hectics. So during the time interval T3, 118 00:17:29,100 --> 00:17:35,730 R1 will be loaded into data register. During time interval T4, output of ALU will go to 119 00:17:35,730 --> 00:17:37,110 the accumulator. 120 00:17:37,110 --> 00:17:44,110 Now the question is ALU is a multi function chip, it performs various operations out of 121 00:17:44,429 --> 00:17:51,260 which I want only the ADD operation. So as you know that ALU has got some functional 122 00:17:51,260 --> 00:17:58,260 select inputs. By selecting those inputs properly I can define that which operation the ALU 123 00:18:00,440 --> 00:18:07,170 will perform. Now it is the timing and control circuit which once it gets the input from 124 00:18:07,170 --> 00:18:11,910 the instruction decoder, it knows that it is the addition operation that will be performed. 125 00:18:11,910 --> 00:18:17,520 So again the timing and control circuit can generate control signals which will be fed 126 00:18:17,520 --> 00:18:24,520 to the function select input of the ALU and those signals should be available during the 127 00:18:26,540 --> 00:18:31,470 time interval T4. 128 00:18:31,470 --> 00:18:37,170 Now once that is done, now the function of ALU become specific. Instead of a general 129 00:18:37,170 --> 00:18:43,190 purpose ALU with these select inputs available, function select inputs available, the ALU 130 00:18:43,190 --> 00:18:50,130 becomes simply an ADD circuit, a combinational circuit performing an addition operation. 131 00:18:50,130 --> 00:18:57,130 So output of that will be sum of accumulator and data register. I have to make a provision 132 00:18:57,380 --> 00:19:03,930 that output enable of ALU should be active so that this added result will be available 133 00:19:03,930 --> 00:19:09,850 onto the data path. Then I have to activate the load input of the accumulator so that 134 00:19:09,850 --> 00:19:16,850 from this data path, this result can be loaded back into the accumulator itself. 135 00:19:18,740 --> 00:19:24,730 So for execution of this ADD instruction including the output phase, I need total 5 intervals 136 00:19:24,730 --> 00:19:31,730 T0, T1, T2, T3 and T4. Out of which T0, T1 and T2 these are common for all the instructions. 137 00:19:34,040 --> 00:19:41,040 T3 and T4, these two time intervals the micro-operations during these two time intervals depends upon 138 00:19:41,790 --> 00:19:48,790 the instruction. Now this is not sufficient, I have to care of one more thing. That is 139 00:19:49,950 --> 00:19:56,950 at the end of T4, execution of this instruction is complete but I must set the machine in 140 00:19:57,600 --> 00:20:04,360 such a way that the machine is ready to fetch the next instruction and execute. As we have 141 00:20:04,360 --> 00:20:11,360 said that fetching the next instruction starts at time interval T0. That means at the end 142 00:20:15,180 --> 00:20:22,180 of T4 I must set the state to time interval T0. So these are the operations to be performed 143 00:20:28,290 --> 00:20:35,290 for this ADD R1 instruction. 144 00:20:36,780 --> 00:20:42,350 Let us take another instruction, so this was a register reference instruction. Similarly 145 00:20:42,350 --> 00:20:47,550 you find that this is the addition instruction which is register reference instruction. If 146 00:20:47,550 --> 00:20:54,550 I simply have a data transfer operation say move R1, R2. If this is the instruction which 147 00:21:05,250 --> 00:21:11,920 has to be executed as before, the first three time intervals during this the operations 148 00:21:11,920 --> 00:21:17,840 are specific, this has to be done. We have to specify that what will be done during T3, 149 00:21:17,840 --> 00:21:24,010 what will be done during T4. This being simply register transfer operation for transferring 150 00:21:24,010 --> 00:21:30,030 the data from one register to another register, just one time interval is sufficient. So I 151 00:21:30,030 --> 00:21:37,030 have to have time interval T3 during which the micro-operation of transferring data from 152 00:21:39,420 --> 00:21:46,420 R2 to R1 will be done. At the end of this operation, I have to put the machine in times 153 00:21:52,050 --> 00:21:55,380 at T0. 154 00:21:55,380 --> 00:22:02,380 The hardware that I am going to design that should take care of all these things. Is that 155 00:22:02,720 --> 00:22:09,720 okay? Let us take a memory reference operation and in our instruction said, we have put only 156 00:22:11,640 --> 00:22:18,470 memory reference instruction which are data transfer operations like move accumulator, 157 00:22:18,470 --> 00:22:24,160 memory or move memory, accumulator. These are the only two memory reference instructions 158 00:22:24,160 --> 00:22:31,160 that we have put. Let us take any of them say move accumulator, memory. So these are 159 00:22:42,790 --> 00:22:49,790 the instructions that we are doing. So here again an operations during T0, operations 160 00:22:56,890 --> 00:23:03,890 during T1, operation during T2, they are already defined. Here get you get the advantage. 161 00:23:06,850 --> 00:23:13,850 You find that during time interval T2 what we have done is along with decoding the instruction, 162 00:23:14,790 --> 00:23:21,090 we have also transferred the content of instruction register 0 to 11, this is 12 bits to memory 163 00:23:21,090 --> 00:23:27,550 address register. That means that the address of the memory which is to be read and transferred 164 00:23:27,550 --> 00:23:33,710 to accumulator that is already said. I don’t need any extra time interval to perform this 165 00:23:33,710 --> 00:23:40,710 operation which otherwise would have been needed. So here what I can do is during time 166 00:23:41,770 --> 00:23:48,770 interval T3, I can directly read the content of the memory and load that into accumulator. 167 00:23:50,720 --> 00:23:57,720 So I can straight away perform the operation of loading the content of memory with address 168 00:24:04,700 --> 00:24:11,700 in the memory address register to accumulator.Yeah exactly that is my assumption. As before after 169 00:24:19,050 --> 00:24:25,770 this operation is done what I have to do is, I have to set commission state to T0 so that 170 00:24:25,770 --> 00:24:32,770 the machine is now ready for fetching the next instruction and executing it. 171 00:24:33,990 --> 00:24:37,670 So now let us see that what are the hardware components that we need. However this can 172 00:24:37,670 --> 00:24:43,090 be expanded when you implement the entire system, what you have to do is you have to 173 00:24:43,090 --> 00:24:50,090 do this kind of analysis for each and every instruction so that you can design the complete 174 00:24:50,450 --> 00:24:57,450 instruction decoder, you can design the complete timing and control circuit. Let us see what 175 00:24:57,490 --> 00:25:04,490 will be the situation with these instructions only. So it is clear that I need two specific 176 00:25:11,460 --> 00:25:18,460 units. One for decoding the instruction, the other unit for generating the machine states 177 00:25:18,790 --> 00:25:25,790 or generating the time intervals T0, T1, T2, T3 and so on. Now what is this simplest way 178 00:25:27,040 --> 00:25:34,040 of generating the machine states? You simply use a counter, output of the counter you fit 179 00:25:38,160 --> 00:25:45,160 to a decoder. So for generating the machine states, the unit that we can use is something 180 00:25:47,920 --> 00:25:49,559 like this. 181 00:25:49,559 --> 00:25:56,559 I use a counter. The 182 00:26:06,570 --> 00:26:13,570 counter output will be fed to a decoder. Then depending upon of the state of the counter, 183 00:26:25,350 --> 00:26:32,350 one of the decoder outputs will be active. So if I assume that this counter is a 4 bit 184 00:26:35,150 --> 00:26:40,480 counter, let us assume this. Now how many bits you need in the counter that depends 185 00:26:40,480 --> 00:26:47,480 upon what is the complexity of an instruction. So here when I assume that my counter is a 186 00:26:49,890 --> 00:26:56,890 4 bit counter that means I can have 16 different machine states that is T0 to T15 and none 187 00:26:57,070 --> 00:27:04,070 of the instructions, in this case can take more than 16 times states including the opcode 188 00:27:04,600 --> 00:27:10,260 fetch cycle. 189 00:27:10,260 --> 00:27:16,429 If you have any instruction which takes more than 16 time states for execution, completion 190 00:27:16,429 --> 00:27:22,010 of the execution 4 bit counter will not be sufficient. I may have to go for 5 bits counter, 191 00:27:22,010 --> 00:27:26,559 6 bit counters. So then how many bits you need in the counter that depends upon the 192 00:27:26,559 --> 00:27:32,130 complexity of the instructions that you have within the instruction set. That can be decided 193 00:27:32,130 --> 00:27:39,130 only after complete analysis of all the instructions in the instruction set. So when this counter 194 00:27:39,660 --> 00:27:46,660 output is fed to the decoder, the decoder outputs will generate different time states. 195 00:27:48,059 --> 00:27:55,059 So this is T0, T1 so like this I will have up to T15. So with this my machine state generator 196 00:28:03,590 --> 00:28:06,210 is complete. 197 00:28:06,210 --> 00:28:13,210 On the other side what I need to have is an instruction decoder. Instruction decoder gets 198 00:28:17,210 --> 00:28:24,210 input from the instruction register so I will put it this way. This is my instruction register 199 00:28:28,929 --> 00:28:35,929 IR which is having as we have said, it will have 16 bits IR0-15. Out of this right now 200 00:28:42,130 --> 00:28:49,130 we are not making use of the most significant bit that is IR15. I will extend this later. 201 00:28:50,480 --> 00:28:57,480 The next three bits I am saying that this contains the opcode of the instruction. So 202 00:29:01,460 --> 00:29:08,460 the simplest way is you have a decoder, here it will be a 3 to 8 decoder. So I have a decoder 203 00:29:15,059 --> 00:29:22,059 which is a 3 to 8 decoder because it takes 3 inputs from the instruction register and 204 00:29:25,270 --> 00:29:32,270 it generates 8 outputs D0 to D7. So now my instruction decoding circuit is done. The 205 00:29:41,110 --> 00:29:47,490 machine state generator circuit is done. What I have to do next? I have to combine these 206 00:29:47,490 --> 00:29:54,490 two to generate the control signals. That means the timing and control circuit, yeah 207 00:30:05,799 --> 00:30:12,799 for register reference instructions, yeah that is true. input to the counter, yeah. 208 00:30:16,790 --> 00:30:23,790 Counter will have one input of clear, that is the set, counter will have one input called 209 00:30:24,580 --> 00:30:31,580 increment, counter will have another input called clock. So this clock is the master 210 00:30:32,190 --> 00:30:39,190 clock or assumption is when this increment input is one, with every clock pulse the counter 211 00:30:39,540 --> 00:30:41,850 will be incremented by one. 212 00:30:41,850 --> 00:30:46,860 When the clear input is one, with this clock pulse the counter will be clear to say and 213 00:30:46,860 --> 00:30:53,860 that is what will enable us to set the machine state to zero after performing desired operation. 214 00:30:56,400 --> 00:31:01,350 This design means I have to set to that how these inputs will be generated so that requires 215 00:31:01,350 --> 00:31:08,350 some of that, when I need to increment the counter, when I need to clear the clear counter. 216 00:31:12,309 --> 00:31:19,309 So this now becomes the timing and control circuit. The timing and control circuit gets input from this instruction decoder. 217 00:31:37,350 --> 00:31:44,350 It gets from this, input from this machine state generator. It also makes use of these 218 00:31:52,559 --> 00:31:59,559 inputs IR0 to IR11 for register reference instructions because these are the bits which 219 00:32:09,669 --> 00:32:16,510 uniquely identify a register reference instruction. For register reference instruction this D7 220 00:32:16,510 --> 00:32:23,510 will be active and this gives you all the timing and control outputs. So as a higher 221 00:32:34,880 --> 00:32:41,880 level schematic, I can say this thing will be timing and control unit along with this 222 00:32:42,390 --> 00:32:49,390 and this performs your instruction decoding unit. Timing and control gets this input so 223 00:32:50,760 --> 00:32:57,760 I can say that this is also a part of timing and control and this counter is normally known 224 00:32:57,890 --> 00:33:04,890 as a sequence counter. Is it okay? 225 00:33:09,780 --> 00:33:16,780 Now the thing is what will be done initially? You all know that whenever you switch on the 226 00:33:17,440 --> 00:33:24,440 power of 8085 or you reset a 8085, the program counter of 8085 becomes 0 and you all know 227 00:33:25,870 --> 00:33:32,870 that the zero th location in the main memory must contain an instruction. If it does not 228 00:33:33,049 --> 00:33:40,049 contain an instruction then however sophisticated hardware you design, that microprocessor based 229 00:33:40,840 --> 00:33:47,679 system will never work. Why? Because whenever you are switching on the machine or whenever 230 00:33:47,679 --> 00:33:53,970 you are resetting the 8085, the first time state which is generated is time state T0. 231 00:33:53,970 --> 00:34:00,500 That means initially the sequence counter will be set to state zero and during time 232 00:34:00,500 --> 00:34:07,500 state T0, the operation is specific. This is hardware specific, this is not programmable. 233 00:34:08,579 --> 00:34:13,730 That is the program counter goes to the memory address register and whatever you get from 234 00:34:13,730 --> 00:34:19,720 the memory at that particular location that goes to instruction register, it its decoded 235 00:34:19,720 --> 00:34:26,720 and then finally other operations are decided. So in the zero th location in the main memory 236 00:34:27,260 --> 00:34:33,089 for an 8085 based system I put anything other than an instruction, the instruction decoder 237 00:34:33,089 --> 00:34:39,319 will not give me any value. It will give me some … and timing and control circuit cannot 238 00:34:39,319 --> 00:34:44,399 recognize that, it cannot generate any proper timing control signal. 239 00:34:44,399 --> 00:34:51,399 Effectively the system will fail. So that is the reason that it is always told that 240 00:34:53,889 --> 00:34:59,329 zero th location in 8085 based system should always contain an instruction. Typically what 241 00:34:59,329 --> 00:35:05,499 you put is a jump instruction and with that jump instruction you come to a bigger routine 242 00:35:05,499 --> 00:35:12,009 which is your main program and that location is different for different CPU’s. It is 243 00:35:12,009 --> 00:35:19,009 not that for every CPU it has to be 0 0 0, that location is different. So with this, 244 00:35:22,999 --> 00:35:29,999 these two parts are complete. Now let us see how this block is to be realized. So for realization 245 00:35:35,229 --> 00:35:42,229 of this block, let us again come to yeah. So we know that during time interval T0, your 246 00:35:48,569 --> 00:35:55,569 program counter content has to be loaded into memory address register, that is known. So 247 00:35:57,190 --> 00:36:03,029 what are the control signals that are needed for this? I have to activate the output enable 248 00:36:03,029 --> 00:36:10,029 of program counter. I have to activate the load input of memory address register. So 249 00:36:11,499 --> 00:36:16,970 during time interval T0, program counter output has to be enabled. Memory address register 250 00:36:16,970 --> 00:36:23,970 load input has to be enabled. So let me list out the control signals for the instructions 251 00:36:25,440 --> 00:36:32,440 that we are considering. One is program counter, one is memory address register. 252 00:36:47,700 --> 00:36:54,700 So for program counter I have output enable control signal, for memory address register 253 00:36:55,769 --> 00:37:02,769 So far what we have encountered is load control input. We have said that during time interval 254 00:37:05,470 --> 00:37:12,470 T0, output enable of program counter must be active. During time interval T0, load input 255 00:37:13,069 --> 00:37:19,329 of memory address register must be active. They may be active in other situations as 256 00:37:19,329 --> 00:37:26,329 well but during T0 they must be active. So what I will put is I will set output enable 257 00:37:27,039 --> 00:37:34,039 of program counter is equal to T0 OR, so I put an OR condition because when T0 is true, 258 00:37:39,499 --> 00:37:44,859 output enable of program counter has to be true because it is an OR logic. 259 00:37:44,859 --> 00:37:51,859 Similarly for load input of memory address register, I will also put as T0 OR. That is 260 00:37:52,819 --> 00:37:59,819 whenever T0, machine is in T0 load input of memory address register has to be active others 261 00:38:00,989 --> 00:38:07,989 will come later on. So that is what is done during T0. The next time interval is T1. During 262 00:38:12,670 --> 00:38:19,670 T1 what are the registers that are involved? one is instruction register otherwise the 263 00:38:20,210 --> 00:38:27,210 program counter. So I have the next register which is instruction register, I have program 264 00:38:31,460 --> 00:38:38,460 counter. The control signals that are encountered till now for instruction register, it is the 265 00:38:44,079 --> 00:38:51,079 load input. For program counter it is the increment input INR. So if you remember this 266 00:38:55,609 --> 00:39:01,279 block diagram, you find that for the sequence, sorry this is the program counter not the 267 00:39:01,279 --> 00:39:02,269 sequence counter. 268 00:39:02,269 --> 00:39:09,269 So for program counter I have an increment input and the condition is during time interval 269 00:39:10,420 --> 00:39:17,420 T1, the load input of the instruction register must be active. So I said T1 OR whatever be 270 00:39:21,049 --> 00:39:27,609 the other conditions, during T1 the machine state load input must be active. Similarly 271 00:39:27,609 --> 00:39:33,470 for increment of the program counter during time state T1, the increment input must be 272 00:39:33,470 --> 00:39:39,650 active. Here following the same logic as in case of sequence counter, I assume that clock 273 00:39:39,650 --> 00:39:46,299 input is also going to the program counter. So whenever increment control input of the 274 00:39:46,299 --> 00:39:53,299 program counter is active with every clock pulse, the program counter content will be 275 00:39:55,119 --> 00:39:58,880 incremented by one. 276 00:39:58,880 --> 00:40:05,880 Now what is done during time interval T2? During time interval T2, you find that the 277 00:40:06,749 --> 00:40:13,749 instruction is to be decoded. However this decoder is simply a logic circuit. So I need 278 00:40:14,079 --> 00:40:21,079 not specify any control input for this logic circuit because it is the combinational logic 279 00:40:22,329 --> 00:40:28,079 circuit. When it has input after few gate delays, it will give me the output. The thing 280 00:40:28,079 --> 00:40:35,079 that I have to ensure is before time interval T3 starts, the decoder output must be available. 281 00:40:36,039 --> 00:40:43,039 However during time interval T2 again I am loading the content of instruction register 282 00:40:45,319 --> 00:40:52,319 0 to 11, the lower 12 bits of the instruction register into memory address register. So 283 00:40:52,789 --> 00:40:58,160 for this the output enable of instruction register, one output of the instruction register 284 00:40:58,160 --> 00:41:04,539 is always connected to instruction decoder. So for that part I don’t need any activating 285 00:41:04,539 --> 00:41:10,479 signal but the other path from the instruction register which is going over to the common 286 00:41:10,479 --> 00:41:16,630 data path, there I must have some enabling operation, some enabling circuit. 287 00:41:16,630 --> 00:41:23,630 I will say that the output enable of the instruction register, here I have an instruction register, 288 00:41:26,599 --> 00:41:33,599 the output enable of this connects instruction register to common data path, output of the 289 00:41:33,670 --> 00:41:38,779 instruction register to common data path. for inputs we don’t have any problem, input 290 00:41:38,779 --> 00:41:44,640 can go simultaneously to all the destinations but the one for which the load input will 291 00:41:44,640 --> 00:41:51,359 be active that will only load that input, others will not loaded but for output we must 292 00:41:51,359 --> 00:41:57,759 have specific selection otherwise there will be data clash. So for instruction register, 293 00:41:57,759 --> 00:42:04,759 the output enable control will decide the output of instruction register going to the 294 00:42:04,969 --> 00:42:11,969 common data path and this must be active during time interval T2. So I will put it as T2 OR, 295 00:42:14,920 --> 00:42:21,920 so whenever T2 is true output enable of instruction register is true. During time interval T2, 296 00:42:24,170 --> 00:42:28,999 the content of instruction register goes to memory address register. That means the load 297 00:42:28,999 --> 00:42:35,109 input of memory address register also must be active during time interval T2. 298 00:42:35,109 --> 00:42:42,109 So when you go to load input of memory address register, here this should be T0 OR T2. So 299 00:42:49,150 --> 00:42:54,239 with this all the common operations are complete. That is the operation that you have to do 300 00:42:54,239 --> 00:42:59,049 during T0, operation we have to do during T1, the operation we have to do during T2. 301 00:42:59,049 --> 00:43:06,049 Now T3 onwards, the decoder output will come into picture. So for that let us consider 302 00:43:11,479 --> 00:43:18,479 this ADD R1 instruction. We have said that the decoder output for this ADD R1… for 303 00:43:24,019 --> 00:43:31,019 ADD R1 we have said that the D7 output of the decoder will be high because we have said 304 00:43:33,890 --> 00:43:40,749 that 1 1 1 in the opcode tells you that it is a register instruction. 305 00:43:40,749 --> 00:43:47,749 So when the opcode field is 1 1 1, in that case in this decoder that D7 output will be 306 00:43:47,749 --> 00:43:54,749 active. So what will be my logic? During time interval T3, if I find that D7 is high, instruction 307 00:43:58,759 --> 00:44:05,759 decoder output D7 is high and at the same time it is ADD operation if I0, the zero th 308 00:44:08,119 --> 00:44:15,119 bit in the operand field of the instruction register is high then it is ADD R1. So my 309 00:44:17,839 --> 00:44:24,839 logic is if it is time interval T3 and D7 is high and I0 is high. Then what I have do 310 00:44:31,759 --> 00:44:38,759 to? What are the micro-operations? I have to transfer the data from R1 to data register. 311 00:44:43,660 --> 00:44:50,660 So two more registers come into picture, one is register R1 and other one is the register, 312 00:44:54,119 --> 00:45:01,119 data register that is DR. So during time interval T3, if D7 is high and I or R zero or I0 is 313 00:45:11,940 --> 00:45:18,940 high then output enable of R1, so this is output enable of R1 must be high. 314 00:45:31,210 --> 00:45:37,029 Similarly this output of R1 goes to the data register. So I have to activate load input 315 00:45:37,029 --> 00:45:43,719 of the data register. So load input of the data register must be active following the 316 00:45:43,719 --> 00:45:50,719 same condition that if the machine is in state T3 and instruction decoder output D7 is high 317 00:45:51,789 --> 00:45:58,789 and the instruction register bit I0 is high. This is one of the conditions. Whenever this 318 00:45:59,829 --> 00:46:05,819 is true, output enable of register R1 must be active. Whenever this is true, the load 319 00:46:05,819 --> 00:46:11,999 input of register, DR data register must be active. There may be other conditions as well 320 00:46:11,999 --> 00:46:18,999 so I will put as OR condition. So this OR some other condition this will be active. 321 00:46:20,109 --> 00:46:27,109 This OR some other condition this will be active. So with this I will complete my discussion 322 00:46:28,700 --> 00:46:32,559 today. We will continue from this point onwards in the next class. Thank you. 323