Module 2 : Intel 8051 Microcontroller

Lecture 9 : Interrupts in 8051

Interrupts

8051 provides 5 vectored interrupts. They are -

  1. TF0
  2. TF1
  3. RI/TI

Out of these, and    are external interrupts whereas Timer and Serial port interrupts are generated internally. The external interrupts could be negative edge triggered or low level triggered. All these interrupt, when activated, set the corresponding interrupt flags. Except for serial interrupt, the interrupt flags are cleared when the processor branches to the Interrupt Service Routine (ISR). The external interrupt flags are cleared on branching to Interrupt Service Routine (ISR), provided the interrupt is negative edge triggered. For low level triggered external interrupt as well as for serial interrupt, the corresponding flags have to be cleared by software by the programmer.

The schematic representation of the interrupts is as follows -

        Interrupt                                                                                                                                                                                Vector Location
Fig 9.1   8051 Interrupt Details

Each of these interrupts can be individually enabled or disabled by 'setting' or 'clearing' the corresponding bit in the IE (Interrupt Enable Register) SFR. IE contains a global enable bit EA which enables/disables all interrupts at once.

Interrupt Enable register (IE): Address: A8H

EX0     interrupt (External)   enable bit

ET0 Timer-0 interrupt enable bit

EX1    interrupt (External) enable bit

ET1 Timer-1 interrupt enable bit

ES Serial port interrupt enable bit

ET2 Timer-2 interrupt enable bit

EA Enable/Disable all

Setting '1' Enable the corresponding interrupt

Setting '0' Disable the corresponding interrupt

Priority level structure:

Each interrupt source can be programmed to have one of the two priority levels by setting (high priority) or clearing (low priority) a bit in the IP (Interrupt Priority) Register . A low priority interrupt can itself be interrupted by a high priority interrupt, but not by another low priority interrupt. If two interrupts of different priority levels are received simultaneously, the request of higher priority level is served. If the requests of the same priority level are received simultaneously, an internal polling sequence determines which request is to be serviced. Thus, within each priority level, there is a second priority level determined by the polling sequence, as follows.

Interrupt Priority register  (IP)

    '0'       low priority

    '1'      high priority

Interrupt handling:

The interrupt flags are sampled at P2 of S5 of every instruction cycle (Note that every instruction cycle has six states each consisting of P1 and P2 pulses). The samples are polled during the next machine cycle (or instruction cycle). If one of the flags was set at S5P2 of the preceding instruction cycle, the polling detects it and the interrupt process generates a long call (LCALL) to the appropriate vector location of the interrupt. The LCALL is generated provided this hardware generated LCALL is not blocked by any one of the following conditions.

  1. An interrupt of equal or higher priority level is already in progress.
  2. The current polling cycle is not the final cycle in the execution of the instruction in progress.
  3. The instruction in progress is RETI or any write to IE or IP registers.

When an interrupt comes and the program is directed to the interrupt vector address, the Program Counter (PC) value of the interrupted program is stored (pushed) on the stack. The required Interrupt Service Routine (ISR) is executed. At the end of the ISR, the instruction RETI returns the value of the PC from the stack and the originally interrupted program is resumed.

Reset is a non-maskable interrupt. A reset is accomplished by holding the RST pin high for at least two machine cycles. On resetting the program starts from 0000H and some flags are modified as follows -

 

Register

Value(Hex) on Reset

PC

0000H
DPTR
0000H

A

00H
B
00H

SP

07H
PSW
00H

Ports P0-3 Latches

FFH
IP
XXX 00000 b

IE

0 XX 00000 b
TCON
00H

TMOD

00H
TH0
00H

TL0

00H
TH1
00H

TL1

00H
SCON
00H

SBUF

XX H
PCON
0  XXXX XXX  b

The schematic diagram of the detection and processing of interrupts is given as follows.

Instruction Cycles

Fig 9.2   Interrupt Handling in 8051

It should be noted that the interrupt which is blocked due to the three conditions mentioned before is not remembered unless the flag that generated interrupt is not still active when the above blocking conditions are removed, i.e. ,every polling cycle is new.