Module 2 : Intel 8051 Microcontroller

Lecture 5 : Introduction to Intel 8051 Microcontroller

Some of the microcontrollers of 8051 family are given as follows:

DEVICE

ON-CHIP DATA MEMORY

(bytes)

ON-CHIP PROGRAM MEMORY

(bytes)

16-BIT TIMER/COUNTER

NO. OF VECTORED INTERUPTS

FULL DUPLEX I/O

8031

128

None

2

5

1

8032
256
none
2
6
1

8051

128

4k ROM

2

5

1

8052

256

8k ROM

3

6

1

8751

128

4k EPROM

2

5

1

8752

256

8k EPROM

3

6

1

AT89C51

128

4k Flash Memory

2

5

1

AT89C52

256

8k Flash memory

3

6

1

 

Basic 8051 Architecture

8051 employs Harvard architecture. It has some peripherals such as 32 bit digital I/O, Timers and Serial I/O. The basic architecture of 8051 is given in fig 5.1

Fig 5.1 : Basic 8051 Architecture

Various features of 8051 microcontroller are given as follows.
  • 8-bit CPU
  • 16-bit Program Counter
  • 8-bit Processor Status Word (PSW)
  • 8-bit Stack Pointer
  • Internal RAM of 128bytes
  • Special Function Registers (SFRs) of 128 bytes
  • 32 I/O pins arranged as four 8-bit ports (P0 - P3)
  • Two 16-bit timer/counters : T0 and T1
  • Two external and three internal vectored interrupts
  • One full duplex serial I/O

8051 Clock and Instruction Cycle

In 8051, one instruction cycle consists of twelve (12) clock cycles. Instruction cycle is sometimes called as Machine cycle by some authors.

Fig 5.2 : Instruction cycle of 8051

In 8051, each instruction cycle has six states (S 1 - S 6 ). Each state has two pulses (P1 and P2)

128 bytes of Internal RAM Structure (lower address space)

Fig 5.3: Internal RAM Structure

The lower 32 bytes are divided into 4 separate banks. Each register bank has 8 registers of one byte each. A register bank is selected depending upon two bank select bits in the PSW register. Next 16bytes are bit addressable. In total, 128bits (16X8) are available in bitaddressable area. Each bit can be accessed and modified by suitable instructions. The bit addresses are from 00H (LSB of the first byte in 20H) to 7FH (MSB of the last byte in 2FH). Remaining 80bytes of RAM are available for general purpose.

Internal Data Memory and Special Function Register (SFR) Map

 

Fig 5.4 : Internal Data Memory Map

The special function registers (SFRs) are mapped in the upper 128 bytes of internal data memory address. Hence there is an address overlap between the upper 128 bytes of data RAM and SFRs. Please note that the upper 128 bytes of data RAM are present only in the 8052 family. The lower128 bytes of RAM (00H - 7FH) can be accessed both by direct or indirect addressing while the upper 128 bytes of RAM (80H - FFH) are accessed by indirect addressing.The SFRs (80H - FFH) are accessed by direct addressing only. This feature distinguishes the upper 128 bytes of memory from the SFRs, as shown in fig 5.4.

SFR Map

The set of Special Function Registers (SFRs) contains important registers such as Accumulator, Register B, I/O Port latch registers, Stack pointer, Data Pointer, Processor Status Word (PSW) and various control registers. Some of these registers are bit addressable (they are marked with a * in the diagram below). The detailed map of various registers is shown in the following figure.

Address
F8H                
F0H B*              
E8H                
E0H ACC*              
D8H                
D0H PSW*              
C8H (T2CON)*   (RCAP2L) (RCAP2H) (TL2) (TH2)    
C0H                
B8H IP*              
B0H P3*              
A8H IE*              
A0H P2*              
98H SCON* SBUF            
90H P1*              
88H TCON* TMOD TL0 TL1 TH0 TH1    
80H P0* SP DPL DPH       PCON

Fig 5.5: SFR Map

It should be noted hat all registers appearing in the first column are bit addressable. The bit address of a bit in the register is calculated as follows.
Bit address of 'b' bit of register 'R' is
                       Address of register 'R' + b
                       where  0   ≤  b ≤ 7

Processor Status Word (PSW)     Address=D0H

Fi g 5.6: Processor Status Word

PSW register stores the important status conditions of the microcontroller. It also stores the bank select bits (RS1 & RS0) for register bank selection.