Module 4 : Architecture of Advanced Microprocessor

Lecture 33 : Intel 80386 - A 32-bit Microprocessor with Memory Paging Facility

 

Intel 80386 - A 32-bit Microprocessor with Memory Paging Facility

Intel 80386 is a logical extension of the 80286 microprocessor. The basic architecture of 80386 is given here.

Fig. 33.1  Basic architecture of 80386 microprocessor

Features of 80386:
  • More highly pipelined than 80286
  • Instruction fetching, instruction decoding, instruction execution and memory management are all carried out in parallel.
  • 32-bit data bus
  • 32-bit non-multiplexed address bus
  • 232  = 4 Gigabyte of physical memory
  • 246 or 64 Terabyte of virtual memory.
Instruction set compatibility :

Instruction sets of Intel microprocessors have upward compatibility (for example, a program written in 80186 can run in any higher 80286 or 80386 architecture).

Fig.  33.2   Instruction sets of Intel microprocessors (8086/8088 to 80386) are upward compatible
Segment registers:
 
Real address mode of 80386

After reset, the 80386 starts from the memory location FFFFFFF0 H under real address mode. In real address mode, 80386 works as a fast 8086 with 32 bit registers and data types. The addressing techniques, memory size, interrupt handling in this mode of 80386 are similar to the real addressing mode of 80286. In real address mode, the default operand size is 16 bit but 32 bit operands and addressing modes may be used with the help of override prefixer.

Maximum physical memory  = 1Mega byte
0000 0000 - 000FFFFF (A 0 -A 19 ).
Maximum virtual memory:
2 14x2 32 = 2 46 bytes or 64 Terabytes.

Protected Virtual Addressing Mode (PVAM)
80386 operates in two memory management modes in PVAM. They are given as follows
1. Non Paged mode:

MMU operates similar to 80286.Virtual addresses are represented with a selector component and an offset component. The selector component is used to index a descriptor in a descriptor table. The descriptor contains the 32 bit physical base address for the segment. The offset part of the virtual address is added to the base address to produce the actual physical address. The offset part of a virtual address can be 16 or 32 bits so segment can be as large as 4 gigabytes.

Hence the virtual memory size is

2 13 *2*2 32 = 2 46 bytes or 64 Terabytes.

Advantage of segmentation of memory: Segments corresponds to code and data structures in the program. Hence segmentation is useful.

Limitation of segmentation of memory : If we need only a part of memory, even then we have to swap the whole segment content. This will increase the time for execution.

Paged mode:

In this mode, instead of segments, 4 kbytes of fixed page length are used.
Limitation : Pages do not correspond to the logical structure of the program.
Advantage : Pages can be quickly swapped.

Conversion of linear address into physical address:

Fig.  33.3  Address translation mechanism in 80386 paging unit
Page directory
Page directory entry
Page table entry
P = entry can be used in address translation

P = 1   Yes
P = 0   No

A  = accessed
        A  = 1 page is accessed
             = 0 page is unaccessed

D = dirty bit

Dirty bit is set before any write operation to the page.
Dirty bit is undefined for page directory entries.

U/S and R/W bits are used to provide protection.

U/S
R/W
permitted for level3

permitted for levels 2,1,0

0
0
None
Read/Write
0
1
None
Read/Write
1
0
Read only
Read/Write
1
1
Read-write
Read/Write