Module 4 : Architecture of Advanced Microprocessor

Lecture 32 : Architecture of Intel 80286

Architecture of Intel 80286

Key Features -

  • 16-bit date bus
  • 24-bit non-multiplexed bus
  • Packaged in a 68-pin ceramic pack

80286 has 2 24 = 16 M Byte of physical memory accessibility

Fig 32.1  Basic Architecture of 80286
Memory Bank

Memory of 80286 is setup as an odd bank and an even bank, just as it is for the 8086. The even bank is enabled when A 0 is low and the odd bank is enabled when   is low. To access an aligned word, both A 0    will be low.

Fig 32.2   Memory banks in 80286

Memory Addressing in 80286
  1.  Real Addressing Mode - It is just like as in 8086. Address is 20 bit with 16 bit segment and 16 bit offset. When 80286 is hardware reset, it automatically enters real address mode.
  2. Protected Virtual Addressing Mode (PVAM) - In this we have 1 GByte of virtual memory and 16 Mbyte of physical memory. The address is 24 bit. To enter PVAM mode, Processor Status Word (PSW) is loaded by the instruction LPSW.

Fig 32.3   Load Processor Status Word

PE - Protection Enable
MP - Monitor Processor Extension
EM - Emulate Processor Extension
TS - Task Switch

Hardware reset is the only way to come out of protected mode.

80286 Memory Management Scheme
Memory is organized into logical segments. Segment size can be anywhere between 1 Byte to 16 KByte. All 24 address pins are active and 16 MByte of physical memory is available.

Descriptor

It is 8-byte quantity. Each segment has a descriptor. There are two main types of descriptor -

  • Segment Descriptor
  • System control Descriptor
Format of a Descriptor
Fig  32.4  Descriptor Format

Access Right byte definition

7
Present (P)

1 - Yes
0 - No

6-5
Descriptor Privilege level (DPL)

0 to 3

4
Segment Descriptor

1 - Segment
0 - Control

For segment descriptor, i.e. for S = 1, bits 3-0 have the following meaning -

3

E

0 - Data
1 - Code

2

Expansion/ Confirming

If code, Confirming: 1 means 'Yes', 0 means 'No'
If data, Expand down: 1 - Yes, 0 - No (normal case)

1

R / W

If code, Readable: 1 - Yes, 0 - Not
If data, Writeable: 1 - Yes, 0 - Not

0

Accessed (A)

A = 0, Not accessed
A = 1, Accessed

Descriptors are contained in a descriptor table. There are two categories of descriptor table - global and local. A system has only one global descriptor table or GDT. A local descriptor table or LDT is set up in the system for each task or closely related group of tasks. Each task can have its own descriptor table and memory area defined by the descriptors in it.

Accessing Segments

The 80286 microprocessor keeps the base address and limits for the descriptor tables currently in use in internal registers. These registers are load descriptor table register (LDTR) and global descriptor table register (GDTR). Descriptor in memory is addressed by adding segment selector to these registers. The descriptors contain the base address of segments, which when added with the offset in the virtual address points to the required memory location.

Accessing a Segment of Higher Privilege Level

Tasks operate at the lowest privilege level. Usually, segments at a lower privilege level are not allowed to access segments at a higher privilege level directly. However, a lower level segment can access a higher level segment indirectly by a Gate Descriptor. The details of a gate descriptor are given herewith.

Fig 32.5  Privilege Level
Gate Description Format

Fig  32.6  Gate Descriptor Format

Name

Value

Description

Type

4

Call gate

.

5

Task gate

.

6

Interrupt gate

.

7

Trap gate

P

0

Descriptor contents are NOT valid

.

1

Descriptor contents are valid

DPL

0-3

Descriptor privilege level

Word Count

0-31

Number of words to copy from callers stack to called procedures stack. Only used with called gates.

Destination Selector

16-bit Selector

Selector to target code segment (call, interrupt, task gates)

Selector to target task state segment (task gate)

Destination Offset

16-bit Offset

Entry point within the target code segment

 
Task Switching and Task gates

Each task in a PVAM system has a 22-word task state segment (TSS) associated with it. A TSS holds copies of all registers and flags, the selector for the tasks' LDT, and a link to the TSS of the previously executing task.

Descriptors for each task state segment are kept in the global descriptor table. A task register (TR) in the 80286 holds the selector and the task state segment descriptor for the currently executing task. The load task register (LTR) instruction can be used to initialize the task register to the task state segment for a particular task. During a task switch the task register is automatically loaded with the selector and descriptor for the new task.

Method of Task Switching

  1. Long jump or call instructions that contain a selector which points to the Task State segment descriptor
  2. IRET
  3. Selectors in a long jump or call points to a task gate
  4. Interrupt occurs and the vectors point to a task gate descriptor
80286 Interrupt Handling

Real addressing mode has 256 interrupts with types 0-255. Each interrupt takes 4 bytes, so we have to reserve 1KByte of memory for interrupt.

In PVAM mode also we have 256 interrupts but it is not assigned a fixed memory. The interrupt descriptor table can be anywhere in the physical memory. Base address of interrupt descriptor table is stored in interrupt descriptor table register (IDTR). The particular descriptor is accessed as follows -

(Interrupt Type * 8) + IDTR Descriptor