Module 3 : Introduction to PIC Microcontrollers

Lecture 26 : I 2C Communication in PIC Microcontroller:

 I2C Communication in PIC Microcontroller

I 2C stands for Inter-Integrated circuit. I 2C communication is a two wire bi-directional interface for connecting one or more master processors with one or more slave devices, such as an EEPROM, ADC, RAM, LCD display, DAC, etc. I 2C interface requires two open drain I/O pins, viz. SDA (Serial Data) and SCL (Serial Clock).

The reason for open drain connection is that the data transfer is bi-directional and any of the devices connected to the I 2C bus can drive­ the data line (SDA). The serial clock line (SCL) is usually driven by the master. Since SDA and SCL pins are open drain pins, external pull-up resistances are required for operation of I 2C bus.

A typical I2C  bus showing the connection of multi-master and multi-slave configuration is shown in the following figure.
Fig 26.1 Multimaster Multislave Connection

Some conventions are followed in I2C communication. Let us assume that there is one master and one slave and 8-data bits are sent. We will initially assume that the master is the transmitter and the slave is the receiver. The clock is driven by the master. On receiving 8-bits, an acknowledgement bit is driven by the receiver on SDA line. The acknowledgement bit is usually Low (0). The following diagram shows the data communication pattern having 8 data bits and one acknowledgement bit.

Fig 26.2 Timing diagram for data transfer

The following features are to be noted -

  1. SDA line transmits/ receives data bits. MSB is sent first.
  2. Data in SDA line is stable during clock (SCL) high. A new bit is initiated at the negative clock transition after a specified hold time.
  3. Serial clock (SCL) is driven by the master.
  4. An acknowledgement bit (0) is driven by the receiver after the end of reception. If the receiver does not acknowledge, SDA line remains high (1).

I2C  bus transfer consists of a number of byte transfers within a START condition and either another START condition or a STOP condition. During the idle state when no data transfer is taking place, both SDA and SCL lines are released by all the devices and remains high. When a master wants to initiate a data transfer, it pulls SDA low followed by SCL being pulled low. This is called START condition. Similarly, when the processor wants to terminate the data transfer it first releases SCL (SCL becomes high) and then SDA. This is called a STOP condition. START and STOP conditions are shown in the diagram as follows.

Fig 26.3 Timing diagram for START and STOP Conditions

START and STOP conditions are unique and they never happen within a data transfer.

Data Communication Protocol:
In I2C communication both 7-bit and 10-bit slave addressing are possible. In 7-bit addressing mode 128 slaves can be interfaced with a single master. Similarly, in 10-bit addressing mode, 1024 slaves can be interfaced with the master. We will discuss here 7-bit addressing mode only. 10-bit addressing mode is similar to 7-bit addressing except from the fact that the number of address bits is more.

Following a 'start' condition, the master sends a 7-bit address of the slave on SDA line. The MSB is sent first. After sending 7-bit address of the slave peripheral, a R/ (8th bit) bit is sent by the master. If R/ bit is '0', the following byte (after the acknowledgement bit) is written by the master to the addressed slave peripheral. If R/=1, the following byte (after the acknowledgement bit) has to be read from the slave by the master.

After sending the 7-bit address of the slave, the master sends the address (usually 8 bit) of the internal register of the slave wherefrom the data has to be read or written to. The subsequent access is automatically directed to the next address of the internal register.

The following diagrams give the general format to write and read from several peripheral internal registers.

Fig 26.4  Data transfer protocol for writing to a slave device
R/ (Read / Write) bit indicates whether the data is to be written by the master or read by the master. If R/ is 1, the subsequent data are to be read by the master. If R/ = 0, the subsequent data are to be written by the master to the addressed slave. It has to be noted that the slave address is sent first, following a 'start' condition. The addressed slave responds by acknowledging and gets ready for data transfer.
If data has to be read from a specific address of the slave device, the master sends the 7-bit address of the slave first following a 'start' condition. R/ bit is sent as 'low'. The addressed slave acknowledges by pulling the ACK line low. The master then sends the 8-bit internal address of the slave from which data has to be read. The slave acknowledges. Since R/ bit was initially 0, the master is in the write mode. To change this to read mode, the 'start' condition is again generated followed by 7-bit address of the slave with R/ = 1. The slave acknowledges. The slave then sends data from previously specified internal address to the master. The master acknowledges by pulling ACK bit low. The data transfer stops when the master does not acknowledge the data reception and a 'stop' condition is generated.