Module 3 : Introduction to PIC Microcontrollers

Lecture 24 : Synchronous Serial Port (SSP) Module:

 

Most of mid range PIC microcontrollers include a Synchronous Serial Port (SSP) Module. The discussion in this section is relevant to PIC16C74A only. SSP Module section can be configured in either of the following two modes.

  • Serial Peripheral Interface  (SPI)
  • Inter Integrated Circuit (I2C)
Either of these modes can be used to interconnect two or more PIC chips to each other using a minimal number of wires for communication. Alternatively, either can be used to connect a PIC microcontroller to a peripheral chip. When I 2C mode is selected, the peripheral chip must also have an I 2C  interface. On the other hand, the SPI mode provides the clock and serial data lines for direct connection to shift registers. This leads to increased I/O interface capability and an arbitrary number of I/O devices can be connected to a PIC microcontroller. SPI can also achieve data rate significantly higher than  I2C. Both the communication methods are synchronous, i.e., the data transfer is synchronized with an explicit clock signal.

Two special purpose registers control the synchronous serial port (SSP) operations. These registers are:

  • SSPCON (Synchronous Serial Port Control Register), Address: 14H
  • SSPSTAT(Synchronous Serial Port status Register), Address:  94H
Serial Peripheral Interface (SPI)
Port-C three pins, viz., RC5/SDO, RC4/SDI and RC3/SCK/SCL are mainly used for SPI mode. In addition, one Port-A pin, viz.,   RA5/ /AN4 is used for slave select. The schematic block diagram of SPI is shown in the figure
Fig 24.1 Schematic diagram under SPI Mode
The SPI port requires RC3/SCK pin to be an output that generates the clock signal used by the external shift registers. When SPI is configured in the slave  mode, RC3/SCK pin works as the input for the clock.

When a byte is written to SSPBUF register, it is shifted out of RC5/SDO pin in synchronous with the emitted clock pulses on RC3/SCK pin. The MSB of SSPBUF is the first bit to appear on RC5/SDO pin. Simultaneously, the same write to SSPBUF also initiates the 8 bit data reception into SSPBUF of whatever appears on RC4/SDI pin at the time of rising edges of the clock on SCK pin. Hence shifting-in and shifting-out of data occur simultaneously.

Fig 24.2  SPI Master / Slave Connection
The schematic diagram of SPI Master/Slave connection is shown in the figure.

Timing diagram for data transfer in 'Master mode' :

SSPIF interrupt flag is cleared by the user software if already in the set mode. The interrupt is enabled. Any write to SSPBUF initiates the data transfer, i.e., transmission and reception. The clock pulses (8 clock pulses) are output through SCK pin. The data is received through SDI. When CKP=1 (SSPCON<4>), data changes at SDO at negative clock transition and is read through SDI at positive clock transition. The idle state of clock is high. If CKP=0, data appears at SDO at positive clock transition and is read through SDI at negative clock transition. The idle state of the clock is low. These are shown in the following diagrams.

(i)  Timing diagram for CKP=1

(ii)  Timing diagram for CKP=0

Fig 24.3 Timing Diagram under SPI mode