Module 3 : Fabrication Process and Layout Design Rules
Lecture 13 : Layout Design Rules
 
13.3 Layer Representations
With increase of complexity in the CMOS processes, the visualization of all the mask levels that are used in the actual fabrication process becomes inhibited. The layer concept translates these masks to a set of conceptual layout levels that are
easier to visualize by the circuit designer. From the designer's viewpoint, all CMOS designs have the following entities:
 

  Two different substrates and/or wells: which are p-type for NMOS and n-type for PMOS.

  Diffusion regions (p+ and n+): which defines the area where transistors can be formed. These regions are also called active     areas. Diffusion of an inverse type is needed to implement contacts to the well or to substrate. These are called select     regions.

  Transistor gate electrodes : Polysilicon layer

  Metal interconnect layers

  Interlayer contacts and via layers.

 
The layers for typical CMOS processes are represented in various figures in terms of:

   A color scheme (Mead-Conway colors).
   Other color schemes designed to
    differentiate CMOS structures.
   Varying stipple patterns
   Varying line styles

 
An example of layer representations for CMOS inverter using above design rules is shown below-
 
Figure 13.32 :CMOS Inverter Layout
Figure 13.31 Mead ­Conway Color coding for layers.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
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